TWI575111B - 蝕刻經錫或錫合金填充之凹陷結構的方法 - Google Patents

蝕刻經錫或錫合金填充之凹陷結構的方法 Download PDF

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TWI575111B
TWI575111B TW101106577A TW101106577A TWI575111B TW I575111 B TWI575111 B TW I575111B TW 101106577 A TW101106577 A TW 101106577A TW 101106577 A TW101106577 A TW 101106577A TW I575111 B TWI575111 B TW I575111B
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tin
tin alloy
recessed structure
substrate
etching solution
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尼爾 烏德
德克 特維斯
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德國艾托特克公司
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
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    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
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    • C23F1/44Compositions for etching metallic material from a metallic material substrate of different composition
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Description

蝕刻經錫或錫合金填充之凹陷結構的方法
本發明係關於印刷電路板、IC基板及類似物之製造,更特定言之錫及錫合金之蝕刻。
長期以來,在諸如印刷電路板(PCB)與IC基板之電子設備製造中,錫及錫合金作為可焊性表面或焊劑材料。
近期之發展係錫及錫合金以焊劑材料藉由電鍍至電子設備之凹陷結構中之沉積物。錫或錫合金沉積可藉由圖形電鍍或板面電鍍進行電鍍。
製造焊劑沉積之板面電鍍方法揭示於EP2180770A1中。
具諸如由銅製成之結合襯墊之基板表面係鍍有焊劑遮罩材料,並且焊劑遮罩材料中形成開孔以曝露結合襯墊。該等開孔在此處係指凹陷結構。其它類型的凹陷結構係貫穿電子設備之介電基板至抗蝕材料或貫穿一層以上之該等層體形成。
然後,將導電種晶層沉積於整個基板表面與凹陷結構表面上。然後藉由電鍍將錫或錫合金沉積於導電種晶層上,以填充該等凹陷結構。
然而,當以錫或錫合金完全填充凹陷結構時,同時將一定量的錫或錫合金沉積於未覆蓋凹陷結構的導電種晶層表面上。為完全填充凹陷結構,始終需要此一過量的錫或錫合金層。
然後,去除填充有錫或錫合金之凹陷結構之頂部之該過 量錫或錫合金。
此任務可藉由將抗蝕劑沉積於與該等凹陷結構對準的錫或錫合金表面上,然後蝕刻掉未被抗蝕劑覆蓋的過量錫或錫合金層來達成。此方法揭示於US 2006/0219567 A1中。此方法之弊端諸多:a)經錫或錫合金填充之所得凹陷結構具有高於周圍焊劑遮罩材料之高度。此導致於隨後製程步驟中藉由(網板-)印刷額外焊劑材料所沉積的焊劑材料未對準及b)此方法需要更多製程步驟。
在EP 2180770 A1中揭示之用於製造焊劑沉積之板面電鍍方法需要一種用於錫或錫合金的蝕刻溶液,其可控制到不需要抗蝕劑之程度。當去除過量錫或錫合金層時,蝕刻侵蝕必須相當均勻,以使得經錫或錫合金填充之凹陷結構之表面光滑與平整。
該項技術中已知之用於錫及錫合金的水性蝕刻溶液(Jordan:The Electrodeposition of Tin and its Alloys,1995,373-377頁)由於電鍍於凹陷結構中的錫或錫合金之去除速度係高於焊劑遮罩材料頂部之過量錫或錫合金層而失敗。此於經錫或錫合金填充之凹陷結構中產生凹坑(圖1)。須避免此等凹坑,因為隨後步驟中會導致不穩定且不可靠焊接點。
因此本發明之目的係提供一種使經錫或錫合金填充之凹陷結構平坦化之避免凹坑形成之方法。
本發明之第二目的係提供經平坦化錫或錫合金焊劑沉積填充之凹陷結構,以製造穩定可靠之焊點。
該等目的係藉由蝕刻過量錫及錫合金沉積之方法達到,其包括以下步驟:a.提供一基板,該基板具有經錫或錫合金填充之凹陷結構與過量錫或錫合金層,b.提供由氫氧根離子源與經硝基取代的芳族磺酸組成之pH值大於7之水性蝕刻溶液,c.使該基板與該水性蝕刻溶液接觸,以去除該等經錫或錫合金填充之凹陷結構頂部之該過量錫或錫合金層。
基板(101)包含諸如由銅製成之結合襯墊(102)與具有曝露結合襯墊(102)之開孔之焊劑遮罩材料(103)。含銅之導電種晶層(104)覆蓋焊劑遮罩材料(103)表面與結合襯墊(102)。該等開口係經錫或錫合金填充且類似於經錫或錫合金填充之凹陷結構(105a)及經填充之凹陷結構(105a)上方與焊劑遮罩材料(103)頂部的過量錫或錫合金層(106)。
使過量錫或錫合金層(106)與水性蝕刻溶液接觸,該水性蝕刻溶液係由氫氧根離子源與經硝基取代的芳族磺酸組成且pH值大於7。pH值範圍為7-14,更佳11-14。
氫氧根離子源選自由以下組成之群:LiOH、NaOH、KOH、NH4OH與諸如乙醇胺、二乙醇胺及三乙醇胺之有機氫氧源及其混合物。最佳氫氧根離子源係NaOH。氫氧根離子濃度為0.5-100 g/l,更佳10-40 g/l及最佳20-30 g/l。
經硝基取代之芳族磺酸較佳選自由以下組成之群:鄰硝 基苯磺酸、間硝基苯磺酸、對硝基苯磺酸及其等與鈉及鉀的對應鹽及其混合物。經硝基取代之芳族磺酸、其鹽及其混合物的濃度為1-100 g/l,更佳為20-80 g/l及最佳為40-60 g/l。
該水性蝕刻溶液可進一步包含潤濕劑。較佳之潤濕劑係選自包括下列之群:烷基化或芳基化環氧乙烷-環氧丙烷共聚物、烷基硫酸酯、烷基磺酸酯、芳烷基磺酸酯與低發泡非離子或陰離子表面活性劑。
進行步驟c時,水性蝕刻劑溫度係保持在20-90℃之間,更佳30-70℃。
進行步驟c時,使基板與水性蝕刻溶液接觸10-240秒,更佳60-120秒。
可藉由將該基板浸於該水性蝕刻溶液中、藉由用該水性溶液水平溢流加工該基板或藉由將該水性蝕刻溶液噴塗於該基板上來使基板與水性蝕刻溶液接觸。使基板與水性蝕刻溶液接觸之最佳方法係藉由利用噴塗或溢流施用來水平加工。
當具有凹陷結構之基板經受電鍍時會顯現寬廣的電流密度範圍,尤其係當將錫或錫合金電鍍於凹陷結構內及該基板頂部上時。電鍍時寬廣的電流密度範圍導致所沉積錫或錫合金具有非均質晶粒結構。凹陷結構內及該凹陷結構頂部之晶粒尺寸比焊劑遮罩材料頂部上之晶粒尺寸大很多。該項技術中已知之水性蝕刻溶液侵蝕尺寸較大的錫或錫合金晶粒之速度比侵蝕小尺寸晶粒快很多。該技術中已知之 用於錫及錫合金之蝕刻溶液之蝕刻步驟結果顯示於圖1中。由於作用於較大尺寸晶粒上之蝕刻侵蝕較快,因此經具有較大晶粒尺寸的錫或錫合金填充之凹陷結構中會形成凹坑。經錫或錫合金填充之凹陷結構中之該等凹坑係不可接受,其會在後續製程步驟中導致不穩定且不可靠之焊接點。
不依賴於晶粒尺寸,根據本發明之方法會產生作用於錫與錫合金沉積之均勻蝕刻侵蝕。根據本發明之方法之結果顯示於圖2中。由於均勻蝕刻侵蝕,故在經錫或錫合金填充之凹陷結構中未形成非所需之凹坑。
實例
本發明將參照以下非限制性實例進行闡明。
實例中所用基板包含直徑100 μm及深度30 μm之圓柱形凹陷結構。該等凹陷結構壁係由銅結合襯墊102(底部)與焊劑遮罩材料103(側壁)組成。
將由銅製成之導電種晶層104沉積於凹陷結構中與焊劑遮罩材料103頂部。然後藉由電鍍,使凹陷結構填充有錫105a。為了完全填充凹陷結構,需電鍍過量錫或錫合金層106(板面電鍍)。
過量錫層106係藉由下述不同水性蝕刻溶液去除。
利用光學顯微鏡觀察經不同蝕刻溶液處理之基板之橫截面。將凹坑用作蝕刻過量錫或錫合金層(106)之量度。藉由測量凹陷結構頂部與凹陷結構中錫或錫合金沉積頂部之間的距離來量化凹坑。在凹陷結構中心處測量距離。凹坑即 為不合格,需避免。
實例1(對比)
使用由50 g/l硝酸與50 g/l九水合硝酸鐵組成的酸性水性蝕刻溶液。在溫度30℃下,將基板浸於該水性蝕刻溶液中60 s。將過量錫層106完全去除。
經錫105b填充之凹陷結構具有20 μm的凹坑。因此,不能獲得穩定可靠之焊接點。
實例2(對比)
使用由50 g/l甲磺酸與50 g/l間硝基苯磺酸鈉鹽組成的酸性水性蝕刻溶液。在溫度30℃下,將基板浸於該水性蝕刻溶液中60 s。將過量錫層106完全去除。
經錫105b填充之凹陷結構具有20 μm的凹坑。因此,不能獲得穩定可靠之焊接點。
實例3(本發明)
使用由50 g/l氫氧化鈉與50 g/l間硝基苯磺酸鈉鹽組成的酸性水性蝕刻溶液。在溫度50℃下,將基板浸於該水性蝕刻溶液中60 s。將過量錫層106完全去除。
經錫105b填充之凹陷結構未顯示凹坑。因此,可獲得穩定可靠之焊接點。
101‧‧‧基板
102‧‧‧結合襯墊
103‧‧‧焊劑遮罩材料
104‧‧‧導電種晶層
105a‧‧‧凹陷結構
105b‧‧‧錫
106‧‧‧過量錫或錫合金層
圖1a與1b顯示經錫填充之凹陷結構根據先前技術已知的蝕刻方法進行的蝕刻。
圖2a與2b顯示經錫填充之凹陷結構根據本發明進行的蝕刻。
101‧‧‧基板
102‧‧‧結合襯墊
103‧‧‧焊劑遮罩材料
104‧‧‧導電種晶層
105b‧‧‧錫

Claims (10)

  1. 一種用於蝕刻過量錫或錫合金沉積物之方法,其包括以下步驟:a.提供基板(101),該基板具有經錫或錫合金填充之凹陷結構(105a)與過量錫或錫合金層(106),b.提供由氫氧根離子源與經硝基取代的芳族磺酸組成之pH值大於7之水性蝕刻溶液,c.使該基板與該水性蝕刻溶液接觸,以去除經錫或錫合金填充之該等凹陷結構(105a)頂部之該過量錫或錫合金層(106)。
  2. 如請求項1之方法,其中該氫氧根離子源係選自由LiOH、NaOH、KOH與NH4OH組成之群。
  3. 如請求項2之方法,其中該氫氧根離子之濃度係20至30 g/l。
  4. 如請求項1之方法,其中該經硝基取代的芳族磺酸係選自由鄰硝基苯磺酸、間硝基苯磺酸、對硝基苯磺酸及其等混合物組成之群。
  5. 如請求項4之方法,其中該經硝基取代的芳族磺酸之濃度係30至60 g/l。
  6. 如請求項1之方法,其中該pH值係11至14。
  7. 如請求項1之方法,其中該水性蝕刻溶液進一步含有潤濕劑。
  8. 如請求項1之方法,其中在步驟c期間,該水性蝕刻劑之溫度係保持在30至70℃之間。
  9. 如請求項1之方法,其中在步驟c中,使該基板與該水性蝕刻溶液接觸60至120秒。
  10. 如請求項1之方法,其中該基板係藉由利用噴塗或溢流施用水平加工來與該水性蝕刻溶液接觸。
TW101106577A 2011-03-22 2012-02-29 蝕刻經錫或錫合金填充之凹陷結構的方法 TWI575111B (zh)

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Publication number Priority date Publication date Assignee Title
US4687545A (en) * 1986-06-18 1987-08-18 Macdermid, Incorporated Process for stripping tin or tin-lead alloy from copper

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US2200782A (en) * 1935-05-23 1940-05-14 Metal & Thermit Corp Detinning
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US4397753A (en) * 1982-09-20 1983-08-09 Circuit Chemistry Corporation Solder stripping solution
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* Cited by examiner, † Cited by third party
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