TWI569401B - High frequency module - Google Patents
High frequency module Download PDFInfo
- Publication number
- TWI569401B TWI569401B TW102122300A TW102122300A TWI569401B TW I569401 B TWI569401 B TW I569401B TW 102122300 A TW102122300 A TW 102122300A TW 102122300 A TW102122300 A TW 102122300A TW I569401 B TWI569401 B TW I569401B
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- semiconductor substrate
- main surface
- substrate
- module
- resin layer
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Description
本發明係關於一種在配線基板之兩主面分別構裝零件而成之模組。
以往,作為搭載於行動電話或行動資訊終端等之資訊通訊終端之模組,如圖6所示之習知模組500,已知有半導體基板503被樹脂層504被覆者,該半導體基板503係面朝下(face down)構裝於豎設有外部連接用之柱狀之連接端子502(電極柱)之配線基板501之一主面上以電氣連接於連接端子502。此種模組500例如以下述方式形成。亦即,在半導體基板503面朝下構裝於豎設有連接端子502之配線基板501之一主面上後,在配線基板501之一主面上以被覆連接端子502及半導體基板503之方式填充樹脂,藉此形成樹脂層504。接著,以連接端子502之上端面及半導體基板503之背面露出之方式研磨或研削樹脂層504之上面,藉此完成模組500。
專利文獻1:日本特開2002-343904號(參照段落0013、圖1等)
然而,近年來,資訊通訊終端之小型、薄型化及高機能化急速地發展,作為搭載於資訊通訊終端之模組,期盼藉由零件構裝密度提高而謀求高機能化且抑制高度變高之模組。又,在零件構裝密度提高而謀求
模組之高機能化之情形,由於會有來自形成在半導體基板(構裝在搭載於資訊通訊終端之模組)之既定電路之不需要輻射對構裝於模組之其他零件、或搭載於資訊通訊終端之其他模組等造成影響之虞,因此需謀求適當之對策。
本發明係有鑑於上述課題而構成,其第1目的在於提供一種零件構裝密度提高而謀求高機能化且高度變低之模組。又,第2目的在於提供一種可抑制來自構裝在模組之半導體基板之不需要輻射造成之影響之技術。
為了達成上述第1目的,本發明之模組,係在配線基板之兩主面分別構裝零件而成,其特徵在於,具備:第1零件層,係設在該配線基板之一主面,在該一主面作為該零件僅面朝下構裝半導體基板而形成;以及第2零件層,係設在該配線基板之另一主面,在該另一主面構裝複數個該零件而形成;該第1零件層之厚度形成為較該第2零件層之厚度薄。
在以上述方式構成之發明,藉由在配線基板之兩主面分別構裝零件提高零件構裝密度以謀求模組之高機能化。另一方面,在配線基板之一主面作為零件僅面朝下構裝半導體基板而形成且設在該一主面之第1零件層之厚度形成為較在配線基板之另一主面構裝複數個零件而形成且設在該另一主面之第2零件層之厚度薄。
亦即,即使面朝下構裝在配線基板之一主面之半導體基板之背面側被研磨或研削,半導體基板之電氣特性亦不會大幅變化,因此以形成在表面側之既定電路不受損之方式研磨或研削該半導體基板之背面側,藉此能使半導體基板變薄。因此,設在配線基板之一主面之第1零件層,
半導體基板之背面側以使半導體基板變薄,藉此能將第1零件層之厚度形成為較第2零件層之厚度薄。
是以,儘管藉由在配線基板之兩主面分別構裝零件謀求高機能化,在配線基板之一主面僅面朝下構裝半導體基板而形成之第1零件層之厚度形成為較在配線基板之另一主面構裝複數個零件而形成之第2零件層之厚度薄,藉此可提供零件構裝密度提高而謀求高機能化且高度變低之模組。
又,該第1零件層之厚度較構裝在該配線基板之另一主面側之該各零件中之離該另一主面之高度最低之該零件之高度薄亦可。
若以上述方式構成,則第1零件層之厚度形成為較構裝在配線基板之另一主面側之各零件中之離另一主面之高度最低之零件之高度薄,因此能進一步有效地使模組高度變低。
又,為了達成上述第2目的,本發明之模組,該第1零件層具備外部連接用之複數個柱狀之連接端子,該複數個連接端子豎設在該配線基板之一主面且電氣連接於構裝在該一主面之該半導體基板;該複數個連接端子包含接地用之端子。
在以上述方式構成之發明,第1零件層具備外部連接用之複數個柱狀之連接端子,該複數個連接端子豎設在配線基板之一主面且電氣連接於構裝在該一主面之半導體基板,但複數個連接端子包含接地用之端子,第1零件層形成為較第2零件層之薄,因此若與外部連接用之各連接端子設在第2零件層之情形相較,各連接端子形成較短。
是以,包含接地用之端子之外部連接用之複數個連接端子形
成較短,藉此降低各連接端子之寄生電感,因此可強化模組搭載於外部之母基板等時之外部之接地電極與半導體基板之電氣連接。又,模組搭載於外部之母基板等時,形成較薄之第1零件層所具備之半導體基板與配置在母基板與模組之配線基板之間且兩基板具備之接地電極接近配置,因此來自半導體基板之不需要輻射容易被母基板及配線基板之接地電極吸收,可抑制來自構裝在模組之半導體基板之不需要輻射造成之影響。
又,構裝在該兩主面之該各零件中之構裝在該配線基板之一主面之該半導體基板之俯視下面積,與其他該各零件之俯視下面積相較為最大亦可。
若以上述方式構成,雖設在配線基板之一主面之第1零件層形成為較設在另一主面之第2零件層薄,但由於形成較薄之第1零件層具備之半導體基板之俯視下面積,與其他各零件之俯視下面積相較為最大,因此可防止因配線基板彎曲導致模組產生彎曲。
又,該第1零件層具備設在該一主面之第1樹脂層,該第1樹脂層以該配線基板之一主面側之該半導體基板之背面露出之方式被覆該半導體基板之側面;該第2零件層具備設在該另一主面之第2樹脂層,該第2樹脂層被覆該配線基板之另一主面側之該各零件;形成該第1樹脂層之樹脂之線膨脹係數較形成該第2樹脂層之樹脂之線膨脹係數大亦可。
若以上述方式構成,第1零件層具備之第1樹脂層形成為較第2零件層具備之第2樹脂層薄,但第1樹脂層由線膨脹係數較形成第2樹脂層之樹脂大之樹脂形成,藉此可縮小厚度較薄之第1樹脂層之收縮力之大小與厚度較厚之第2樹脂層之收縮力之大小之差,因此可抑制在模組
產生起因於樹脂收縮之彎曲。
又,在與該配線基板之一主面對向之該半導體基板之表面形成有既定電路;在該配線基板之另一主面側之該各零件包含陶瓷積層晶片零件亦可。
若以上述方式構成,則在配線基板之另一主面側之各零件包含無法由研磨或研削等變薄之陶瓷積層晶片零件,第2零件層之厚度無法形成為較該晶片零件之高度薄,但藉由將作為零件僅構裝半導體基板而形成之第1零件層之厚度形成為較第2零件層之厚度薄,可提供高度低之實用模組。
根據本發明,在配線基板之一主面僅面朝下構裝半導體基板而形成之第1零件層之厚度形成為較在配線基板之另一主面構裝複數個零件而形成之第2零件層之厚度薄,藉此可提供零件構裝密度提高而謀求高機能化且高度變低之模組。
100,100a‧‧‧模組
101‧‧‧配線基板
101a‧‧‧一主面
101b‧‧‧另一主面
102‧‧‧第1零件層
103‧‧‧第2零件層
104‧‧‧半導體基板(零件)
105‧‧‧陶瓷積層晶片零件(零件)
106,106a‧‧‧連接端子
107‧‧‧第1樹脂層
108‧‧‧第2樹脂層
圖1係顯示具備本發明之模組之模組搭載裝置之圖。
圖2係顯示圖1之模組搭載裝置具備之模組之製造方法之圖,(a)~(e)係分別顯示不同狀態。
圖3係顯示連接端子之一例之主要部分放大圖。
圖4係顯示連接端子之另一例之主要部分放大圖。
圖5係顯示模組之變形例之圖。
圖6係習知模組之剖面圖。
參照圖1~圖3說明本發明之一實施形態。圖1係顯示具備本發明之模組之模組搭載裝置之圖,圖2係顯示圖1之模組搭載裝置具備之模組之製造方法之圖,(a)~(e)係分別顯示不同狀態。又,圖3係顯示連接端子之一例之主要部分放大圖。
(模組搭載裝置)
模組搭載裝置1,如圖1所示,具備母基板2、構裝在母基板2之模組100、及為了保護母基板2與模組100之連接部而由樹脂形成之底填樹脂層3,搭載於行動電話或行動資訊終端等之資訊通訊終端。
母基板2,包含接地用之接地電極之配線圖案(省略圖示)設在其內部,配線圖案係透過通孔導體(省略圖示)等連接於形成在母基板2之構裝面2a之構裝用電極2b。又,母基板2由玻璃環氧樹脂或液晶聚合物等之樹脂材料或陶瓷材料等之一般基板形成用之材料形成。又,配線圖案及通孔導體由Ag或Cu、Au等之導電材料形成,以通孔導體等連接配線圖案以將各種電路形成在母基板2內亦可。
又,模組100,形成在外部連接用之連接端子106之前端面及半導體基板104之背面之金屬膜109係藉由使用焊料H連接於母基板2之構裝用電極2b而構裝於構裝面2a。此外,本實施形態中,形成在半導體基板104之背面之金屬膜109係藉由焊料H連接於構裝用電極2b,該構裝用電極2b連接於設在母基板2之電極。
底填樹脂層3係藉由在構裝於母基板2之構裝面2a之模組100與母基板2之間之間隙填充例如環氧樹脂而形成。
(模組)
模組2係藉由在配線基板101之兩主面101a,101b分別構裝半導體基板104或陶瓷積層晶片零件105等之零件而形成為Bluetooth(註冊商標)模組或無線LAN模組、天線開關模組等之高頻模組,如圖1所示,具備配線基板101、設在配線基板101之一主面101a且在該一主面101a作為零件僅面朝下構裝半導體基板104而形成之第1零件層102、設在配線基板101之另一主面101b且在該另一主面101b構裝複數個晶片零件105而形成之第2零件層103。
配線基板101由玻璃環氧樹脂或液晶聚合物等之樹脂基板、陶瓷(LTCC)基板、玻璃基板等一般基板構成,視模組100之使用目的,配線基板101形成為單層基板及多層基板之任一者亦可。又,在配線基板101之兩主面101a,101b形成有用以構裝零件等之複數個構裝用電極101c,各構裝用電極101c係透過通孔導體(省略圖示)等與藉由Ag或Cu、Au等之導電材料設在配線基板101之內部且包含接地電極等之配線圖案(省略圖示)電氣連接。
此外,例如,在配線基板101由LTCC(Low Temperature Co-fired Ceramics)多層基板形成之情形,配線基板101係以下述方式形成。亦即,首先,準備氧化鋁及玻璃等之混合粉末與有機結合劑及溶劑等一起混合後之漿料形成為片狀之陶瓷坯片。接著,在此陶瓷坯片之既定位置藉由將含有Ag或Cu等之導體糊填充於雷射加工等所形成之通孔形成層間連接用之通孔導體,藉由使用導體糊之印刷形成各種配線圖案。接著,各陶瓷坯片積層、壓接形成之陶瓷積層體在約1000℃前後之低溫進行所謂低溫
燒成,藉此形成配線基板101。
第1零件層102具備外部連接用之柱狀之複數個連接端子106,該複數個連接端子106係藉由在配線基板101之一主面101a豎設複數個棒狀之Cu等之金屬構件而形成,電氣連接於構裝在一主面101a之半導體基板104,各連接端子106之至少一個係形成為接地用之端子。又,第1零件層102具備之半導體基板104,藉由在與配線基板101之一主面101a對向之表面形成省略圖示之既定電路,構成處理RF訊號或基頻訊號之系統IC。又,半導體基板104具有從Si等之半導體晶圓裁切出之裸晶片構造或晶圓等級晶片尺寸封裝體(WL-CSP)構造,面朝下構裝於配線基板101之一主面101a。
又,第1零件層102具備設在該一主面101a之第1樹脂層107,該第1樹脂層107係以構裝在配線基板101之一主面101a之半導體基板104之背面與連接端子106之前端面露出之方式在該一主面101a藉由填充環氧樹脂等之一般模具用之樹脂被覆半導體基板104及連接端子106之側面。本實施形態中,如圖1所示,第1樹脂層107係以半導體基板104之背面側之端部與連接端子106之前端部露出之方式被覆半導體基板104及連接端子106之側面之一部分而形成。亦即,第1樹脂層107係以半導體基板104之背面側之端部與連接端子106之前端部分別從第1樹脂層107之表面突出之方式形成。
又,第1樹脂層107表面之與半導體基板104側面接觸之部分,如圖1中之虛線圍繞之區域A所示,從半導體基板104側面之該半導體基板104之背面側之端緣朝向第1樹脂層107形成為圓角狀。又,半導體
基板104之從第1樹脂層107之表面突出部分之角部被去角(省略圖示)。
又,在從第1樹脂層107露出之半導體基板104之背面及連接端子106之前端面,藉由施加Ni/Au鍍敷形成有金屬膜109。又,本實施形態中,如圖1所示,在構裝於配線基板101之一主面101a之狀態之半導體基板104及連接端子106分別離一主面101a之高度形成為相同高度Ha(第1零件層102之厚度)。
第2零件層103具備設在該另一主面101b之第2樹脂層108,該第2樹脂層108係藉由在配線基板101之另一主面101b填充環氧樹脂等一般模具用之樹脂以被覆各晶片零件105。又,包含晶片電容器、晶片電感器、晶片電阻等之各晶片零件105係藉由使用焊料H之一般表面構裝技術構裝在配線基板101之另一主面101b。此外,本實施形態中,由於第2樹脂層108係被覆構裝在配線基板101之另一主面101b之各晶片零件105而設置,因此第2樹脂層108之厚度成為第2零件層103之厚度。
又,本實施形態中,如圖2所示,第2零件層103包含在構裝在配線基板101之另一主面101b之狀態下之離該另一主面101b之高度不同之複數個晶片零件105。此外,第1零件層102之厚度Ha係形成為較構裝在配線基板101之另一主面101b之各晶片零件105中之離該另一主面101b之高度最低之晶片零件105之高度Hb薄,藉此,第1零件層102之厚度形成為較第2零件層103之厚度薄。
又,本實施形態中,構裝在配線基板101之兩主面101a,101b之各零件中之構裝在配線基板101之一主面101a之半導體基板104之俯視下面積,與各晶片零件105之俯視下面積相較為最大。若以上述方式構成,
則設在配線基板101之一主面101a之第1零件層102形成為較設在另一主面101b之第2零件層103薄,但形成較薄之第1零件層102具備之半導體基板104之俯視下面積,與其他各晶片零件105之俯視下面積相較形成為最大,由於半導體基板104較樹脂硬,因此可抑制起因於各樹脂層107,108硬化時收縮使配線基板101彎曲所導致之模組100之彎曲。
又,此情形,使形成第1零件層102之第1樹脂層107之樹脂之線膨脹係數較形成第2零件層103之第2樹脂層108之樹脂之線膨脹係數大即可。若以上述方式構成,則第1零件層102具備之第1樹脂層107形成為較第2零件層103具備之第2樹脂層108薄,但第1樹脂層107由線膨脹係數較形成第2樹脂層108之樹脂大之樹脂形成,藉此,厚度較薄之第1樹脂層107硬化時之收縮力之大小與厚度較厚之第2樹脂層108硬化時之收縮力之大小之差變小,可取得將配線基板101從兩主面101a,101b側拉伸之力之平衡,因此可抑制分別形成各樹脂層107,108之樹脂收縮導致在模組100產生彎曲。
又,以連接端子106離配線基板101之一主面101a之高度較半導體基板104離一主面101a之高度高之方式形成連接端子106亦可。藉由以上述方式形成連接端子106,將模組100構裝於母基板2等時,半導體基板104不會成為妨礙,可提升模組100之構裝性。
又,以半導體基板104離配線基板101之一主面101a之高度較連接端子106離一主面101a之高度高之方式形成連接端子106亦可。此情形,模組100連接於母基板2時之半導體基板104之背面與母基板2之構裝面2a之距離變短,因此易於使從模組100產生之熱經由形成在母基
板2之面狀之接地電極(省略圖示)等散熱,可提升模組100之散熱特性。又,母基板2之構裝用電極2b與連接端子106藉由焊料H連接之情形,由於母基板2與連接端子106之距離較母基板2與半導體基板104之距離大,因此在母基板2與連接端子106之間可確保間隙,將母基板2與連接端子106加以接合之焊料H不會被擠壓,焊料H不易從接合部分露出,可防止因相鄰之連接端子106或構裝用電極2b彼此熔融之焊料H導致短路。
(模組之製造方法)
接著,說明模組100之製造方法之一例。
首先,如圖2(a)所示,準備配線基板101,該配線基板101,在其內部設置形成接地用之接地電極等之配線圖案,且透過通孔導體等電氣連接於此配線圖案之構裝用電極101c設在其兩主面101a,101b(配線基板準備步驟)。接著,如圖2(b)所示,半導體基板104及各晶片零件105與形成連接端子106之棒狀之金屬構件藉由焊料H表面構裝於設在配線基板101之兩主面101a,101b之各構裝用電極101c中之分別對應之構裝用電極101c(零件構裝步驟)。此外,半導體基板104係以面朝下覆晶構裝於配線基板101之一主面101a之構裝用電極101c,各晶片零件105係藉由周知之表面構裝技術構裝在配線基板101之另一主面101b。
接著,如圖2(c)所示,藉由在配線基板101之一主面101a填充樹脂形成被覆半導體基板104及連接端子106之第1樹脂層107,藉由在另一主面101b填充樹脂形成被覆各晶片零件105之第2樹脂層108(樹脂層形成步驟)。具體而言,各樹脂層107,108係藉由分配器填充樹脂而形成、或使用轉移成形技術或壓縮成形技術而形成、或配線基板101之兩主面101a,
101b藉由樹脂片包覆而形成。
如上述,藉由圖2(a)~圖2(c)所示之步驟(配線基板準備步驟~樹脂層形成步驟)準備模組坯體,該模組坯體,半導體基板104及各晶片零件105分別埋設於各樹脂層107,108,柱狀之連接端子106在豎設在配線基板101之一主面101a之狀態下配置於第1樹脂層107內(參照圖2(c))。
接著,如圖2(d)所示,以半導體基板104之背面側之端部與連接端子106之前端部從第1樹脂層107表面露出之方式,研磨或研削模組坯體之第1樹脂層107表面,藉此除去樹脂之一部分(除去步驟)。此外,藉由研磨除去第1樹脂層107之樹脂時,較佳為,藉由使用杯狀磨石之研磨、使用游離磨粒之拋光研磨、噴砂執行除去步驟。亦即,藉由調整游離磨粒之粒徑或材質等,能從第1零件層102將形成第1樹脂層107之樹脂較半導體基板104之背面及連接端子106之前端面優先地研磨並除去。是以,能以半導體基板104之背面側之端部與連接端子106之前端部露出之方式,將被覆半導體基板104及連接端子106分別之側面之一部分之第1樹脂層107容易地形成在配線基板101之一主面101a。
又,藉由除去步驟,半導體基板104之從第1樹脂層107表面突出之部分之角部被去角,且第1樹脂層107表面與半導體基板104側面接觸之部分,從半導體基板104側面之該半導體基板104之背面側之端緣朝向第1樹脂層107形成為圓角狀(參照圖1中之區域A)。再者,藉由研磨或研削半導體基板104之背面,在半導體基板104之背面形成凹凸。
然而,若半導體基板104之背面之表面粗度Ra之值過小,則不易在半導體基板104之背面藉由鍍敷處理等形成金屬膜109,若表面粗
度Ra之值過大,則有半導體基板104破損之虞,因此較佳為,以半導體基板104之背面之表面粗度Ra成為0.1μm~15μm之範圍之方式研磨或研削該背面。
又,本實施形態中,在除去步驟,以半導體基板104及連接端子106分別離配線基板101之一主面101a之高度相同之方式,與第1樹脂層107表面一起研磨或研削半導體基板104之背面側之端部及連接端子106之前端部。此外,本實施形態中,以離配線基板101之一主面101a之高度最高之半導體基板104及連接端子106之高度Ha較離配線基板101之另一主面101b之高度最低之晶片零件105之高度Hb低之方式,研磨或研削半導體基板104之背面側之端部及連接端子106之前端部。
接著,如圖2(e)所示,在從第1樹脂層107表面露出之半導體基板104之背面及連接端子106之前端面藉由鍍敷處理或網版印刷、蒸鍍等一般方法形成金屬膜109,藉此完成模組100(金屬膜形成步驟)。例如,藉由鍍敷處理形成金屬膜109之情形,首先,在半導體基板104之背面及連接端子106之前端面形成Ni層,在已形成之Ni層上形成Au層,藉此形成金屬膜109。
此外,半導體基板104之背面之金屬膜109不需形成在半導體基板104之背面整面,只要至少形成在其一部分即可。又,半導體基板104之背面之凹凸未必要形成,但若在半導體基板104之背面形成有凹凸,則在形成有凹凸之背面形成有金屬膜109時,在該金屬膜109亦形成凹凸,因此能使熱傳導率高之金屬膜109之表面積增大。
接著,以上述方式製造之模組100係配置成配線基板101之
一主面101a與母基板2之構裝面2a對向,形成在半導體基板104之背面及連接端子106之前端面之金屬膜109與形成在母基板2之構裝面2a之構裝用電極2b係藉由焊料H連接,藉此製造模組搭載裝置1。
此外,半導體基板104及連接端子106分別離配線基板101之一主面101a之高度未必要成為相同高度,以分別之高度不同之方式研磨或研削半導體基板104之背面側之端部及連接端子106之前端部亦可。此情形,例如,藉由調整研磨所使用之游離磨粒之粒徑或材質等,可調整半導體基板104及連接端子106離一主面101a之高度。
如上述,根據上述實施形態,藉由在配線基板101之兩主面101a,101b分別構裝半導體基板104及晶片零件105等之零件,提高零件構裝密度以謀求模組100之高功能化。另一方面,在配線基板101之一主面101a作為零件僅面朝下構裝半導體基板104而形成且設在該一主面101a之第1零件層102之厚度Ha形成為較在配線基板101之另一主面101b構裝複數個晶片零件105而形成且設在該另一主面101b之第2零件層103之厚度薄。
亦即,面朝下構裝在配線基板101之一主面101a之半導體基板104,在其表面側形成有既定電路,半導體基板104之背面側即使被研磨或研削,半導體基板104之電氣特性亦不會大幅變化,因此以形成在半導體基板104之背面側之電路不會受損之方式研磨或研削該半導體基板104之背面側,藉此能使半導體基板104變薄。因此,設在配線基板101之一主面101a之第1零件層102,作為零件僅面朝下構裝半導體基板104而形成,因此研磨或研削第1零件層102之半導體基板104之背面側使半導體基板
104變薄,藉此能將第1零件層102之厚度形成為較第2零件層103之厚度薄。
是以,儘管藉由在配線基板101之兩主面101a,101b分別構裝半導體基板104及晶片零件105等之零件以謀求模組100之高功能化,僅半導體基板104面朝下構裝在配線基板101之一主面101a而形成之第1零件層102之厚度Ha形成為較在配線基板101之另一主面101b構裝複數個晶片零件105而形成之第2零件層103之厚度薄,藉此提高零件構裝密度而謀求高功能化,且可提供高度變低之模組100。
又,第1零件層102之厚度Ha形成為較構裝在配線基板101之另一主面101b側之各晶片零件105中之離該另一主面101b之高度最低之晶片零件105之高度Hb薄,因此能更有效地使模組100高度變低。
又,第1零件層102具備豎設在配線基板101之一主面101a且電氣連接於構裝在該一主面101a之半導體基板104之外部連接用之複數個柱狀之連接端子106,但複數個連接端子106包含接地用之端子,第1零件層102形成為較第2零件層103薄,因此若與外部連接用之各連接端子106設在第2零件層103之情形相較,各連接端子106形成較短。
是以,藉由包含接地用之端子之外部連接用之複數個連接端子106形成較短降低各連接端子106之寄生電感,因此可強化模組100搭載於外部之母基板2等時之接地電極與半導體基板104之電氣連接。又,模組100搭載於外部之母基板2等之情形,形成較薄之第1零件層102所具備之半導體基板104與配置在母基板2與模組100之配線基板101之間且兩基板2,101具備之接地電極接近配置,因此來自半導體基板104之不需要輻射容
易被母基板2及配線基板101之接地電極吸收,可抑制來自構裝在模組100之半導體基板104之不需要輻射造成之影響。再者,上述實施形態中,半導體基板104背面之金屬膜109係藉由焊料H連接於母基板2之構裝用電極2b而連接於接地電極,因此能更有效地抑制來自半導體基板104之不需要輻射造成之影響。
又,配線基板101之另一主面101b側之各陶瓷積層晶片零件105,與半導體基板104不同,無法進行研磨或研削等而變薄,因此第2零件層103之厚度無法形成為較該晶片零件105之高度薄,但藉由將作為零件僅構裝半導體基板104而形成之第1零件層102之厚度形成為較第2零件層103之厚度薄,可提供高度低之實用模組100。
又,上述實施形態中,棒狀之金屬構件藉由焊料H構裝在配線基板101之一主面101a,藉此形成有外部連接用之連接端子106。因此,藉由調整位在一主面101a之構裝用電極101c之焊料H之量,以在連接端子106構裝在構裝用電極101c時熔融之焊料H濕潤連接端子106之側面之方式,如圖3所示,使被覆連接端子106之側面之焊料H從第1樹脂層107表面露出即可。如此,能使外部連接用之連接端子106之俯視下面積增加,可謀求使用焊料H之模組100與母基板2等之構裝強度之提升。
又,在模組100之配線基板101之一主面101a側,以半導體基板104之背面側之端部與連接端子106之前端部從第1樹脂層107表面突出而露出之方式,形成有被覆半導體基板104及連接端子106分別之側面之一部分之第1樹脂層107,因此熱傳導率較形成第1樹脂層107之樹脂高之半導體基板104之背面側之端部及熱傳導率較樹脂高之金屬所形成之連
接端子106之前端部從第1樹脂層107表面露出之部分之表面積增加,因此可謀求模組100之散熱特性之提升。
又,半導體基板104之背面側之端部從第1樹脂層107表面突出而露出,因此若與半導體基板104被樹脂被覆之模組相較,在模組100構裝在母基板2時,由於半導體基板104之背面與設在母基板2之接地電極之距離變近,因此模組100產生之熱易於透過接地電極散熱,因此模組100之散熱特性提升。再者,上述實施形態中,半導體基板104背面之金屬膜109係藉由焊料H連接於母基板2之構裝用電極2b而連接於接地電極,因此能使模組100產生之熱更有效地透過接地電極散熱。
又,連接端子106之前端部從第1樹脂層107表面突出而形成模組100,因此連接端子106與母基板2之構裝用電極2b容易接觸,因此可謀求連接端子106與母基板2之連接性之提升。再者,母基板2之構裝面2a之構裝用電極2b與連接端子106藉由焊料H連接時,如圖1所示,在熔融之焊料H濕潤連接端子106之前端部之側面之狀態下硬化成圓角狀,因此可謀求藉由焊料H連接之模組100及母基板2間之連接強度之提升。
又,半導體基板104背面側之端部及連接端子106之前端部從第1樹脂層107表面突出而形成模組100,因此在模組100構裝在母基板2時,在半導體基板104及連接端子106之周邊形成夾在第1樹脂層107表面與母基板2之構裝面2a之間之空間。是以,模組100構裝在母基板2時熔融之焊料H留在形成在連接端子106及半導體基板104周邊之空間,因此,可防止以往般熔融之焊料H流動至密合之第1樹脂層107及構裝面2a之界面導致相鄰之連接端子106及構裝用電極2b彼此短路。
又,在模組100構裝在母基板2時,在夾在第1樹脂層107表面與母基板2之構裝面2a之間而形成之空間,可填充形成底填樹脂層3之樹脂,能使底填樹脂層3與模組100及母基板2之接觸面積變大,因此能提升模組100對母基板2之構裝強度。
又,第1樹脂層107表面之與半導體基板104側面接觸之部分,從半導體基板104側面之該半導體基板104之背面側之端緣朝向第1樹脂層107形成為圓角狀,因此對第1樹脂層107表面與半導體基板104接觸之部分施加之應力被形成為圓角狀之樹脂分散,因此可防止第1樹脂層107從半導體基板104剝離。
又,半導體基板104之從第1樹脂層107表面突出之部分之角部係藉由研磨或研削去角,因此可防止半導體基板104裂開或破裂。
又,由於在半導體基板104之背面形成有凹凸,因此熱傳導率高之半導體基板104從第1樹脂層107露出之部分之表面積變大,能使模組100之散熱特性提升。又,在從第1樹脂層107露出之半導體基板104之背面之至少一部分形成有金屬膜109,因此熱傳導率較半導體基板104高之金屬膜109作為散熱片而作用,藉此進一步提升模組100之散熱特性。又,藉由將形成在半導體基板104之背面之金屬膜109利用為與母基板2之接地電極連接用之電極,能使用連接端子106及金屬膜109藉由焊料H連接母基板2與模組100,因此可謀求母基板2與模組100之連接強度之提升。
又,在形成在半導體基板104之背面之金屬膜109之表面形成有凹凸,因此金屬膜109之表面積增加,可進一步提升模組2之散熱特性。又,將金屬膜109利用為與母基板2之連接用電極之情形,由於與母基板2
之連接面積增加,因此可謀求模組100與母基板2之連接強度之提升。
又,藉由在半導體基板104之背面形成金屬膜109,半導體基板104之背面受到保護,因此可防止半導體基板104因外力等而破損。
此外,本發明並不限於上述各實施形態,只要不脫離其趣旨,可進行上述以外之各種變更,例如,上述實施形態中,將棒狀之金屬構件藉由焊料H構裝在配線基板101而形成連接端子106,但如圖4所示之連接端子之另一例,在將半導體基板104構裝在配線基板101之一主面101a前,藉由使用光微影之鍍敷處理形成連接端子106a亦可。若以上述方式構成,則不會如圖3所示之連接端子106般焊料H濕潤連接端子106,可高精度地形成細微徑之連接端子106a,因此能使連接端子106a之配置間隔變窄。又,在埋設有半導體基板104之狀態之第1樹脂層107藉由雷射加工等形成通孔,在已形成之通孔填充Ag或Cu等之導電糊、或施加通孔填鍍以形成連接端子亦可。
又,如圖5所示之模組之變形例,以僅設在模組100a之配線基板101之一主面101a之半導體基板104之背面及連接端子106之前端面露出之方式形成第1樹脂層107,藉此形成為第1樹脂層107表面、半導體基板104背面、連接端子106之前端面構成同一面之所謂面高相同狀態亦可。
又,在配線基板101之一主面101a構裝有複數個半導體基板104亦可,在配線基板101之另一主面101b除了晶片零件105外構裝有其他電子零件或半導體基板作為零件亦可。亦即,只要為在配線基板101之一主面101a作為零件僅構裝背面可研磨或研削之半導體基板104之構成即可,適當地將任何零件構裝在配線基板101以提高模組100之構裝密度而
具備對應使用目的之功能亦可。
又,形成在配線基板101之一主面101a之連接端子106之數並不限於上述例,在配線基板101之另一主面101b亦形成連接端子106亦可。又,連接端子106未必要配置在配線基板101之一主面101a。亦即,連接端子106與半導體基板104分別配置在配線基板101之不同主面亦可。又,第1零件層102之厚度形成為較第2零件層103(第2樹脂層108)之厚度薄即可,各樹脂層107,108未必要設在配線基板101之兩主面101a,101b。
又,在半導體基板104之背面及連接端子106之前端面未必要形成有金屬膜109,依據模組100之使用目的形成有金屬膜109即可。又,半導體基板104與連接端子106分別配置在配線基板101之不同主面之情形,金屬膜109不僅形成在半導體基板104之背面,亦形成在第1樹脂層107之周圍,藉此能使金屬膜109作為模組100之屏蔽層而作用。又,母基板2與模組100之連接並不限於焊料H,例如,使用導電性接著材將母基板2與模組100電氣連接亦可。又,未必要如上述實施形態般將半導體基板104之背面與母基板2之構裝面2a焊料連接,半導體基板104之背面與母基板2之構裝面2a僅接觸配置亦可。又,半導體基板104之背面與母基板2之構裝面2a分離配置亦可。
又,對模組100之配線基板101之兩主面101a,101b之各零件之構裝方法並不限於利用焊料之方法,藉由利用超音波振動技術或電漿等之表面活性化技術之構裝方法將各零件構裝在配線基板101亦可。
此外,可將本發明廣泛地適用於在配線基板之兩主面分別構裝零件而成之模組。
H‧‧‧焊料
1‧‧‧模組搭載裝置
2‧‧‧母基板
2a‧‧‧構裝面
2b‧‧‧構裝用電極
3‧‧‧底填樹脂層
100‧‧‧模組
101‧‧‧配線基板
101a‧‧‧一主面
101b‧‧‧另一主面
101c‧‧‧構裝用電極
102‧‧‧第1零件層
103‧‧‧第2零件層
104‧‧‧半導體基板(零件)
105‧‧‧陶瓷積層晶片零件(零件)
106‧‧‧連接端子
107‧‧‧第1樹脂層
108‧‧‧第2樹脂層
109‧‧‧金屬膜
Claims (5)
- 一種高頻模組,係在配線基板之兩主面分別構裝零件而成,其特徵在於,具備:第1零件層,係設在該配線基板之一主面,在該一主面作為該零件僅面朝下構裝半導體基板而形成;以及第2零件層,係設在該配線基板之另一主面,在該另一主面構裝複數個該零件而形成;該第1零件層之厚度形成為較該第2零件層之厚度薄;該第1零件層具備設在該一主面之第1樹脂層,該第1樹脂層以該配線基板之一主面側之該半導體基板之背面露出之方式被覆該半導體基板之側面;該第2零件層具備設在該另一主面之第2樹脂層,該第2樹脂層被覆該配線基板之另一主面側之該各零件;形成該第1樹脂層之樹脂之線膨脹係數較形成該第2樹脂層之樹脂之線膨脹係數大。
- 如申請專利範圍第1項之高頻模組,其中,該第1零件層之厚度較構裝在該配線基板之另一主面側之各該零件中之離該另一主面之高度最低之該零件之高度薄。
- 如申請專利範圍第1或2項之高頻模組,其中,該第1零件層具備外部連接用之複數個柱狀之連接端子,該複數個連接端子豎設在該配線基板之一主面且電氣連接於構裝在該一主面之該半導體基板;該複數個連接端子包含接地用之端子。
- 如申請專利範圍第1或2項之高頻模組,其中,構裝在該兩主面之各該零件中之構裝在該配線基板之一主面之該半導體基板在俯視下之面積,與其他各該零件在俯視下之面積相較為最大。
- 如申請專利範圍第1或2項之高頻模組,其中,在與該配線基板之一主面對向之該半導體基板之表面形成有既定電路;在該配線基板之另一主面側之該各零件包含陶瓷積層晶片零件。
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Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6129177B2 (ja) * | 2012-08-03 | 2017-05-17 | パナソニック株式会社 | 電子部品モジュールとその実装体 |
WO2016067908A1 (ja) * | 2014-10-29 | 2016-05-06 | 株式会社村田製作所 | 無線通信モジュール |
EP3318113A1 (en) * | 2015-06-30 | 2018-05-09 | 3M Innovative Properties Company | Electronic devices comprising a via and methods of forming such electronic devices |
JP2017045954A (ja) * | 2015-08-28 | 2017-03-02 | ミツミ電機株式会社 | モジュール及びその製造方法 |
WO2018043162A1 (ja) * | 2016-08-31 | 2018-03-08 | 株式会社村田製作所 | 回路モジュールおよび電子機器 |
WO2018043388A1 (ja) * | 2016-08-31 | 2018-03-08 | 株式会社村田製作所 | 回路モジュールおよび電子機器 |
CN110392926B (zh) * | 2017-03-14 | 2022-12-06 | 株式会社村田制作所 | 高频模块 |
JP6725059B2 (ja) | 2017-03-15 | 2020-07-15 | 株式会社村田製作所 | 高周波モジュール及び通信装置 |
CN211858622U (zh) * | 2017-06-16 | 2020-11-03 | 株式会社村田制作所 | 电路基板及电路模块 |
JP6891849B2 (ja) * | 2017-07-19 | 2021-06-18 | 株式会社村田製作所 | 電子モジュールおよび電子モジュールの製造方法 |
US10453802B2 (en) * | 2017-08-30 | 2019-10-22 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure, semiconductor device and method for manufacturing the same |
WO2019065569A1 (ja) | 2017-09-29 | 2019-04-04 | 株式会社村田製作所 | 高周波回路および通信装置 |
TWI736736B (zh) * | 2018-01-22 | 2021-08-21 | 矽品精密工業股份有限公司 | 電子封裝件及其製法 |
WO2019146284A1 (ja) | 2018-01-25 | 2019-08-01 | 株式会社村田製作所 | 高周波モジュールおよび通信装置 |
WO2019216300A1 (ja) * | 2018-05-08 | 2019-11-14 | 株式会社村田製作所 | 高周波モジュール |
US11462455B2 (en) | 2018-06-22 | 2022-10-04 | Advanced Semiconductor Engineering, Inc. | Semiconductor package device and method of manufacturing the same |
JPWO2020017582A1 (ja) * | 2018-07-20 | 2021-06-24 | 株式会社村田製作所 | モジュール |
US20200075547A1 (en) * | 2018-08-31 | 2020-03-05 | Qorvo Us, Inc. | Double-sided integrated circuit module having an exposed semiconductor die |
KR102455842B1 (ko) | 2018-09-28 | 2022-10-19 | 가부시키가이샤 무라타 세이사쿠쇼 | 회로 모듈 및 통신 장치 |
US10834818B2 (en) * | 2018-11-05 | 2020-11-10 | Ngk Spark Plug Co., Ltd. | Wiring board |
WO2020218289A1 (ja) | 2019-04-26 | 2020-10-29 | 株式会社村田製作所 | モジュール部品、アンテナモジュール及び通信装置 |
JP2021100213A (ja) * | 2019-12-23 | 2021-07-01 | 株式会社村田製作所 | 高周波モジュール及び通信装置 |
JP2022140870A (ja) * | 2021-03-15 | 2022-09-29 | 株式会社村田製作所 | 回路モジュール |
US11862688B2 (en) * | 2021-07-28 | 2024-01-02 | Apple Inc. | Integrated GaN power module |
CN113840449A (zh) * | 2021-09-06 | 2021-12-24 | 华为技术有限公司 | 一种基板和电子设备 |
US20230091182A1 (en) * | 2021-09-22 | 2023-03-23 | Qualcomm Incorporated | Package comprising an integrated device with a back side metal layer |
CN114496988A (zh) * | 2022-04-19 | 2022-05-13 | 宁波德葳智能科技有限公司 | 脑电波处理系统的再布线封装结构及其制作方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1189282A1 (en) * | 2000-03-21 | 2002-03-20 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device, method of manufacturing electronic device, electronic device, and portable information terminal |
US20110182039A1 (en) * | 2008-10-08 | 2011-07-28 | Murata Manufacturing Co., Ltd. | Composite module |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1050926A (ja) | 1996-07-31 | 1998-02-20 | Taiyo Yuden Co Ltd | ハイブリッドモジュール |
KR100563122B1 (ko) * | 1998-01-30 | 2006-03-21 | 다이요 유덴 가부시키가이샤 | 하이브리드 모듈 및 그 제조방법 및 그 설치방법 |
JP2001007256A (ja) | 1999-06-22 | 2001-01-12 | Mitsubishi Electric Corp | 半導体集積回路装置および半導体集積回路装置の製造方法 |
JP2002216473A (ja) | 2001-01-16 | 2002-08-02 | Matsushita Electric Ind Co Ltd | 半導体メモリ装置 |
JP2002343904A (ja) | 2001-05-21 | 2002-11-29 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP3859225B2 (ja) * | 2001-11-30 | 2006-12-20 | 日本特殊陶業株式会社 | 配線基板 |
JP2004193404A (ja) * | 2002-12-12 | 2004-07-08 | Alps Electric Co Ltd | 回路モジュール、及びその製造方法 |
JP2005203633A (ja) * | 2004-01-16 | 2005-07-28 | Matsushita Electric Ind Co Ltd | 半導体装置、半導体装置実装体、および半導体装置の製造方法 |
CN100472780C (zh) * | 2004-02-13 | 2009-03-25 | 株式会社村田制作所 | 电子零部件及其制造方法 |
DE112006002635B4 (de) * | 2005-10-20 | 2012-11-15 | Murata Manufacturing Co., Ltd. | Schaltungsmodul und Schaltungsvorrichtung, die ein Schaltungsmodul umfasst |
WO2007049458A1 (ja) * | 2005-10-26 | 2007-05-03 | Murata Manufacturing Co., Ltd. | 積層型電子部品、電子装置および積層型電子部品の製造方法 |
CN101346310B (zh) * | 2005-12-27 | 2012-01-25 | 株式会社村田制作所 | 镁橄榄石粉末的制造方法、镁橄榄石粉末、镁橄榄石烧结体、绝缘体陶瓷组合物以及层叠陶瓷电子器件 |
JP2007281160A (ja) | 2006-04-06 | 2007-10-25 | Matsushita Electric Ind Co Ltd | 回路部品内蔵モジュールおよび該回路部品内蔵モジュールの製造方法 |
WO2007132612A1 (ja) * | 2006-05-17 | 2007-11-22 | Murata Manufacturing Co., Ltd. | 複合基板及びその製造方法 |
JP2008205071A (ja) | 2007-02-19 | 2008-09-04 | Matsushita Electric Ind Co Ltd | 電子部品内蔵基板とこれを用いた電子機器、およびその製造方法 |
US8415789B2 (en) * | 2008-05-09 | 2013-04-09 | Kyushu Institute Of Technology | Three-dimensionally integrated semicondutor device and method for manufacturing the same |
JP5093353B2 (ja) * | 2008-08-12 | 2012-12-12 | 株式会社村田製作所 | 部品内蔵モジュールの製造方法及び部品内蔵モジュール |
JP5261255B2 (ja) * | 2009-03-27 | 2013-08-14 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
WO2011030542A2 (ja) * | 2009-09-11 | 2011-03-17 | 株式会社村田製作所 | 電子部品モジュールおよびその製造方法 |
-
2013
- 2013-06-19 WO PCT/JP2013/066790 patent/WO2014017228A1/ja active Application Filing
- 2013-06-19 CN CN201380038081.8A patent/CN104471707B/zh active Active
- 2013-06-19 JP JP2014526821A patent/JP5773082B2/ja active Active
- 2013-06-24 TW TW102122300A patent/TWI569401B/zh active
-
2015
- 2015-01-23 US US14/603,433 patent/US9293446B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1189282A1 (en) * | 2000-03-21 | 2002-03-20 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device, method of manufacturing electronic device, electronic device, and portable information terminal |
US20110182039A1 (en) * | 2008-10-08 | 2011-07-28 | Murata Manufacturing Co., Ltd. | Composite module |
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