TWI550789B - 可堆疊微電子封裝結構 - Google Patents

可堆疊微電子封裝結構 Download PDF

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Publication number
TWI550789B
TWI550789B TW102100751A TW102100751A TWI550789B TW I550789 B TWI550789 B TW I550789B TW 102100751 A TW102100751 A TW 102100751A TW 102100751 A TW102100751 A TW 102100751A TW I550789 B TWI550789 B TW I550789B
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Taiwan
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microelectronic
package
terminals
component
substrate
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TW102100751A
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English (en)
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TW201342546A (zh
Inventor
畢哥辛 哈芭
房炅模
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英帆薩斯公司
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    • H—ELECTRICITY
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
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Description

可堆疊微電子封裝結構 相關申請案交互參考
本申請案係2012年1月9日申請之美國專利申請案第13/346,167號之接續案，其揭示內容以引用的方式併入本文中。
本發明係關於經改良之微電子封裝及製作此等封裝之方法。
微電子元件通常包括半導體材料(諸如矽或砷化鎵)之薄板，通常稱作晶粒或半導體晶片。半導體晶片通常具體體現大量主動或被動裝置，其等可在內部電連接在一起以執行電路功能，例如，作為積體電路。半導體晶片通常提供為個別、預封裝單元。在一些單元設計中，半導體晶片安裝至基板或晶片載體。
儘管半導體封裝已得到提升，但是仍需要可幫助減小封裝之總體大小同時提高電互連可靠性之改良。本發明之此等屬性藉由如下文所述之微電子封裝之構建及製作微電子封裝之方法而實現。
本揭示內容之一態樣係關於微電子總成，其包含第一微電子封裝，該第一微電子封裝具有基板，該基板具有第一及第二相對表面及其上之基板接觸件。第一封裝進一步包含第一微電子元件及第二微電子元件，各具有與基板接觸件電連接之元件接觸件，第一微電子元件及第二微電子元件在第一表面上彼此間隔開以在第一微電子元件與第二微電子元件之間提供第一表面之互連區域。第二表面上之複數個封裝端子與基板接觸件電互連以連接封裝與封裝外之組件。複數個堆疊 端子暴露在互連區域中之第一表面上以連接封裝與覆蓋基板之第一表面之組.件。總成進一步包含覆蓋第一微電子封裝且具有接合至第一微電子封裝之堆疊端子之端子之第二微電子封裝。
封裝端子及堆疊端子可覆蓋彼此成各自電連接對。在一實例中，封裝端子及堆疊端子可為穿過基板之導電通孔之相對末端。
堆疊端子之額外者可在基板在其位於互連區域外之部分中之第一表面上。在一實施例中，第一微電子封裝可進一步包含間隔在第一微電子元件與第二微電子元件之間之互連區域之相對側上之第三微電子元件及第四微電子元件。在此一實施例中，堆疊端子之額外者可在由微電子元件之相鄰者限定之基板之角隅區域中。此外或或者，堆疊端子之至少一些可與第一微電子元件及第二微電子元件兩者連接。在此一實例中，與第一微電子元件及第二微電子元件兩者連接之堆疊端子之至少一些可經組態以攜載命令、位址及定時信號之至少一者。
第一微電子封裝可進一步包含覆蓋基板之第一表面之至少一部分之成形囊封層且第一導電互連件之至少部分可包括延伸穿過成形囊封層至暴露末端之第一導電通孔。在一實施例中，第一微電子元件及第二微電子元件之接觸件支承面可面向基板，且基板接觸件包含暴露在第二表面上之基板接觸件且元件接觸件可藉由導線接合與基板接觸件連接。
微電子總成可包含暴露在第一表面上之基板接觸件。在此一實施例中，第一微電子元件及第二微電子元件之元件接觸件可面向暴露在第一表面上之基板接觸件並可結合至其。
第二微電子封裝可包含安裝在第二基板上之第三微電子元件。在此一實施例中，第二封裝之端子可在第二基板上且與第三微電子元件電連接。在一實例中，第二微電子封裝可包含具有第一及第二間隔開表面及安裝在其第二表面上之第三微電子元件及第四微電子元件之 基板。第三微電子元件及第四微電子元件可在第二封裝之基板上間隔開以在其中界定互連區域，且端子可在互連區域內暴露在第二封裝之基板之第二表面上。第二封裝之基板可進一步包含在其第一表面與第二表面之間延伸穿過其之窗且第二封裝之端子可藉由延伸穿過窗之導線接合而結合至第一封裝之堆疊端子。在又一實施例中，第一封裝之基板可界定圍繞第一微電子元件及第二微電子元件之至少一者之周邊區域，額外堆疊端子位於該周邊區域中。周邊區域可圍繞第三微電子元件及第四微電子元件之至少一者且周緣可限定周邊區域。額外端子可位於其周邊區域中且第一封裝之額外堆疊端子之至少一些可藉由延伸經過第二封裝之基板之周緣之導線接合而與第二封裝之額外端子之至少一些結合。
第三微電子封裝可覆蓋第一微電子封裝並可具有結合至第一微電子封裝之堆疊端子之端子。此外，微電子總成可包含具有暴露在其一表面上之電路接觸件之電路板。第一微電子封裝之封裝端子可與電路接觸件電連接。第二微電子封裝端子可為封裝端子或堆疊端子之至少一者。第一封裝之堆疊端子可與第二封裝之封裝端子電連接。此外，第一封裝及第二封裝之堆疊端子可電連接。
微電子總成可進一步包含在第一微電子封裝與第二微電子封裝之間之熱散佈器。熱散佈器可具有形成穿過其、覆蓋互連區域之至少一部分之孔隙。第二微電子封裝之堆疊端子可透過孔隙與第一微電子封裝之堆疊端子連接。在進一步包含第二熱散佈器之總成之一實施例中，該熱散佈器可為第一熱散佈器，第一熱散佈器安置在互連區域之第一側上且第二熱散佈器安置在互連區域之第二側上。間隙可界定在第一熱散佈器與第二熱散佈器之間，且第二微電子封裝之堆疊端子可透過間隙與第一微電子封裝之堆疊端子連接。
本揭示內容之另一態樣係關於包含具有第一微電子元件及第二 微電子元件之第一微電子封裝之微電子總成。各微電子元件具有其正面及背面以及暴露在各自正面上之元件接觸件。第一微電子元件及第二微電子元件側向彼此間隔開以在其間提供互連區域。第一封裝進一步具有介電層，該介電層具有覆蓋第一微電子元件及第二微電子元件之正面及背向微電子元件之正面之表面。介電層進一步具有與第一表面相對之第二表面。複數個封裝端子暴露在介電層之第一表面上且透過沿著介電層延伸之跡線及從跡線延伸且接觸元件接觸件之第一金屬化通孔與元件接觸件電連接。複數個堆疊端子暴露在介電層之第二表面上且與封裝端子電連接以連接封裝與覆蓋介電層之第二表面之組件。總成進一步包含覆蓋第一微電子封裝且具有結合至第一微電子封裝之堆疊端子之端子之第二微電子封裝。
在一實例中，第一封裝可進一步包含在互連區域內至少部分圍繞第一微電子元件及第二微電子元件且界定其覆蓋介電層之第二表面之表面之成形囊封層。導電互連件可與堆疊端子電連接且具有暴露在成形囊封層之表面上之端面。
本揭示內容之又一態樣係關於微電子總成，其包含第一封裝，該第一封裝具有基板，該基板上具有第一及第二相對表面。第一封裝進一步包含各具有與第一表面上之相應基板接觸件電連接之元件接觸件之第一微電子元件及第二微電子元件。第一微電子元件及第二微電子元件在第一表面上彼此間隔開以提供第一微電子元件與第二微電子元件之間之第一表面之互連區域。第二表面上之複數個封裝端子與基板接觸件電互連以連接封裝與封裝外之組件。在互連區域中暴露在基板之第一表面上之複數個堆疊端子與封裝端子之至少一些電連接。總成進一步包含覆蓋第一微電子封裝且具有端子之第二微電子封裝。複數個導電互連件結合在第一微電子封裝之堆疊端子與第二微電子封裝之端子之間。
第二微電子封裝可進一步具有：第二介電層，其具有第一及第二相對表面；及至少一微電子元件，其安裝在介電層之第一表面上。
根據本發明之另一實施例之微電子總成包含：第一封裝，其具有基板，該基板具有第一及第二相對表面；及各具有與第一表面上之相應基板接觸件電連接之元件接觸件之四個微電子元件。微電子元件配置在第一表面上以界定被微電子元件圍繞之第一表面之互連區域。第二表面上之複數個封裝端子與基板接觸件電互連以連接封裝與封裝外之組件。互連區域中之第一表面上之複數個堆疊端子與封裝端子電連接。總成進一步包含覆蓋第一微電子封裝且具有端子之第二微電子封裝。導電互連件結合在第一微電子封裝之堆疊端子與第二微電子封裝之端子之間。微電子元件之各者可包含鄰近互連區域之周緣使得內部互連區域被界定為矩形區域。第一導電元件之至少一些可與第一微電子元件之至少兩者電連接。
本揭示內容之另一態樣係關於微電子總成，其包含第一封裝，該第一封裝具有基板，該基板具有第一及第二相對表面。第一封裝亦包含各具有與第一表面上之相應基板接觸件電連接之元件接觸件之第一微電子元件及第二微電子元件，第一微電子元件及第二微電子元件在第一表面上彼此間隔開以提供第一微電子元件與第二微電子元件之間之第一表面之互連區域。複數個接觸墊具有暴露在基板之第二表面上之表面，接觸墊之表面界定與基板接觸件電互連以連接封裝與封裝外之組件之封裝端子。成形囊封層覆蓋基板之第一表面之至少一部分並界定囊封表面。總成進一步包含接合至囊封表面且具有面向囊封表面之端子之第二微電子封裝。複數個導電通孔至少延伸穿過成形囊封層且連接第一微電子封裝之接觸墊與第二微電子封裝之端子。
導電通孔可進一步延伸穿過與其電接觸之第一封裝之接觸墊。第二微電子封裝可進一步包含具有第一及第二間隔開表面之基板。第 二表面可接合至囊封表面，且第二封裝之端子可為暴露在基板之第二表面上之導電墊之表面。導電通孔可進一步延伸穿過與其電接觸之第二封裝之導電墊。
根據本揭示內容之另一態樣之系統可包含根據上述實施例之任意者之微電子總成及電連接至微電子總成之一或多個其他電子組件。
本揭示內容之又一態樣係關於用於製作微電子總成之方法。方法包含組裝第一微電子封裝與第二微電子封裝，第二微電子封裝覆蓋第一微電子封裝且在其上具有端子。第一微電子封裝包含具有第一及第二相對表面之基板及其上之基板接觸件。第一封裝進一步包含各具有與基板接觸件電連接之元件接觸件之第一微電子元件及第二微電子元件。第一微電子元件及第二微電子元件在第一表面上彼此間隔開以提供第一微電子元件與第二微電子元件之間之第一表面之互連區域。第二表面上之複數個封裝端子與基板接觸件電互連以連接封裝與封裝外之組件。複數個堆疊端子暴露在互連區域中之第一表面上以連接封裝與覆蓋基板之第一表面之組件。方法進一步包含連接第二微電子封裝之端子與第一微電子封裝之堆疊端子以在其間形成電連接。
在一實施例中，連接第二微電子封裝之端子與第一微電子封裝之堆疊端子之步驟包含至少在其互連區域中將封裝端子結合至覆蓋基板之第一表面之第一微電子封裝之囊封層上之互連件之暴露末端。在此一實例中，互連件可結合至與其暴露末端相對之堆疊端子。在另一實施例中，連接第二微電子封裝之端子與第一微電子封裝之堆疊端子之步驟可包含至少在互連區域中將導電接合材料塊體沈積在覆蓋基板之第一表面之第一微電子封裝之囊封層內之孔中。在此一實施例中，堆疊端子可暴露在孔內之囊封層之表面上且導電接合材料塊體可結合至第二封裝之端子及第一封裝之堆疊端子。
在又一實施例中，連接第二微電子封裝之端子與第一微電子封 裝之堆疊端子之步驟可包含至少在其互連區域中形成複數個孔為至少穿過覆蓋基板之第一表面之第一微電子封裝之囊封劑。複數個孔可與其第一末端上之堆疊端子之各自者及其第二末端上之第二封裝之端子之相應者對準。此一方法可進一步包含用與第一微電子封裝之堆疊端子及第二封裝之封裝端子接觸之導電材料填充孔。孔可進一步形成為穿過第一封裝之基板及穿過其各自堆疊端子。或者，孔可進一步形成為穿過第二封裝之基板及穿過其相應端子。
1‧‧‧系統
3‧‧‧電子組件
4‧‧‧共同外殼
5‧‧‧透鏡
6‧‧‧電子組件
8‧‧‧微電子總成
10A‧‧‧微電子封裝
10B‧‧‧微電子封裝
10C‧‧‧微電子封裝
10D‧‧‧微電子封裝
12‧‧‧基板
14‧‧‧第一表面/正面
16‧‧‧第二表面/背面
22‧‧‧基板佈線
24‧‧‧基板接觸件
26‧‧‧封裝端子
28‧‧‧堆疊端子
32‧‧‧窗
40‧‧‧微電子元件
42‧‧‧正面
44‧‧‧背面
45‧‧‧邊緣
48‧‧‧導線接合件
50‧‧‧囊封劑
52‧‧‧成形介電層
54‧‧‧表面
56‧‧‧互連件
58‧‧‧端面
60‧‧‧黏著層
62‧‧‧接合金屬塊體
70‧‧‧電路板
72‧‧‧導體
74‧‧‧焊球
108‧‧‧微電子封裝
110A‧‧‧微電子封裝
110B‧‧‧微電子封裝
112‧‧‧基板/接觸件
114‧‧‧第一表面
116‧‧‧第二表面
124‧‧‧表面
126‧‧‧封裝端子/孔隙
128‧‧‧堆疊端子
136‧‧‧開口
152‧‧‧成形介電層
156‧‧‧接合金屬互連件
160‧‧‧黏著層
174‧‧‧焊球
210A‧‧‧封裝
210B‧‧‧封裝
212‧‧‧基板
214‧‧‧第一表面
216‧‧‧堆疊端子228之相對面
226‧‧‧堆疊端子
228‧‧‧堆疊端子
240‧‧‧微電子元件
256‧‧‧導線接合互連件
310A‧‧‧封裝
310B‧‧‧封裝
312‧‧‧基板
314‧‧‧第一表面
326‧‧‧封裝端子
328‧‧‧堆疊端子
330‧‧‧通孔
340‧‧‧微電子元件
342‧‧‧正面
346‧‧‧元件接觸件
348‧‧‧焊球
356‧‧‧互連件
360‧‧‧黏著層
410A‧‧‧封裝
410B‧‧‧封裝
456‧‧‧互連件
460‧‧‧黏著層
462‧‧‧焊球
464‧‧‧熱散佈器
466‧‧‧窗
510A‧‧‧微電子封裝
510B‧‧‧微電子封裝
510C‧‧‧微電子封裝
510D‧‧‧微電子封裝
526‧‧‧封裝端子
536‧‧‧金屬化通孔
540‧‧‧微電子元件
542‧‧‧正面
546‧‧‧接觸件
552‧‧‧成形介電質
554‧‧‧表面
556‧‧‧互連件
558‧‧‧端面
560‧‧‧黏著層
562‧‧‧焊球
564‧‧‧熱散佈器
572‧‧‧電路接觸件
574‧‧‧焊球
576‧‧‧封裝基板/封裝接觸件
578‧‧‧封裝接觸件
610‧‧‧封裝
612‧‧‧基板
614‧‧‧表面
618‧‧‧互連區域
620‧‧‧外互連區域
628‧‧‧堆疊端子
628A‧‧‧堆疊端子
640‧‧‧微電子元件
640A‧‧‧微電子元件
640B‧‧‧微電子元件
640C‧‧‧微電子元件
645A‧‧‧內邊緣表面
現將參考附圖描述本發明之不同實施例。應瞭解此等圖僅描繪本發明之一些實施例且因此不得視作限制其範疇。
圖1係根據本揭示內容之實施例之包含微電子封裝之總成之截面圖；圖1A係替代總成之一部分之細節圖；圖2係包含如圖1所示之額外微電子封裝之其他總成之截面圖；圖3A至圖3C係併入替代微電子封裝之替代總成之截面圖；圖4係替代微電子封裝之替代總成之截面圖；圖5A及圖5B係替代微電子封裝之其他替代總成之截面圖；圖6係包含圖1所示之類型之微電子封裝之替代總成；圖7係包含圖1所示之類型之微電子封裝之又一替代總成；圖8至圖10係根據本揭示內容之其他實施例之其他替代微電子封裝之各種總成之截面圖；圖11係併入圖8所示之微電子封裝之圖6所示之類型之總成；圖12係併入圖8所示之微電子封裝之圖7所示之類型之總成；圖13係包含圖8所示之類型之額外微電子元件之總成之截面圖；圖14係其他替代微電子封裝之總成之截面圖；圖15係如圖14所示之總成中所使用之微電子封裝之俯視平面 圖；圖16及圖17係可用於圖14所示之總成中之替代微電子封裝之俯視平面圖；及圖18展示包含根據本揭示內容之實施例之微電子總成之系統。
現參考其中相同參考數字用於指示類似特徵之圖式，圖1展示電路板70上之微電子封裝10A及10B之微電子總成8。在所展示之實施例中，封裝10A及10B實質相同且各包含安裝在基板12之正面14上之複數個微電子元件40。在一實例中，各微電子元件可為或包含具體體現可電組態為舉例而言積體電路之複數個主動電路元件(例如半導體裝置)之半導體晶片。在另一實例中，各微電子元件可包含複數個被動電路元件，諸如電容器、電感器或電阻器，其等在一些情況中可具體體現在半導體晶片中僅作為被動裝置或與主動電路元件即主動裝置一起。在所展示之實施例中，各封裝10A及10B包含兩個微電子元件40，但在其他實施例中，封裝(諸如下文所述之封裝)可包含多於兩個微電子元件，諸如三個、四個或更多個。
在圖1之例示性實施例中，微電子元件40在各自基板上安裝為倒裝導線接合組態。在本組態中，微電子元件40安裝為其等正面42面向基板12之正面14。元件接觸件46暴露在微電子元件40之正面42上，且與可包含形成在基板12上或至少部分嵌入基板12中的跡線或接觸墊的基板佈線22電連接。在所展示之實施例中，元件接觸件46藉由穿過基板12中之窗32的導線接合件48與基板佈線22連接。雖然圖1中僅展示一對導線接合件48，但是複數對導線接合件可沿著一列延伸(見圖15)且可穿過呈長形以接受多個導線接合件對之窗。囊封劑50可在窗32的區域中及沿著其在基板12外延伸超出其背面16的部分，圍繞及保護導線接合件48。成形介電層52可至少部分圍繞包含其邊緣45且在圖1之 倒裝配置中包含正面42的微電子元件40。成形介電層52可進一步將微電子元件40接合至基板12的正面14。成形介電層52可界定可與微電子元件40之背面44實質平齊或可覆蓋背面44以完全囊封微電子元件40的表面54。或者，如圖1A所見，引線之一些或所有可為梁式引線137，其等在平行於第二基板120之表面123或124之方向上延伸，且具有與孔隙126對準的部分，並且結合至第一微電子元件102的接觸件112。
基板佈線22可包含暴露在基板12之背面16上的複數個封裝端子26。封裝端子26可與封裝10A或10B之任一或兩個微電子元件40電連接且可進一步彼此互連。封裝端子26可供用於連接封裝10A或10B與該封裝10A、10B外的組件。舉例而言，封裝10A中之封裝端子26可用於連接封裝10A與暴露在可作為印刷電路板(「PCB」)或類似物之電路板70之表面上的電路接觸件72。封裝10B之封裝端子26圖解說明另一實例，其中封裝端子26可用於透過下文更詳細討論之封裝10A、10B的結構與另一封裝(諸如封裝10A)電連接。
微電子元件40沿著其等在封裝10A、10B中之各自基板12配置使得其等在第一表面14上間隔開以在其間界定互連區域18。在圖1所示之實施例中，微電子元件40經配置使得其各自邊緣表面45以間隔開方式面向彼此且實質平行於彼此以在其間界定互連區域18。但是，邊緣表面45非必須平行。在所示之實施例中，互連區域18可由微電子元件40之邊緣45限定在兩側上及由基板12之邊緣限定在其餘兩側上。在其他實施例中，互連區域18可被視作由在微電子元件40之外部之間延伸之虛邊界限定。在具有舉例而言四個微電子元件40之實施例中，互連區域18可由個別微電子元件40之邊緣45限定在四側上。在具有超過四個微電子元件之實施例中，互連區域可被微電子元件完全圍封在舉例而言與所存在的微電子元件一樣多的邊上。
複數個堆疊端子28配置在暴露為基板12之正面14之互連區域18 內。如本文所使用之術語「暴露在」並非指堆疊端子28至基板12或其間之任意相對位置上之任意特定附接方式。而是，其指示導電結構可用於與在垂直於介電結構之表面之方向上從介電結構外朝向介電結構之表面移動之理論點接觸。因此，暴露在介電結構之表面上之端子或其他導電結構可從此表面突出；可與其他表面平齊；或可相對於此表面內凹及透過介電質中之孔或凹部暴露。堆疊端子28可為可包含其不同列或行之個別端子28之陣列。端子28之其他替代配置亦可行，包含在基於與封裝10A或10B之其他元件之連接選擇之不同位置上僅具有兩個堆疊端子28或具有兩個以上端子之配置。堆疊端子28可為基板佈線22之一部分或可另外與基板佈線22連接使得堆疊端子28可與相同封裝10A或10B之微電子元件40、與其他堆疊端子28或與封裝端子26互連。
堆疊端子28可用於連接相關封裝10A或10B與覆蓋基板12之正面14之外部組件。在一實例中，複數個互連件56可與堆疊端子28連接並從其向上延伸至其可暴露在成形介電層52之表面54上之端面58。互連件56可為接合金屬或其他導電材料之銷、柱、塊體，諸如可包含焊料或金屬，諸如銅、金、銀、錫、鉍、銦、鋁、鎳等。在所示之實施例中，互連件56為遠離基板12之正面14延伸且延伸穿過成形介電層52之銷之形式。在此一實施例中，端面58可形成暴露在表面54上用於與另一組件互連之端子。在其他實施例中，端面58可被與其連接以為端子提供比端面58本身之表面積更大之表面積之接觸件覆蓋。
如圖1所示，封裝10B安裝在封裝10A上方，其可舉例而言使用可由可定位在封裝10A之表面54與封裝10B之基板12之第二表面16之間之介電材料諸如環氧樹脂或另一可固化材料形成之黏著層60完成。如上所述之導電材料或接合金屬諸如焊料或類似物之塊體可連接封裝10A之互連件56之端面58與封裝10B之封裝端子26。此配置因而提供 封裝10A之堆疊端子28與封裝10B之封裝端子26之間之連接，其可促進整個總成8中之許多其他連接。舉例而言，此配置可提供封裝10B之微電子元件40之任一者或兩者與電路板70及因此，與其連接之任意其他組件之間之連接。在另一實例中，封裝10B之微電子組件40之任一者或兩者與封裝10A之微電子組件之任一者或兩者之連接。由此一連接促進之特定連接可藉由在各封裝10A及10B內調適基板佈線22而製作，包含製作至個別堆疊端子28之特定連接。
一種製作諸如圖1所示之微電子總成8之方法可包含製作或形成上文單獨描述之組態之微電子封裝10A及10B。封裝10A及10B隨後可彼此對準使得封裝10B之相應封裝端子26與封裝10A之相應互連件56對準。封裝10B之相應封裝端子26隨後可藉由使用舉例而言接合金屬塊體62形式之導電接合材料諸如焊料或類似物而結合在一起而與其等各自互連件56之末端58電連接。黏著層60隨後可注入或另外沈積在相向表面16與54之間且圍繞接合金屬塊體62以將封裝10A及10B固定在一起。
在封裝10A中，一些封裝端子26及堆疊端子28可直接覆蓋彼此且可藉由延伸穿過基板12之通孔30電連接。在所示之特定實施例中，通孔30可暴露在其在正面14及背面16之末端上使得其各自末端分別為堆疊端子28及封裝端子26。其他實施例可行，包含其中接觸墊覆蓋通孔30以形成堆疊端子28及封裝端子26之實施例。如封裝10A所示，通孔30可與沿著背面16延伸且包含在一個或多個側向方向上從通孔30移位之封裝端子之基板佈線22連接。類似配置可行，其中基板佈線22沿著正面14延伸且包含從通孔30移位之堆疊端子28。封裝之實施例，諸如包含移位封裝端子26之封裝10A亦可覆蓋另一封裝(諸如代替封裝10B)，且此移位可補償互連件56在不同封裝中之不同空間放置或可重新分配特定連接。
如圖2所示，額外微電子封裝，諸如封裝10C及10D可包含在總成8中。在所示之實施例中，封裝10C及10D之結構類似於封裝10B使得封裝10C之封裝端子26可與封裝10B之互連件56端面58連接。類似地，封裝10D之封裝端子26可與封裝10C之互連件56端面58連接。在兩個實例中，封裝使用黏著層60接合在一起且封裝端子26可使用接合金屬塊體62與互連件56之端面58連接。如在圖1之實施例中，封裝10A、10B、10C、10D之間之互連可實現總成元件之間之許多不同互連。舉例而言，封裝10C及10D之微電子元件40可穿過封裝10A及10B連接至電路板70。此外，總成8內之微電子元件40之任意者可透過任意介入封裝之互連件56而與其餘微電子元件40之任意者連接。
製作如圖2所示之封裝8之方法可類似於用於製作圖1之封裝8之上述方法，其包含額外、類似步驟以將額外封裝10C及10D與其附接。
許多其他類型之封裝可以使用微電子元件之間之互連區域中之堆疊端子之方式連接。此外，至至外部封裝端子之此等堆疊端子之許多不同連接亦可行。在圖3A至圖3C所示之實例中，封裝110A及110B之結構分別類似於如圖1所示之封裝10A及10B。但是在圖3A至圖3C之實施例中，互連件為例如接合金屬(例如焊料、錫、銦、金或其等之組合)或其他導電接合材料(諸如導電膏、導電基質材料及其他)之導電塊體形式的接合金屬互連件156。在圖3C所示之實例中，接合金屬互連件156徑直從封裝110A之堆疊端子128延伸至封裝110B之封裝端子126。在此一實施例中，可在封裝110A之成形介電層152中製作孔以在表面154上暴露堆疊端子128。此等孔亦可在黏著層160在與封裝110B組裝前形成之情況中延伸穿過黏著層160。另外，接合材料諸如焊料可沈積在此等孔中接觸堆疊端子128且封裝110B可與封裝110A組裝且接合金屬互連件156可藉由回焊接合金屬而與封裝端子126連接。 在一實例中，黏著層160隨後可注入在封裝110A與110B之間且圍繞接合金屬互連件156之暴露部分。
在作為圖3A之變體之圖3B之實例中，堆疊端子128及封裝端子126為定位為鄰近封裝110A中之基板112之第二表面116之接觸墊134之相對表面。如所示，堆疊端子128藉由基板112中之開口136而暴露在基板112之第一表面114上。在此一實施例中，接合金屬互連件156可進一步延伸至基板112中之開口136中以與堆疊端子128結合。圖3C展示圖3B之實例之其他變體，其中接觸墊134鄰近封裝110A之基板112之第一表面114。封裝端子126藉由基板112中之開口136而暴露在第二表面116上。如上所述，焊球174延伸至開口136中以與封裝端子126連接用於與外部組件連接。圖3C中之封裝110B包含與封裝110A中類似之端子結構。接合金屬互連件156延伸穿過封裝110B之基板112中之開口136以與其封裝端子126連接。在用於製作如圖3A至圖3C所示之微電子封裝108之方法中，開口136可在與封裝110B組裝之前包含在封裝110A中。當封裝110A被提供來與封裝110B組裝時，接合金屬互連件156可包含在開口136中。接合金屬互連件156隨後可經加熱以回焊接合材料用於與封裝110B之封裝端子126結合。或者，開口136可在組裝前保留未填充，此時接合材料可以可流動狀態沈積其中且可進一步與封裝10B之封裝端子126結合。在其他替代中，開口136可填充實質與成形介電質152之表面154相平之接合金屬互連件156。在組裝時，額外接合材料可添加至其並與封裝110B之封裝端子126結合。
圖4展示其他替代配置，其中窗219形成為穿過封裝210B之基板212使得互連件可為將封裝210A之堆疊端子228直接連接至封裝210B之堆疊端子228之導線接合件之形式，諸如導線接合互連件256。在此一實施例中，封裝210B之基板佈線222可連接在堆疊端子228與位於堆疊端子228之相對面216上之導線接合件248之間。在一些情況中， 單個成形介電質250可立即形成，其囊封微電子元件240及將微電子元件240連接至基板佈線222之導線接合件248及導線接合互連件256。如圖4中進一步所示，額外堆疊端子226可在微電子元件240外之周邊區域中暴露在封裝210A之基板212之第一表面214上。類似地，額外堆疊端子228可暴露在封裝210B之基板212之第一表面214上使得額外導線接合互連件256可在其周邊區域中連接在封裝210A及210B之堆疊端子228之間。併有穿過基板窗以互連封裝之導線接合件之總成之額外實例描述於同在申請中、共同擁有之美國專利申請案第11/666,975號及第13/216/415號中，其等之揭示內容之全文以引用的方式併入本文中。
在圖5A及圖5B所示之其他變體中，封裝310A及310B可包含微電子元件340，該微電子元件340在其正面342上包含元件接觸件346。此等微電子元件340為接合在基板312上之覆晶使得元件接觸件346藉由焊球348連接至基板佈線322，包含基板312之第一表面314上之基板接觸件。圖5B之實例進一步展示延伸穿過通孔330(或其他類似結構)之金屬化通孔之形式之互連件356，其等界定封裝310B之封裝端子326及堆疊端子328以與其電連接。通孔330進一步延伸穿過封裝310A之成形介電質352及黏著層360以與封裝310A之堆疊端子328連接。在圖5B所示之實例中，通孔進一步延伸穿過封裝310B之成形介電質352使得通孔330可藉由首先形成穿過封裝310B之相應開口而製作，包含成形介電質352、堆疊端子328、封裝端子326及其間之任意結構(諸如其餘通孔330或基板312之任意部分)。此等開口進一步形成為穿過黏著層360及穿過封裝310A之成形介電質352。在一些實施例中，開口亦可延伸穿過堆疊端子328及任意相關結構，諸如通孔330。開口隨後填充導電材料，諸如銅或本文所述之另一佈線金屬。此等導電金屬可藉由電鍍或類似方法而沈積在開口中。或者，取決於開口之大小及包含 各自封裝310A及310B之厚度之其他因素，導電膏或接合金屬可沈積在開口中以達成所要電連接。參考圖5B所述用於在封裝310A與310B之間連接之通孔330可用於在本文所述之其封裝及總成之其他實例中形成類似連接。
本文所述之類型之封裝可藉由與額外封裝之封裝端子或堆疊端子連接而與類似類型之該等額外封裝組裝。在一實例中，本文所述之任意類型之封裝可以諸如圖6及圖7所示之面對面配置安裝至彼此。舉例而言，在圖6中，封裝410A及410B經定位使得其等各自介電表面454面向彼此且使得互連件456端面458互相對準。焊球462可電子連接對準之互連件456端面458且黏著層460可黏貼兩個封裝410A及410B。在類似實例中，兩個封裝可背對背與焊球附接，連接相向及對準封裝端子與各自封裝基板之相向背面之間之黏著層。此等實例可進一步經組合以組裝兩組面對面接合之封裝(諸如封裝410A及410B)。圖7展示圖6之實施例之變體，其中熱散佈器464安置在封裝410A與410B之間。熱散佈器464中包含互連件456可穿過之窗466。在另一實例中，熱散佈器464可為兩個離散熱散佈器464，互連區域418之各側上各安置一個。在此一實施例中，窗466可為界定在兩個單獨熱散佈器464之間之間隙之形式。
類似堆疊端子配置亦可併入晶圓級封裝中之多個晶粒配置中。如圖8所示，封裝510A及510B為包含兩個微電子元件540之兩個晶圓級封裝。在此情況中，基板可省略使得微電子封裝510A及510B可為具有封裝結構之微電子元件540之形式，該封裝結構包含覆蓋微電子元件540之正面542之導電重新分佈層。重新分佈層具有金屬化通孔536，其為電性傳導的且延伸穿過封裝之介電層538至微電子元件之接觸件546。重新分佈層包含封裝端子526及與端子526電連接之跡線使得端子諸如透過金屬化通孔536或透過金屬化通孔536及導電跡線而與 接觸件546電連接。在圖8之特定實施例中，其中封裝端子526及堆疊端子528安置在延伸超過微電子元件540之一或多個邊緣之介電層538之區域上，諸如在互連區域518中，封裝510A及510B可進一步被稱作「扇出晶圓級封裝」。堆疊端子528及封裝端子526可為併入介電層538內之各晶圓級封裝510A、510B之重新分佈電路522中之接觸墊534之相對表面。
如圖1之實施例中，互連件556諸如銷或類似物可延伸穿過成形介電質552且若需要，穿過介電層538至暴露在表面554上之其端面558。此結構允許封裝510B組裝在封裝510A上方，封裝510B之封裝端子與互連端面558連接。如上所述，此連接組態諸如藉由封裝510A之封裝端子526至PCB或類似物之電路接觸件之連接而促進封裝510A及510B之組件之間之許多不同特定連接及其與外部組件之連接。如圖8所示，此一連接可藉由舉例而言將封裝510A之封裝端子526直接接合至電路接觸件572而達成。或者，如圖9所示，封裝基板576可包含在經由焊球562連接至封裝510A之封裝端子526之總成508中。封裝基板576隨後可藉由連接至封裝接觸件576之焊球574而連接至電路接觸件572。在一替代實例中，如圖10所示，封裝510A之封裝端子526可導線接合至連接至封裝接觸件578之封裝基板576內之佈線。
圖11及圖12展示包含類似於圖6及圖7所示之配置之配置之晶圓級封裝510A及510B之總成508之實例。特定言之，封裝510A及510B面對面組裝，焊球562連接相向及互相對準之互連件556之端面558。黏著層560可附接在各自封裝510A及510B之相向表面554之間。圖500之實施例以與圖7類似之方式併入熱散佈器564。如上所述，面對面接合之封裝之多個子總成可組裝在一起。
如圖13所示，藉由以與參考圖2所述類似之方式繼續堆疊組裝封裝及連接鄰近之封裝端子526對及互連件556之端面558而組裝額外封 裝510C及510D。甚至圖13所示之多於四個封裝可包含在此一總成中。
如上所述，上文在圖1至圖13中所討論之任意總成可適於在各封裝中包含多於兩個電子元件。圖14至圖17展示圖8所示之類型之總成之其他實例，其在各封裝610中具有四個微電子元件640。特定言之，圖15展示可用於圖14之總成中之封裝610之俯視示意圖。在本實施例中，微電子元件640經配置使得邊緣645沿著基板612之表面614配置為正方形。此配置界定由邊緣645界定之正方形區域之互連區域618。如在上述實施例中，堆疊端子628配置為互連區域618內之基板612之正面614上之陣列。如上所述，封裝端子626暴露在基板612之背面616上且可與堆疊端子628直接對準或可從其偏移。
如圖15所示，除界定在四個微電子元件640內之互連區域618外，鄰近之微電子元件640對界定其邊緣645與基板612之邊界之間之外互連區域620。額外堆疊端子628亦可暴露在此等外互連區域620中之基板612之正面614上。在圖15中所示之實例中，四個此等外互連區域620可界定在基板612上；但是，取決於給定封裝中所包含之微電子元件之數量，可存在更多或更少外互連區域。
在圖14及圖15所示之類型之封裝610之總成608中，不同互連區域618及620內之堆疊端子628可取決於其位置用於攜載不同信號或可與微電子元件640之不同組合互連。舉例而言，互連區域618內之堆疊端子628可與超過一個微電子元件640互連以攜載共同信號至微電子元件640之兩者、三者或所有。如圖15所示，一此堆疊端子628A可與所有微電子元件640連接。在其他實例中，外互連區域620內之堆疊端子可僅與限定其之微電子元件640之一者或與限定該特定外互連區域640之微電子元件之兩者連接。在一實施例中，外互連區域640內之堆疊端子628C可僅與微電子元件640C之最靠近一者連接以攜載專門於該 微電子元件之信號。其餘堆疊端子可根據此方案與不同微電子元件640連接。如此連接可能歸因於堆疊端子628與微電子元件640之間之相對距離而有利，此係因為外互連區域620中之堆疊端子628在相對微電子元件(諸如微電子元件640A與640B)之間的距離可能太不同以攜載共同信號。此可歸因於此等信號到達微電子元件640之更遠者所需之額外時間。相反地，互連區域618內之堆疊端子628可在距離上足夠靠近所有微電子元件640以可靠地攜載共同信號。
在本發明之特定實施例中，封裝中之微電子元件包含經組態以提供記憶體儲存陣列功能的微電子元件。舉例而言，微電子元件可提供動態隨機存取記憶體(「DRAM」)功能，且在一些情況中可包含或可為專用DRAM晶片。在此情況中，互連區域中之堆疊端子628可經組態以攜載一組命令位址匯流排信號的全部至第二微電子封裝601B。具有經組態以攜載命令、位址及定時信號之位於中心之端子的封裝可如2011年7月12日申請之共同擁有的美國臨時專利申請案第61/506,889號(「'889申請案」)、2011年10月3日申請之美國臨時專利申請案第61/542,488號(「'488申請案」)及2011年10月3日申請之美國臨時專利申請案第61/542,553號(「'553申請案」)進一步所述，該等'889、'488及'553申請案之揭示內容以引用的方式併入本文中。通常，命令位址匯流排信號可藉由匯流排在電路板(諸如印刷電路板或模組卡)上傳送至多個平行微電子封裝，尤其至安裝至電路板之相同或相對表面的微電子封裝。在一實例中，此一電路板可為母板或單列直插式記憶體模組或「SIMM」或雙列直插式記憶體模組或「DIMM」模組板。在特定實例中，互連區域的命令位址匯流排信號端子可經組態以攜載一組命令信號、位址信號、記憶庫位址信號及時脈信號的全部，其中命令信號係寫入啟用、列位址選通及行位址選通，且時脈信號係用於對位址信號取樣的取樣時脈。雖然時脈信號可 為不同類型，但是在一實施例中，由此等端子攜載之時脈信號可為接收為差動或真實及互補時脈信號的一對或多對差動時脈信號。在又一實例中，與堆疊端子對準或安置在基板之向外表面上的封裝端子亦可包含用於與電路板相配或用於與相同封裝之堆疊端子相配的命令位址匯流排信號端子。
在一實施例中，微電子封裝可在功能上等效於SIMM或DIMM，且封裝之互連區域中之堆疊端子及連接至其之封裝端子可經組態以攜載一組命令位址匯流排端子的全部；即，命令信號、位址信號、記憶庫位址信號及時脈信號的全部被傳送至封裝，命令信號係寫入啟用、列位址選通及行位址選通，且時脈信號係用於對位址信號取樣的取樣時脈。在特定實施例中，亦如'488申請案所述，封裝可併入緩衝元件，例如其積體電路，其經組態以再生封裝端子上所接收的命令位址匯流排信號，並在堆疊端子上將再生信號傳輸至可與其組裝在一起的額外封裝。在此情況中，微電子封裝可在功能上等效於暫存DIMM或「RDIMM」。在另一實例中，微電子封裝可在功能上等效於負載減小之DIMM(「LRDIMM」)，在該情況中，緩衝元件可經組態以再生由微電子封裝接收之資料信號的全部，並將其傳輸至與之組裝在一起的一或多個額外微電子封裝。
在特定實例中，微電子封裝可經組態以在時脈循環中平行傳送，即由封裝接收或從封裝傳輸三十二個資料位元。在另一實例中，微電子封裝可經組態以在時脈循環中平行傳送六十四個資料位元。許多其他資料傳送數量可行，其間將僅提及一些此等傳送數量而非限制。舉例而言，封裝可經組態以每時脈循環傳送72個資料位元，其可包含代表資料之一組64個下伏位元及作為64個下伏位元之誤差校正碼(「ECC」)位元之8個位元。九十六個資料位元、108個位元(資料及ECC位元)、128個資料位元及144個位元(資料及ECC位元)係微電子封 裝可經組態以支援之每循環之資料傳送寬度之其他實例。
圖16及圖17展示微電子元件640可如何配置為四微電子元件封裝610之額外實例。在圖16中，微電子元件640錯開且不重疊(如其等在圖15中般)，其免去外互連區域620。特定言之，圖16之配置之微電子元件640可描述為具有沿著與另一微電子元件640之相鄰內邊緣表面645A相交之平面延伸之內邊緣表面645A。在此一實施例中，互連區域618內之堆疊端子628可攜載共同及特定信號兩者。如圖16所述，基板612可延伸至微電子元件640所覆蓋之區域外以界定圍繞微電子元件640且在其中包含堆疊端子628之連續外互連區域620。此等堆疊端子628可與相鄰微電子元件連接以用被微電子元件640圍繞之互連區域618內之堆疊端子628所攜載之共同信號攜載特定於該元件之信號。
在圖17中，如在圖15之實施例中，展示微電子元件640之非重疊配置，其界定在其中具有堆疊端子628之外互連區域620。在此一配置中，內邊緣表面645A沿著平面延伸使得各微電子元件640定位在由相鄰微電子元件640之內邊緣表面645A界定之兩個此等平面之間。如本文中所使用，「在……之間」可包含微電子元件與此一平面相切之配置。
本文所述之連接組件之不同實施例可結合各種不同電子系統使用。如圖18所示，上述互連組件可用於構建不同電子系統。舉例而言，根據本發明之其他實施例之系統1可包含微電子總成8，其為由微電子封裝10A及10B之總成形成之單元，類似於圖1所示之微電子總成8。所示之實施例以及如上所述之微電子總成之其他變體可結合其他電子組件6及3使用。在所描繪之實例中，組件6可為半導體晶片或封裝或包含半導體晶片之其他總成，而組件3為顯示螢幕、但是可使用任意其他組件。當然，雖然為方便闡釋在圖18中僅描繪兩個額外組件，但是系統可包含任意數量之此等組件。在又一變體中，可使用包 含微電子元件及互連組件之任意數量之微電子總成。微電子總成及組件6及3安裝在虛線示意描繪之共同外殼4中且根據需要彼此電互連以形成所要電路。在所展示之例示性系統中，系統包含電路板70諸如可撓印刷電路板，且電路板包含將組件彼此互連之許多導體72。但是此僅係例示性的；可使用用於製作電連接之任意適當結構，包含可連接至接觸墊或類似物或與接觸墊或類似物整合之許多跡線。此外，電路板70可使用焊球74或類似物連接至總成8。外殼4描繪為可使用類型之可攜式外殼，舉例而言，在蜂巢式電話或個人數位助理中，且螢幕3暴露於外殼之表面上。在系統1包含光敏元件諸如成像晶片的情況下，亦可提供透鏡5或其他光學裝置將光路由至結構。再次，圖18所示之簡化系統1僅為例示性的；其他系統，包含通常被視作固定結構之系統，諸如桌上型電腦、路由器及類似物可使用上述結構製作。
雖然本文已參考特定實施例進行描述，但是應瞭解此等實施例僅闡釋本揭示內容之原理及應用。因此，應瞭解可對闡釋性實施例進行衆多修改且設計其他配置而不脫離如隨附申請專利範圍所定義之本揭示內容之精神及範疇。
8‧‧‧微電子總成
10A‧‧‧微電子封裝
10B‧‧‧微電子封裝
12‧‧‧基板
14‧‧‧第一表面/正面
16‧‧‧第二表面/背面
22‧‧‧基板佈線
24‧‧‧基板接觸件
26‧‧‧封裝端子
28‧‧‧堆疊端子
32‧‧‧窗
40‧‧‧微電子元件
42‧‧‧正面
44‧‧‧背面
45‧‧‧邊緣
48‧‧‧導線接合件
50‧‧‧囊封劑
52‧‧‧成形介電層
54‧‧‧表面
56‧‧‧互連件
58‧‧‧端面
60‧‧‧黏著層
62‧‧‧接合金屬塊體
70‧‧‧電路板
72‧‧‧導體
74‧‧‧焊球

Claims (42)

  1. 一種微電子總成，其包括：一第一微電子封裝，其包含：一基板，其具有第一及第二相對表面以及其上之基板接觸件；第一微電子元件及第二微電子元件，其等各具有與該等基板接觸件電連接之元件接觸件，該第一微電子元件及該第二微電子元件在該第一表面上彼此間隔開，以提供該第一微電子元件與該第二微電子元件之間之該第一表面之一互連區域；第三微電子元件及第四微電子元件，其等在該第一微電子元件與該第二微電子元件之間之該互連區域之相對側上相隔；複數個封裝端子，其等在該第二表面上與該等基板接觸件電互連以連接該封裝與該封裝外之一組件；及複數個堆疊端子，其等暴露在該互連區域中之該第一表面上，以連接該封裝與覆蓋該基板之該第一表面之一組件；及一第二微電子封裝，其覆蓋該第一微電子封裝且具有結合至該第一微電子封裝之該等堆疊端子之端子。
  2. 如請求項1之微電子總成，其中該等封裝端子及該等堆疊端子彼此覆蓋成各自電連接對。
  3. 如請求項2之微電子總成，其中該等封裝端子及該等堆疊端子為穿過該基板之導電通孔之相對末端。
  4. 如請求項1之微電子總成，其中該等堆疊端子之額外者在其在該互連區域外之一部分中之該基板之該第一表面上。
  5. 如請求項4之微電子總成，其中該等堆疊端子之至少一些與該第一微電子元件及該第二微電子元件兩者連接。
  6. 如請求項5之微電子總成，其中與該第一微電子元件及該第二微電子元件之兩者連接之該等堆疊端子之至少一些經組態以攜載命令、位址及定時信號之至少一者。
  7. 如請求項1之微電子總成，其中該等堆疊端子之額外者定位在由該等微電子元件之相鄰者限定之該基板之一角隅區域中。
  8. 如請求項1之微電子總成，其中該第三微電子元件及該第四微電子元件分別在其鄰近藉此界定之該互連區域之角隅的角隅區域中與該第一微電子元件及該第二微電子元件重疊。
  9. 如請求項1之微電子總成，其中該第一微電子元件、該第二微電子元件、該第三微電子元件及該第四微電子元件之各者具有界定該互連區域之一側之一邊緣，且其中該等邊緣表面之各者沿著與一相鄰微電子元件之該邊緣表面相交之一平面延伸。
  10. 如請求項1之微電子總成，其中該第一微電子元件、該第二微電子元件、該第三微電子元件及該第四微電子元件之各者具有界定該互連區域之一側之至少一部分之一邊緣表面，且其中該等邊緣表面之各者沿著一平面延伸，該等微電子元件之各者定位在兩個相鄰平面之間。
  11. 如請求項1之微電子總成，其中該第一微電子封裝進一步包含覆蓋該基板之該第一表面之至少一部分之一成形囊封層，且其中該等第一導電互連件之至少部分包括延伸穿過該成形囊封層至暴露末端之第一導電通孔。
  12. 如請求項1之微電子總成，其中該第一微電子元件及該第二微電子元件之接觸件支承面面向該基板，該等基板接觸件包含暴露在該第二表面上之基板接觸件，且其中該等元件接觸件藉由導 線接合件與該等基板接觸件連接。
  13. 如請求項1之微電子總成，其包含暴露在該第一表面上之基板接觸件，且其中該第一微電子元件及該第二微電子元件之該等元件接觸件面向暴露在該第一表面上之該等基板接觸件，並與其結合。
  14. 如請求項1之微電子總成，其中該第二微電子封裝包含安裝在一第二基板上之一第五微電子元件，該等端子在該第二基板上並與該第五微電子元件電連接。
  15. 如請求項1之微電子總成，其中該第二微電子封裝包含具有第一及第二間隔開表面之一基板及安裝在其該第二表面上之第五微電子元件及第六微電子元件，該第五微電子元件及該第六微電子元件在該第二封裝之該基板上間隔開，以在其中界定一互連區域，且該等端子暴露在該互連區域內之該第二封裝之該基板之該第二表面上，該第二封裝之該基板進一步包含在其該第一表面與該第二表面之間延伸穿過之一窗，且其中該第二封裝之該等端子藉由延伸穿過該窗之導線接合件結合至該第一封裝之該等堆疊端子。
  16. 如請求項15之微電子總成，其中該第一封裝之該基板界定圍繞該第一微電子元件及該第二微電子元件之至少一者之一周邊區域，額外堆疊端子位於該周邊區域中，其中該第二封裝之該基板界定圍繞該第五微電子元件及該第六微電子元件之至少一者之一周邊區域及限定該周邊區域之一周緣，額外端子位於其該周邊區域中，且其中該第一封裝之該等額外堆疊端子之至少一些藉由延伸經過該第二封裝之該基板之該周緣的導線接合件與該第二封裝之該等額外端子的至少一些結合。
  17. 如請求項1之微電子總成，進一步包含下伏於該第一微電子封裝 且具有結合至該第一微電子封裝之該等封裝端子之端子之一第三微電子封裝。
  18. 如請求項1之微電子總成，進一步包含具有暴露在其一表面上之電路接觸件之一電路板，其中該第一微電子封裝之該等封裝端子與該等電路接觸件電連接。
  19. 如請求項1之微電子總成，其中該等第二微電子封裝端子為封裝端子或堆疊端子之至少一者。
  20. 如請求項19之微電子總成，其中該第一封裝之該等堆疊端子與該第二封裝之該等封裝端子電連接。
  21. 如請求項19之微電子總成，其中該第一封裝及該第二封裝之堆疊端子電連接。
  22. 如請求項21之微電子總成，進一步包含在該第一微電子封裝與該第二微電子封裝之間之一熱散佈器。
  23. 如請求項22之微電子總成，其中該熱散佈器包含形成為穿過該熱散佈器、覆蓋該互連區域之至少一部分之一孔隙，該第二微電子封裝之該等堆疊端子透過該孔隙與該第一微電子封裝之該等堆疊端子連接。
  24. 如請求項22之微電子總成，其中該熱散佈器係一第一熱散佈器，該總成進一步包含一第二熱散佈器，該第一熱散佈器安置在該互連區域之一第一側上，且該第二熱散佈器安置在該互連區域之一第二側上，一間隙界定在該第一熱散佈器與該第二熱散佈器之間，該第二微電子封裝之該等堆疊端子透過該間隙與該第一微電子封裝之該等堆疊端子連接。
  25. 一種微電子總成，其包括：一第一微電子封裝，其包含：第一微電子元件及第二微電子元件，其等各具有其正面及 背面及暴露在該等各自正面上之元件接觸件，該第一微電子元件及該第二微電子元件彼此側向間隔開，以在其間提供一互連區域；第三微電子元件及第四微電子元件，其等在該第一微電子元件與該第二微電子元件之間之該互連區域之相對側上相隔；一介電層，其具有覆蓋該第一微電子元件及該第二微電子元件之該等正面且背向該等微電子元件之該等正面之一表面，該介電層進一步具有與該第一表面相對之一第二表面；複數個封裝端子，其等暴露在該介電層之該第一表面上，且透過沿著該介電層延伸之跡線及從該等跡線延伸且接觸該等元件接觸件的第一金屬化通孔與該等元件接觸件電連接；及複數個堆疊端子，其等暴露在該介電層之該第二表面上，且與該等封裝端子電連接以連接該封裝與覆蓋該介電層之該第二表面之一組件；及一第二微電子封裝，其覆蓋該第一微電子封裝，且具有結合至該第一微電子封裝之該等堆疊端子之端子。
  26. 如請求項25之總成，其中該第一封裝進一步包含：一成形囊封層，其至少部分圍繞該互連區域內之該第一微電子元件及該第二微電子元件，且界定其覆蓋該介電層之該第二表面之一表面；及導電互連件，其等與該等堆疊端子電連接，且具有暴露在該成形囊封層之該表面上之端面。
  27. 一種微電子總成，其包括：一第一封裝，其包含： 一基板，其具有第一及第二相對表面；第一微電子元件及第二微電子元件，其等各具有與該第一表面上之相應基板接觸件電連接的元件接觸件，該第一微電子元件及該第二微電子元件在該第一表面上彼此間隔開，以提供該第一微電子元件與該第二微電子元件之間之該第一表面之一互連區域；第三微電子元件及第四微電子元件，其等在該第一微電子元件與該第二微電子元件之間之該互連區域之相對側上相隔；複數個封裝端子，其等在該第二表面上與該等基板接觸件電互連以連接該封裝與該封裝外之一組件；複數個堆疊端子，其等暴露在該互連區域中之該基板之該第一表面上，且與該等封裝端子之至少一些電連接；一第二微電子封裝，其覆蓋該第一微電子封裝且具有端子；複數個導電互連件，其等結合在該第一微電子封裝之該等堆疊端子與該第二微電子封裝之該等端子之間。
  28. 如請求項27之微電子總成，其中該第二微電子封裝進一步包含：一第二介電層，其具有第一及第二相對表面；及至少一微電子元件，其安裝在該介電層之該第一表面上。
  29. 一種微電子總成，其包括：一第一封裝，其包含：一基板，其具有第一及第二相對表面；四個微電子元件，其等各具有與該第一表面上之相應基板接觸件電連接的元件接觸件，該等微電子元件配置在該第一表面上，以界定被該等微電子元件圍繞之該第一表面之一互連區域； 複數個封裝端子，其等在該第二表面上與該等基板接觸件電互連，以連接該封裝與該封裝外之一組件；及複數個堆疊端子，其等在該互連區域中之該第一表面上與該等封裝端子電連接；一第二微電子封裝，其覆蓋該第一微電子封裝且具有端子；導電互連件，其等結合於該第一微電子封裝之該等堆疊端子與該第二微電子封裝之該等端子之間。
  30. 如請求項29之微電子總成，其中該等微電子元件之各者包含鄰近該互連區域之一周緣，使得該內部互連區域被界定為一矩形區域。
  31. 如請求項29之微電子總成，其中該等第一堆疊端子之至少一些與該等第一微電子元件之至少兩者電連接。
  32. 一種微電子總成，其包括：一第一封裝，其包含：一基板，其具有第一及第二相對表面；第一微電子元件及第二微電子元件，其等各具有與該第一表面上之相應基板接觸件電連接之元件接觸件，該第一微電子元件及該第二微電子元件在該第一表面上彼此間隔開，以提供該第一微電子元件與該第二微電子元件之間之該第一表面之一互連區域；第三微電子元件及第四微電子元件，其等在該第一微電子元件與該第二微電子元件之間之該互連區域之相對側上相隔；複數個接觸墊，其等具有暴露在該基板之該第二表面上之表面，該等接觸墊之該等表面界定與該等基板接觸件電互連以連接該封裝與該封裝外之一組件的封裝端子；及 一成形囊封層，其覆蓋該基板之該第一表面的至少一部分並界定一囊封表面；及一第二微電子封裝，其接合至該囊封表面，且具有面向該囊封表面之端子；複數個導電通孔，其等至少延伸穿過該成形囊封層並連接該第一微電子封裝之該等接觸墊與該第二微電子封裝之該等端子。
  33. 如請求項32之總成，其中該等導電通孔進一步延伸穿過與其電接觸之該第一封裝之該等接觸墊。
  34. 如請求項32之總成，其中該第二微電子封裝進一步包含具有第一及第二間隔開表面之一基板，該第二表面接合至該囊封表面，其中該第二封裝之該等端子係暴露在該基板之該第二表面上之導電墊的表面，且其中該等導電通孔進一步延伸穿過與其電接觸之該第二封裝之該等導電墊。
  35. 一種系統，其包括如請求項1之微電子總成及電連接至該微電子總成之一或多個其他電子組件。
  36. 一種用於製作一微電子總成之方法，其包括：組裝一第一微電子封裝與一第二微電子封裝，該第二微電子封裝覆蓋該第一微電子封裝，且在其上具有端子，該第一微電子封裝包含：一基板，其具有第一及第二相對表面及其上之基板接觸件；第一微電子元件及第二微電子元件，其等各具有與該等基板接觸件電連接之元件接觸件，該第一微電子元件及該第二微電子元件在該第一表面上彼此間隔開，以提供該第一微電子元件與該第二微電子元件之間之該第一表面之一互連區 域；第三微電子元件及第四微電子元件，其等在該第一微電子元件與該第二微電子元件之間之該互連區域之相對側上相隔；複數個封裝端子，其等在該第二表面上與該等基板接觸件電互連，以連接該封裝與該封裝外之一組件；及複數個堆疊端子，其等暴露在該互連區域中之該第一表面上，用以連接該封裝與覆蓋該基板之該第一表面之一組件；及連接該第二微電子封裝之該等端子與該第一微電子封裝之該等堆疊端子，以在其間形成一電連接。
  37. 如請求項36之方法，其中連接該第二微電子封裝之該等端子與該第一微電子封裝之該等堆疊端子之該步驟包含至少在其該互連區域中將該等封裝端子結合至覆蓋該基板之該第一表面之該第一微電子封裝之一囊封層上之互連件的暴露末端，該等互連件結合至與其該等暴露末端相對之該等堆疊端子。
  38. 如請求項36之方法，其中連接該第二微電子封裝之該等端子與該第一微電子封裝之該等堆疊端子之該步驟包含至少在該互連區域中將導電接合材料塊體沈積至覆蓋該基板之該第一表面之該第一微電子封裝之一囊封層內的孔中，該等堆疊端子暴露在該等孔內之該囊封層之一表面上，且其中該等導電接合材料塊體結合至該第二封裝之該等端子及該第一封裝之該等堆疊端子。
  39. 如請求項36之方法，其中連接該第二微電子封裝之該等端子與該第一微電子封裝之該等堆疊端子之該步驟包含：至少在其該互連區域中形成複數個孔，使其至少穿過覆蓋該 基板之該第一表面之該第一微電子封裝之一囊封劑，該複數個孔與其第一末端上之該等堆疊端子之各自者及其第二末端上之該第二封裝之該等端子之相應者對準；及用與該第一微電子封裝之該等堆疊端子及該第二封裝之該等封裝端子接觸之一導電材料來填充該等孔。
  40. 如請求項39之方法，其中該等孔進一步形成為穿過該第一封裝之該基板及穿過其該等各自堆疊端子。
  41. 如請求項39之方法，其中該等孔進一步形成為穿過該第二封裝之一基板及穿過其該等相應端子。
  42. 如請求項36之方法，其中連接該第二微電子封裝之該等端子與該第一微電子封裝之該等堆疊端子之該步驟促進該第一封裝之該第一微電子元件、該第二微電子元件、該第三微電子元件及該第四微電子元件與該第二封裝之間之一連接。
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US20150200183A1 (en) 2015-07-16
TW201342546A (zh) 2013-10-16
KR101925427B1 (ko) 2019-02-27
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US20140199811A1 (en) 2014-07-17
US9911717B2 (en) 2018-03-06
US20180261571A1 (en) 2018-09-13
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US8680684B2 (en) 2014-03-25
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US10468380B2 (en) 2019-11-05
US20130175699A1 (en) 2013-07-11

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