TWI538762B - 銲球凸塊與封裝結構及其形成方法 - Google Patents

銲球凸塊與封裝結構及其形成方法 Download PDF

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TWI538762B
TWI538762B TW103100145A TW103100145A TWI538762B TW I538762 B TWI538762 B TW I538762B TW 103100145 A TW103100145 A TW 103100145A TW 103100145 A TW103100145 A TW 103100145A TW I538762 B TWI538762 B TW I538762B
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Taiwan
Prior art keywords
wafer
ppm
silver alloy
solder
substrate
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TW103100145A
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English (en)
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TW201527029A (zh
Inventor
莊東漢
蔡幸樺
李俊德
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樂金股份有限公司
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Priority to TW103100145A priority Critical patent/TWI538762B/zh
Priority to CN201410133209.5A priority patent/CN104766849B/zh
Priority to US14/256,233 priority patent/US9425168B2/en
Priority to DE102014106714.2A priority patent/DE102014106714B4/de
Priority to KR1020140064122A priority patent/KR20150081223A/ko
Priority to JP2014261033A priority patent/JP6050308B2/ja
Publication of TW201527029A publication Critical patent/TW201527029A/zh
Application granted granted Critical
Publication of TWI538762B publication Critical patent/TWI538762B/zh

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Description

銲球凸塊與封裝結構及其形成方法
本發明是關於銲球凸塊結構、其封裝結構及其形成方法,特別是關於具有銀合金銲球凸塊結構的銲球凸塊結構、其封裝結構及其形成方法。
覆晶組裝(Flip Chip Assembly)具有接點數高、接點間距小、封裝面積小、高頻性能佳、可靠度高以及耐電磁波干擾等優點,已普遍採用於積體電路及發光二極體(LED)等電子產品封裝製程中。覆晶組裝最重要的關鍵技術在於凸塊(Bump)的製作及組裝。覆晶凸塊材料大多使用銲錫(Solder)合金,例如:錫-37鉛、錫-9鋅、錫-0.7銅、錫-3.5銀、錫-51銦、錫-58鉍、錫-3銀-0.5銅、錫-9鋅-3鉍等各種合金組成。銲錫凸塊(Solder Bump)的製作方法主要可分為電鍍(Electroplating)及錫膏鋼版印刷(Stencil Printing)兩種。電鍍法除了環保問題,且難以形成特定的合金組成。此外,在形成無鉛銲錫時,很難找到適當鍍液配方與電鍍製程參數。例如,欲形成凸塊如錫-3.5銀、錫-0.7銅及錫-3銀-0.5銅時,其合金組成很難穩定控制;欲形成銲球凸塊如錫-51銦、錫-58鉍及錫-9鋅-3鉍時,則難以找到理想鍍液。
因此,近年來大部分封裝廠針對覆晶組裝銲錫凸塊的製作均逐漸以錫膏(solder paste)鋼版印刷(Stencil Printing)為主。然而,覆晶錫膏的關鍵材料在於錫粉(tin powder)。一般而言,在表面實裝(Surface Mount Technology;SMT)所使用之錫粉粒徑大約為30μm至50μm,這樣的尺寸在製造上較為容易。然而,由於覆晶凸塊的尺寸在120μm以下,其錫膏所使用錫粉粒徑必須大約在10μm以下,故其製作與粒徑篩選困難度均相當高。此外,當覆晶銲球凸塊尺寸減小至100μm以下甚至達到50μm時,即使使用尺寸在10μm以下的錫粉,其單顆銲錫凸塊仍只有少數幾個錫粉分佈其中,故於迴銲(reflow)後將造成很嚴重的共平面度(Coplanarity)問題。另外,以錫膏製作覆晶凸塊的問題還包括助銲劑(flux)迴銲後會留下空孔,以及在接點間距小至100μm以下時,錫膏鋼版印刷不良率大增等問題。
覆晶組裝導電凸塊亦可利用電鍍方法製作金凸塊(Electroplating Gold Bump),或者利用金線結球製作金銲球凸塊(Gold Stud Bump),然而不論是電鍍金凸塊或金銲球凸塊在與鋁銲墊接合時,均會發生介金屬化合物(Intermetallic Compounds)成長太快,以至於接合界面脆化之問題;另外,如果採用傳統軟銲(Soldering)技術進行金凸塊與基板的組裝,由於金在銲錫的溶解速度極快,將使大量金凸塊溶入銲錫內部而形成大量脆性的AuSn4介金屬化合物,因此電鍍金凸塊或金銲球凸塊進行晶片與基板的組裝一般只能採用導電膠接合,不僅導電性較銲錫接合差,更喪失了銲錫接合的自我對位(Self Alignment)與可重工(Reworkable)兩大優點;當然金凸塊在材 料成本上亦極為昂貴。
因此電子產業亦有考慮利用電鍍方法製作銅凸塊(Electroplating Copper Bump)或銅柱(Copper Pillar),或者利用金線結球製作銅銲球凸塊(Copper Stud Bump),然而不論是電鍍銅凸塊、銅柱或銅銲球凸塊在與鋁銲墊接合時,均會發生介金屬化合物成長太慢以至於接合界面虛銲的顧慮;另外,銅易氧化及腐蝕,其封裝產品可靠度不佳;更為嚴重的是銅的硬度太高,製作銅銲球凸塊時易造成晶片破裂(Chip Cratering),在與基板組裝時亦會發生共平面(Coplanarity)問題,此一共平面問題在超小間距(Ultrafine Pitch)封裝時尤其嚴重。
有鑑於此,本發明的一實施例是提供一種銲球凸塊結構,包括:一第一基板;以及一第一銀合金銲球凸塊,設置於上述第一基板上,其中上述第一銀合金銲球凸塊的組成是選自下列組成之族群之一:組成1:0.01~10重量%的鈀與餘量的銀;組成2:0.01~10重量%的鈀、0.01至10重量%的鉑與餘量的銀;組成3:0.01~10重量%的鈀、0.01至10重量%的鉑、0.01至10重量%的金與餘量的銀;組成4:0.01~10重量%的鈀、10至800ppm的微量金屬與餘量的銀,其中上述微量金屬包含10至600ppm的鈹、10至100ppm的鈰、10至100ppm的鑭中的至少一種;組成5:0.01~10重量%的鈀、0.01至10重量%的鉑、10至800ppm的微量金屬與餘量的銀,其中上述微量金屬包含10至600ppm的鈹、10至100ppm的鈰、10至100ppm的鑭中的至少一種;組成6:0.01~10重量%的鈀、0.01至10重量%的金、10 至800ppm的微量金屬與餘量的銀,其中上述微量金屬包含10至600ppm的鈹、10至100ppm的鈰、10至100ppm的鑭中的至少一種;以及組成7:0.01~10重量%的鈀、0.01至10重量%的鉑、0.01至10重量%的金、10至800ppm的微量金屬與餘量的銀,其中上述微量金屬包含10至600ppm的鈹、10至100ppm的鈰、10至100ppm的鑭中的至少一種。
本發明的另一實施例是提供一種封裝結構,包含:一第一晶片,具有一晶片上銲墊;一晶片上銀合金銲球凸塊,設置於上述第一晶片的上述晶片上銲墊上;以及一基板,藉由與上述第一晶片覆晶接合的形式,以其一基板上銲墊電性連接於晶片上銀合金銲球凸塊;其中上述晶片上銀合金銲球凸塊是選自下列組成之族群之一:組成1:0.01~10重量%的鈀與餘量的銀;組成2:0.01~10重量%的鈀、0.01至10重量%的鉑與餘量的銀;組成3:0.01~10重量%的鈀、0.01至10重量%的鉑、0.01至10重量%的金與餘量的銀;組成4:0.01~10重量%的鈀、10至800ppm的微量金屬與餘量的銀,其中上述微量金屬包含10至600ppm的鈹、10至100ppm的鈰、10至100ppm的鑭中的至少一種;組成5:0.01~10重量%的鈀、0.01至10重量%的鉑、10至800ppm的微量金屬與餘量的銀,其中上述微量金屬包含10至600ppm的鈹、10至100ppm的鈰、10至100ppm的鑭中的至少一種;組成6:0.01~10重量%的鈀、0.01至10重量%的金、10至800ppm的微量金屬與餘量的銀,其中上述微量金屬包含10至600ppm的鈹、10至100ppm的鈰、10至100ppm的鑭中的至少一種;以及組成7:0.01~10重量%的鈀、0.01至10重量% 的鉑、0.01至10重量%的金、10至800ppm的微量金屬與餘量的銀,其中上述微量金屬包含10至600ppm的鈹、10至100ppm的鈰、10至100ppm的鑭中的至少一種。
本發明的又另一實施例是提供一種封裝結構的形成方法,包含:提供一銀合金銲線;燒熔上述銀合金銲線的一端以形成一球狀物;將上述球狀物接合至一第一晶片的一晶片上銲墊上;截斷上述銀合金銲線,使得上述球狀物留在上述晶片上銲墊上以形成一晶片上銀合金銲球凸塊;以及以覆晶接合,將上述第一晶片經由上述晶片上銀合金銲球凸塊電性接合於一基板的一基板上銲墊;其中上述銀合金銲線是選自下列組成之族群之一:組成1:0.01~10重量%的鈀與餘量的銀;組成2:0.01~10重量%的鈀、0.01至10重量%的鉑與餘量的銀;組成3:0.01~10重量%的鈀、0.01至10重量%的鉑、0.01至10重量%的金與餘量的銀;組成4:0.01~10重量%的鈀、10至800ppm的微量金屬與餘量的銀,其中上述微量金屬包含10至600ppm的鈹、10至100ppm的鈰、10至100ppm的鑭中的至少一種;組成5:0.01~10重量%的鈀、0.01至10重量%的鉑、10至800ppm的微量金屬與餘量的銀,其中上述微量金屬包含10至600ppm的鈹、10至100ppm的鈰、10至100ppm的鑭中的至少一種;組成6:0.01~10重量%的鈀、0.01至10重量%的金、10至800ppm的微量金屬與餘量的銀,其中上述微量金屬包含10至600ppm的鈹、10至100ppm的鈰、10至100ppm的鑭中的至少一種;以及組成7:0.01~10重量%的鈀、0.01至10重量%的鉑、0.01至10重量%的金、10至800ppm的微量金屬與餘量的銀,其中上述微量金 屬包含10至600ppm的鈹、10至100ppm的鈰、10至100ppm的鑭中的至少一種。
102、104、106、108、110、112、114‧‧‧步驟
200‧‧‧銀合金銲線
202‧‧‧第一晶片
204‧‧‧晶片上銲墊
206‧‧‧球狀物
208‧‧‧晶片上銀合金銲球凸塊
260‧‧‧界面
614‧‧‧黏膠
615‧‧‧銲錫
616‧‧‧基板
618‧‧‧基板上銲墊
第1圖顯示在本發明一實施例中形成銀合金銲球凸塊結構及其覆晶組裝的流程圖。
第2圖是一側視圖,顯示在本發明一實施例中形成銲球凸塊的過程的示意圖。
第3圖是一側視圖,顯示在本發明一實施例中形成銲球凸塊的過程的示意圖。
第4圖是一側視圖,顯示在本發明一實施例中形成銲球凸塊的過程的示意圖。
第5圖是一側視圖,顯示在本發明一實施例中形成銲球凸塊的過程的示意圖。
第6圖顯示在本發明一實施例中利用黏膠進行銀合金銲球凸塊覆晶組裝的方法。
第7圖顯示在本發明一實施例中利用銲錫進行銀合金銲球凸塊覆晶組裝的方法。
第8圖顯示在本發明一實施例中利用熱壓進行銀合金銲球凸塊覆晶組裝的方法。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂,下文特舉出較佳實施例,並配合所附圖式,作詳細說明如下:
要瞭解的是本說明書以下的揭露內容提供許多不同的實施例或範例,以實施本發明的不同特徵。而本說明書以下的揭露內容是敘述各個構件及其排列方式的特定範例,以求簡化發明的說明。當然,這些特定的範例並非用以限定本發明。例如,若是本說明書以下的揭露內容敘述了將一第一特徵形成於一第一特徵之上或上方,即表示其包含了所形成的上述第一特徵與上述第二特徵是直接接觸的實施例,亦包含了尚可將附加的特徵形成於上述第一特徵與上述第二特徵之間,而使上述第一特徵與上述第二特徵可能未直接接觸的實施例。另外,本說明書以下的揭露內容可能在各個範例中使用重複的元件符號,以使說明內容更加簡化、明確,但是重複的元件符號本身不會使不同的實施例及/或結構彼此具有特定的關係。
另外,在本案專利說明書中,在數值相關敘述後接「以上」、「以下」之詞來敘述數值範圍的情況中,除非另有加註,相關的數值範圍是包含上述「以上」、「以下」之詞前接的數值。
本案專利說明書所指「積體電路」可以是例如:邏輯電路及其周邊電路、揮發性記憶體電路及其周邊電路、非揮發性記憶體電路及其周邊電路、發光元件及其關聯電路與周邊電路、感光元件及其關聯電路與周邊電路、微機電裝置及其關聯電路與周邊電路、測試用電路、其他種類的積體電路中的一種或二種以上的組合。
第1圖顯示在本發明一實施例中利用銀合金銲球凸塊進行晶片與基板覆晶組裝之流程圖。在步驟102中,提供 銀合金銲線。在步驟104中,燒熔銀合金銲線的一端以形成一球狀物。在步驟106中,將上述球狀物接合至晶片上。在步驟108中,截斷銀合金銲線,使得上述球狀物留在晶片上以形成晶片上銀合金銲球凸塊。在步驟110中,利用此晶片上銀合金銲球凸塊使上述第一晶片與基板完成覆晶組裝,亦即將已形成晶片上銀合金銲球凸塊之第一晶片覆晶組裝至上述基板上的基板上銲墊。
第2至5圖是一系列的側視圖,顯示在本發明一實施例中形成銲球凸塊的過程的示意圖。
請參考第1、2圖,在步驟102中,提供銀合金銲線200。此外,可預備第一晶片202及晶片上銲墊204,並將銀合金銲線200引到第一晶片202之晶片上銲墊204上方。在此實施例中,銀合金銲線200的組成為銀添加0.01~10%重量比的鈀,或此銀鈀合金組成再添加0.01至10%的金或鉑以及10至800ppm的鈹或鈰、鑭等稀土混合金屬。銀合金銲線200的線徑例如可介於10至50毫米,但也可根據需要使用具有其他適合的線徑的銀合金銲線。第一晶片202可為已完成積體電路製程且已被分離之一單一的半導體晶片(例如矽晶片),或是代表仍在未切割之包含複數個已完成積體電路製程的晶片的一半導體晶圓(例如矽晶圓)中的一個晶片。晶片上銲墊204例如為銅銲墊、鋁銲墊、金銲墊、銀銲墊、鎳銲墊、或其他常用的銲墊材料。
更詳細而言,銀合金銲線200的組成是選自下列組成之族群之一:組成1:0.01~10重量%的鈀與餘量的銀;組成2:0.01~10重量%的鈀、0.01至10重量%的鉑與餘量的銀;組成3: 0.01~10重量%的鈀、0.01至10重量%的鉑、0.01至10重量%的金與餘量的銀;組成4:0.01~10重量%的鈀、10至800ppm的微量金屬與餘量的銀,其中上述微量金屬包含10至600ppm的鈹、10至100ppm的鈰、10至100ppm的鑭中的至少一種;組成5:0.01~10重量%的鈀、0.01至10重量%的鉑、10至800ppm的微量金屬與餘量的銀,其中上述微量金屬包含10至600ppm的鈹、10至100ppm的鈰、10至100ppm的鑭中的至少一種;組成6:0.01~10重量%的鈀、0.01至10重量%的金、10至800ppm的微量金屬與餘量的銀,其中上述微量金屬包含10至600ppm的鈹、10至100ppm的鈰、10至100ppm的鑭中的至少一種;以及組成7:0.01~10重量%的鈀、0.01至10重量%的鉑、0.01至10重量%的金、10至800ppm的微量金屬與餘量的銀,其中上述微量金屬包含10至600ppm的鈹、10至100ppm的鈰、10至100ppm的鑭中的至少一種。
請參考第1、3圖,在步驟104中,燒熔銀合金銲線200的一端以形成一球狀物206。在此實施例中,係以放電結球(electric flame off;EFO)方式燒熔銀合金銲線200以產生球狀物206。然而,在其他實施例中,也可利用在打線接合製程中的其他結球方法形成此球狀物206。
請參考第1、4圖,在步驟106中,將一球狀物206接合至第一晶片202上。在此實施例中,以熱壓(hot pressing)或超音波熱壓(ultrasonic hot pressing)將球狀物206接合至第一晶片202上的晶片上銲墊204上。然而,在其他實施例中,也可利用其他方法接合球狀物206及第一晶片202。
請參考第1、5圖,在步驟108中,截斷銀合金銲線200,使得球狀物206留在第一晶片202上以形成晶片上銀合金銲球凸塊208。在此實施例中,銲球凸塊結構包括:第一晶片202;以及晶片上銀合金銲球凸塊208,設置於第一晶片202的晶片上銲墊204上。晶片上銀合金銲球凸塊208的直徑可介於20μm至100μm。
請參考第1、6圖,在步驟110中,將第一晶片202翻覆而將晶片上銲墊204上的晶片上銀合金銲球凸塊208放置在基板616的基板上銲墊618上,再將晶片上銀合金銲球凸塊208與基板上銲墊618以黏膠614接合,以完成第一種覆晶組裝。在此實施例中,晶片上銀合金銲球凸塊208的組成為銀添加0.01~10%重量比的鈀,或此銀鈀合金組成再添加0.01至10%的金或鉑以及10至800ppm的鈹或鈰、鑭等稀土混合金屬。基板616例如為已完成穿孔(Through Via)的陶瓷中介層(Interposer)、印刷電路板或不同於第一晶片202的第二晶片,例如已完成矽穿孔(Through Silicon Via,TSV)的矽中介層矽晶基板;晶片上銲墊204與基板上銲墊618例如為銅銲墊、鋁銲墊、金銲墊、銀銲墊、鎳銲墊、或其他常用的銲墊材料。黏膠614例如為等方性導電膠(Isotropic Conductive Adhesive)或異方性導電膠(Anisotropic Conductive Adhesive),在其他實施例亦可使用非導電膠(Nonconductive Adhesive)填充於多數銀合金銲球凸塊之間,利用非導電膠在冷卻過程體積收縮使銀合金銲球凸塊與晶片及基板上的銲墊緊密接觸達到電流導通效果,此非導電膠於冷卻後仍會持續支持前述緊密接觸的狀態。
更詳細而言,第6圖所示晶片上銀合金銲球凸塊208的組成可以與前述銀合金銲線200的組成相同。亦即,可選自前述銀合金銲線200的組成選項的組成1至組成7的其中之一。
請參考第1、7圖,在步驟110中,將位於第一晶片202的晶片上銲墊204上的晶片上銀合金銲球凸塊208翻轉放置在基板616的基板上銲墊618上,再將晶片上銀合金銲球凸塊208與基板616的基板上銲墊618以銲錫615接合,以完成第二種覆晶組裝。在此實施例中,晶片上銀合金銲球凸塊208的組成為銀添加0.01~10%重量比的鈀,或此銀鈀合金組成再添加0.01至10%的金或鉑以及10至800ppm的鈹或鈰、鑭等稀土混合金屬。基板616例如為已完成穿孔(Through Via)的陶瓷中介層(Interposer)、印刷電路板或不同於第一晶片202的第二晶片,此第二晶片例如已完成矽穿孔(Through Silicon Via,TSV)的矽中介層矽晶基板;晶片上銲墊204與基板上銲墊618例如為銅銲墊、鋁銲墊、金銲墊、銀銲墊、鎳銲墊、或其他常用的銲墊材料。銲錫615例如為純錫、純銦、錫-37鉛、錫-9鋅、錫-0.7銅、錫-3.5銀、錫-51銦、錫-58鉍、錫-3銀-0.5銅、錫-9鋅-3鉍等各種合金組成。在一實施例中,銲錫615為厚度10μm以上之填料,在接合晶片上銀合金銲球凸塊208與基板上銲墊時618,此銲錫填料一部份與基板上銲墊618反應,剩餘銲錫填料留存在晶片上銀合金銲球凸塊208與基板上銲墊618的界面,可為如第7圖所示的銲錫615。在此實施例中,上述銲錫填料接合的條件之一例是在大氣或氮氣環境下,不加壓力、溫度高於銲錫填料熔 點10℃,持續進行1-3分鐘。在另一實施例中,銲錫615可為厚度10μm以下之薄膜,使其在加熱過程與銲墊材料反應,所產生的結構類似第7圖所示者,惟不同之處在於本實施例在晶片上銀合金銲球凸塊208與基板616的基板上銲墊618的界面260原先銲錫薄膜將完全消耗,取而代之的是銲錫615與銀合金銲球凸塊208及基板上銲墊618銲墊材料界面反應所形成含錫成分的介金屬化合物,例如依不同銲墊種類可形成Ag3Sn、Cu6Sn5、Cu3Sn、Ni3Sn4等不同組成的介金屬化合物,這些介金屬化合物較銲錫具有更高的熔點,其優點是組裝溫度維持在一般軟銲低溫,但組裝完成的接點可以承受高於軟銲之溫度。在此實施例中,上述銲錫薄膜接合的條件之一例是在10-3-10-6Torr真空環境下,以壓力0.1-1Kg/mm2、溫度高於上述銲錫薄膜材料熔點10℃,持續進行5-30分鐘的加熱、加壓。
更詳細而言,第7圖所示晶片上銀合金銲球凸塊208的組成可以與前述銀合金銲線200的組成相同。亦即,可選自前述銀合金銲線200的組成選項的組成1至組成7的其中之一。
請參考第1、8圖,在步驟110中,將位於第一晶片202的晶片上銲墊204上的晶片上銀合金銲球凸塊208翻轉放置在基板616的晶片上銲墊618上,再將晶片上銀合金銲球凸塊208與基板616以一熱壓方式直接對第一晶片202、晶片上銀合金銲球凸塊208與基板616進行熱壓接合,以完成第三種覆晶組裝。上述熱壓接合的條件例如是在大氣環境下,以壓力0.5-3Kg/mm2、溫度300-600℃,持續進行3-60秒的加熱、加壓。 在此實施例中,晶片上銀合金銲球凸塊208的組成為銀添加0.01~10%重量比的鈀,或此銀鈀合金組成再添加0.01至10%的金或鉑以及10至800ppm的鈹或鈰、鑭等稀土混合金屬。基板616例如為已完成穿孔(Through Via)的陶瓷中介層(Interposer)、印刷電路板或不同於第一晶片202的第二晶片,此第二晶片例如已完成矽穿孔(Through Silicon Via,TSV)的矽中介層矽晶基板;晶片上銲墊204與基板上銲墊618例如為銅銲墊、鋁銲墊、金銲墊、銀銲墊、鎳銲墊、或其他常用的銲墊材料。
更詳細而言,第8圖所示晶片上銀合金銲球凸塊208的組成可以與前述銀合金銲線200的組成相同。亦即,可選自前述銀合金銲線200的組成選項的組成1至組成7的其中之一。
在一實施例中,晶片上銀合金銲球凸塊208(示於第5圖)的組成為銀添加0.01~10%重量比的鈀,或此銀鈀合金組成再添加0.01至10%的金或鉑以及10至800ppm的鈹或鈰、鑭等微量金屬。更詳細而言,第5圖所示晶片上銀合金銲球凸塊208的組成可以與前述銀合金銲線200的組成相同。亦即,可選自前述銀合金銲線200的組成選項的組成1至組成7的其中之一。發明人發現,若僅以純銀製造銲球凸塊,會有離子遷移、材質太軟、易於氧化及濕氣腐蝕等問題。然而,若在銀合金銲球凸塊中加入適量的鈀除了可提高銲球凸塊的抗濕氣腐蝕性、氧化性及強度之外,更可以抑制銀的離子遷移現象,此外,鈀的低擴散速率可以降低介金屬成長,然而,若鈀的含量過高而高於 前述範圍時,則會造成銲球凸塊材質太硬太脆,以及電阻率升高,而成為其應用上的限制。本發明之銲球凸塊組成另外可再添加金或鉑,以進一步提高銲球凸塊的抗濕氣腐蝕性、氧化性及強度;以及添加鈹或鈰、鑭等微量元素以細化晶粒,提高銲球凸塊的強度、延展性及抗高溫潛變性,然而,若金或鉑的含量太高而高於前述範圍時,則會造成介金屬含量過高,導致接點變脆,以及電阻率升高,且也會提高製造成本。另外,若添加鈹或鈰、鑭等微量元素的含量太高而高於前述範圍時,也會造成電阻率升高,接點變脆,以及抗氧化及腐蝕性變差。
應注意的是,上述銲球凸塊結構雖以銀及鈀為主要成分並包含特定比例的金、鉑及稀土元素,然而本發明之範疇並非以此為限。在其他例子中,銲球凸塊結構可更包括其他金屬、非金屬元素、或其他不可避免的雜質成分。應注意的是,其他元素的添加需視應用上的需要調整,以避免影響銲球凸塊結構的性質。
相較於其他金屬銲球凸塊進行覆晶組裝,例如:金銲球凸塊、銅銲球凸塊及銅柱(Copper pillar),本發明之銀合金銲球凸塊成本較低,且後續應用範圍更廣,穩定性更佳。以金銲球凸塊為例,其與晶片上鋁墊會形成大量介金屬反應層,導致接合界面脆裂;當其後續以銲錫合金之軟銲接合方法進行組裝時,銲球凸塊中的金會大量的熔入銲錫中而形成大量AuSn4介金屬化合物,造成接點脆裂,在電子產品使用或可靠度試驗時,也會在金銲球凸塊與鋁墊之界面形成大量脆性AuxAly介金屬化合物,並產生克肯達爾(Kirkendall)孔洞,使得 接點斷裂或電阻上升。因此,一般而言,金銲球凸塊必須以導電膠進行組裝。然而導電膠的導電性較差,而且無法具備銲錫接合的自我對位(self alignment)及可重工(reworkable)優點。
另外,若使用銅銲球凸塊進行覆晶組裝接合,則由於銅銲球凸塊與晶片上鋁墊很難形成介金屬反應層,可能導致虛銲現象,其封裝產品常無法通過殘金試驗(metal residue test)。並且由於銅非常容易氧化及腐蝕,故會造成電子產品的可靠度亦偏低。此外,由於銅的硬度大,故在將銅線打上晶片時常造成晶片破裂,因此也難以以上述方法在晶片上形成銅銲球凸塊。近年來在3D-IC(三維積體電路)或2.5D-IC封裝常使用銅柱(copper pillar)作為覆晶導電凸塊,然而由於銅柱的材質較硬,熱壓組裝接合時很難以塑性變形使銅柱與銲墊緊密接觸,而留下大量孔洞甚至無法接合,使得多數個銅柱接點面臨共平面(co-planar)不良的問題,隨著封裝接點微小化發展趨勢,此問題更加嚴重。
本發明以銀為主的銀合金銲球凸塊材質較軟,熱壓組裝接合時很容易以塑性變形使銀合金銲球與銲墊緊密接觸,不會發生銅柱接點所遭遇的共平面不良問題,因此特別適用於3D-IC或2.5D-IC封裝產品的晶片組裝;由於其材質較軟,在將球狀物打至晶片上時也不會將晶片打破。此外,銀合金銲球凸塊在接合時的介金屬含量不會太高,故不會造成傳統電鍍金凸塊或金銲球凸塊的接點脆化問題;然而,由於其仍會產生足夠的介金屬,使界面完美接合,其封裝產品均可通過殘金試驗(metal residue test),不會發生習知銅銲球凸塊因為介金屬反 應不足所導致的界面虛銲問題。此外,上述銀合金銲球凸塊可根據需要以銲錫軟銲、化學黏膠、熱壓的方式進行組裝,並不限於特定製程方法,已知傳統電鍍金凸塊或金銲球凸塊因為金在銲錫的高溶解度而無法以銲錫軟銲方式進行組裝,採用銅銲球凸塊或銅柱則會因為共平面度問題而無法以熱壓方式進行組裝。
此外,上述銀合金銲球凸塊可形成於晶片(chip)上,或可直接形成於晶圓(wafer)上,進行特殊的晶圓層級封裝(wafel level package)。直接將銲球凸塊形成於晶圓上的優點在於可先一次形成大量的銲球凸塊,而後再對晶圓進行切割,故可降低製程成本。然而,由於晶圓層級封裝必需在同一晶圓上一次製作數萬個銲球凸塊,如果採用上述銲球凸塊形成技術,其整片晶圓在數萬個銲球凸塊逐一熱壓接合過程必需持續加熱。亦即,當數萬個銲球凸塊逐一與晶片接合至最後一個銲球凸塊時,初期完成的銲球凸塊已經隨著晶圓被加熱數十分鐘。因此,若以金為銲球凸塊的主要成分時,由於金的介金屬形成速度快,這些較早形成而不斷被加熱的金銲球凸塊會因此形成大量的介金屬,使得初期形成的金銲球凸塊因界面脆裂而損壞,造成其強度變弱。因此,在形成金銲球凸塊時,一般只能直接形成於晶片上,而無法直接形成晶圓上而後再進行切割。另外,如果採用銅為銲球凸塊的主要成分,則除了界面介金屬層不足引發接合不完全的疑慮,以及銅銲球凸塊太硬造成晶圓破裂,更嚴重的是初期完成的銅銲球凸塊會因長時間隨著晶圓在空氣中加熱而發生的高溫氧化的現象。採用銅柱進行3D-IC 或2.5D-IC晶圓層級封裝則會因為銅柱太硬,在熱壓接合時,部分銅柱因為高低不一的共平面度問題而無法與銲墊接觸,會產生界面孔洞甚至不能接合的問題。
相反的,本發明之銀合金銲球凸塊的介金屬成長厚度適中且成長非常緩慢,使界面完美接合,且當銀合金銲球凸塊直接形成於晶圓上時,初期形成的銀合金銲球凸塊即使隨著整片晶圓經過一段時間的加熱,也不會如傳統金銲球凸塊產生大量的介金屬,故仍可維持銲球凸塊的強度。
綜上所述,在本發明的實施例中提供一種創新的銀合金銲球凸塊覆晶組裝方法。其中,銀合金銲球凸塊與銲墊接合可形成足夠的介金屬層,確保其接合性,不會發生銅銲球凸塊與晶片上鋁墊的虛銲問題。然而,其介金屬化合物的成長極為緩慢,故不會導致電鍍金凸塊或金銲球凸塊之接合界面脆化問題,因此有極高的可靠度。此外,銀合金銲球凸塊材質較軟,在熱壓接合時,可經由塑性變形使界面緊密接觸而達到完美接合,不會發生銅柱組裝的共平面度問題。本發明各實施例之銀合金銲球凸塊與各種電鍍銲錫合金銲球凸塊相較,亦無環境污染的顧慮,且其合金組成可以很精確控制,不會發生錫膏印刷銲錫合金凸塊的共平面度問題。再者,本發明之銀合金銲球銲球凸塊更可應用於晶圓層級封裝(Wafer Level Package)。
以下,基於更詳細的實施例及比較例來說明本發明,但本發明未受限於這些實施例及比較例。
【比較例1】
使用直徑17.4μm的純金線以電弧放電(arc discharge)將線頭燒熔,利用表面張力自然形成圓球狀,再以超音波熱壓銲線技術與矽晶片的鋁墊接合,並將接合至晶片的鋁墊上的金線截斷,以完成金銲球凸塊的製作,其製程參數如表一所示;金銲球凸塊尺寸如表二所示;接合強度則如表三所示。
【比較例2】
使用直徑17.4μm的純銅線以電弧放電(arc discharge)將線頭燒熔,利用表面張力自然形成圓球狀,再以超音波熱壓銲線技術與矽晶片的鋁墊接合,並將接合至晶片的鋁墊上的純銅線截斷,以完成銅銲球凸塊的製作。
【實施例1】銲球凸塊及其組裝製程
使用直徑17.4μm的96wt%銀-4wt%鈀-600ppm鈹-100ppm鈰-100ppm鑭組成的銀合金線以電弧放電(arc discharge)將線頭燒熔,利用表面張力自然形成圓球狀,再以超音波熱壓銲線技術與矽晶片的鋁墊接合,並將接合至晶片的鋁墊上的銀合金線截斷,以完成銀合金銲球凸塊的製作,其製程參數如表一所示;製作完成的銀合金銲球凸塊的尺寸如表二所示;接合強度則如表三所示。參照表二,雖然使用相同直徑的原始銲線,銀合金銲球凸塊尺寸略小於金銲球銲球凸塊。銀合金銲球凸塊較小的尺寸有利於高密度封裝之微小間距需求。此外,將此實施例的晶片上的銀合金銲球凸塊與比較例1的金銲球凸塊以DAGE4000接點強度測試機進行推力試驗(如表三所示),銀合金銲球凸塊的接合強度較金銲球凸塊高15%。
表一 銀合金銲球凸塊與金銲球凸塊之製程參數
【實施例2】可靠度測試
將實施例1的銀合金銲球凸塊、比較例1的金銲球凸塊及比較例2的銅銲球凸塊以96.5wt%錫-3wt%銀-0.5wt%銅的銲錫與球格陣列構裝(BGA)之雙馬來醯亞胺三嗪樹脂(bismaleimide triazine resin;BT樹脂)基板接合,再於基板植上銲錫球,完成覆晶/BGA高密度封裝產品的組裝。而後,將三種材質的銲球凸塊組裝產品進行冷熱循環試驗(Temperature Cycling Test;TCT)、壓力釜試驗(Pressure Cooking Test;PCT)及高溫貯存試驗(High Temperature Storage;HTS),以進行可 靠度試驗。
經實驗發現,比較例1的金銲球凸塊與鋁墊界面產生的介金屬層厚度高達2.1μm,故會造成接點的脆裂與產品失效。另外,比較例2的銅銲球凸塊所形成的介金屬層厚度只有0.1μm,難以確認其是否完全接合。而實施例1的銀合金銲球凸塊所產生的介金屬層厚度大約0.8μm,可以確保界面接合效果,亦不致於造成界面脆裂。
此外,將上述組裝產品進行冷熱循環試驗500次,比較例1的金銲球凸塊的介金屬層厚度劇增到3.5μm,比較例2的銅銲球凸塊組裝產品經過3000次冷熱循環試驗的介金屬層厚度則僅成長至0.3μm,而實施例1的銀合金銲球凸塊組裝產品經過3000次冷熱循環試驗的介金屬層厚度成長至1.2μm。
另外,在壓力釜試驗168小時後,比較例1的金銲球凸塊組裝產品的介金屬層厚度成長至3.2μm;比較例2的銅銲球凸塊組裝產品的介金屬層厚度僅成長至0.4μm;而實施例1的銀合金銲球凸塊組裝產品的介金屬層厚度則成長至1.4μm。
而在高溫貯存試驗500小時後,比較例1的金銲球凸塊組裝產品的介金屬層厚度大幅成長至4.5μm,此時幾乎將晶片上鋁墊完全耗盡;比較例2的銅銲球凸塊組裝產品的介金屬層厚度僅成長至1.1μm;而實施例1的銀合金銲球凸塊組裝產品的介金屬層厚度則成長至1.7μm。
綜合上述各種可靠度試驗可知比較例1的金銲球凸塊組裝產品的介金屬化合物成長太快,會造成接合界面脆 裂。相反的,比較例2的銅銲球凸塊組裝產品的介金屬層成長太慢,其界面有接合不完全的疑慮。亦即,介金屬層厚度過多或不足均會影響組裝產品的可靠度。然而,實施例1的銀合金銲球凸塊組裝產品的介金屬層厚度均介於金銲球凸塊與銅銲球凸塊之間,既不會發生金銲球凸塊的接合界面脆裂,也不會有銅銲球凸塊接合不完全的疑慮,故在可靠度試驗優於比較例1的金銲球凸塊與比較例2的銅銲球凸塊的組裝產品。
【實施例3】晶圓級封裝應用
在一6吋矽晶圓的鋁墊上分別製作12000顆實施例1的銀合金銲球凸塊、比較例1的金銲球凸塊與比較例2的銅銲球凸塊,以進行晶圓層級封裝應用之試驗。
在完成矽晶圓上所有銲球凸塊的製作後,觀察銲球凸塊的介金屬厚度。實驗結果顯示,最先形成的金銲球凸塊(比較例1)的介金屬層厚度為2.1μm;最先形成的銅銲球凸塊(比較例2)的介金屬層厚度為與0.2μm;而最先形成的銀合金銲球凸塊(實施例1)的介金屬層厚度為0.7μm。
此外,將具有銲球凸塊的矽晶圓與另一晶圓以熱壓方式進行組裝,然後將上述組裝產品進行冷熱循環試驗500次,發現晶圓上最初10個金銲球凸塊與銅銲球凸塊的介金屬層平均厚度分別為4.2μm與0.5μm,而銀合金銲球凸塊的介金屬層厚度為1.6μm。這些較早形成的金銲球凸塊顯示界面脆裂現象,而銅銲球凸塊則不僅接合不佳,而且氧化極為嚴重,甚至晶片有破裂跡象。然而,實施例1的銀合金銲球凸頭未呈現這些問題。
另外,此晶圓層級封裝採用比較例1的金銲球凸塊與實施例1的銀合金銲球凸塊的良率均接近100%,而比較例2的銅銲球凸塊的良率只有大約64%。
此外,完成的晶圓層級封裝最初10個金銲球凸塊的平均推球強度較最後10個降低約22%,銅銲球凸塊更降低約28%,而銀合金銲球凸塊的最初與最後10個銲球凸塊平均推球強度幾乎維持不變。
【實施例4】2.5D-IC封裝之應用
在積體電路晶片的鋁墊上分別製作實施例1的銀合金銲球凸塊與比較例1的直徑40μm銅柱,再利用熱壓頭使銲球凸塊與一已完成穿孔(Through Via)的氮化鋁陶瓷中介層基板上的銅銲墊接合,部分銅柱接合界面出現大量孔隙,此孔隙主要是由於銅柱共平面現象所造成。相反的,銀合金銲球凸塊接點均呈現完美的接合界面,其組裝產品使用微小負荷試驗機在位移0.1mm的條件進行三點彎曲動態疲勞試驗平均壽命達14,550次。
【實施例5】3D-IC封裝之應用
在積體電路晶片的鋁墊上分別製作實施例1的銀合金銲球凸塊與比較例1的直徑40μm銅柱,再利用熱壓頭使銲球凸塊與一已完成矽穿孔(Through Silicon Via,TSV)的矽中介層矽晶基板上的銅銲墊接合,部分銅柱接合界面出現大量孔隙,此孔隙主要是由於銅柱共平面現象所造成。相反的,銀合金銲球凸塊接點均呈現完美的接合界面,其組裝產品使用微小負荷試驗機在位移0.1mm的條件進行三點彎曲動態疲勞試驗平 均壽命達16,280次。
雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
202‧‧‧第一晶片
204‧‧‧晶片上銲墊
208‧‧‧晶片上銀合金銲球凸塊
615‧‧‧銲錫
616‧‧‧基板
618‧‧‧基板上銲墊

Claims (22)

  1. 一種銲球凸塊結構,包括:一第一晶片;以及一銀合金銲球凸塊,設置於該第一晶片上,其中該銀合金銲球凸塊的組成是選自下列組成之族群之一:(1)0.01~10重量%的鈀、10至800ppm的微量金屬與餘量的銀,其中上述微量金屬包含10至600ppm的鈹、10至100ppm的鈰、10至100ppm的鑭中的至少一種;(2)0.01~10重量%的鈀、0.01至10重量%的鉑、10至300ppm的微量金屬與餘量的銀,其中上述微量金屬包含10至600ppm的鈹、10至100ppm的鈰、10至100ppm的鑭中的至少一種;以及(3)0.01~10重量%的鈀、0.01至10重量%的鉑、0.01至10重量%的金、10至800ppm的微量金屬與餘量的銀,其中上述微量金屬包含10至600ppm的鈹、10至100ppm的鈰、10至100ppm的鑭中的至少一種。
  2. 如申請專利範圍第1項所述之銲球凸塊結構,其中該第一晶片包括一已被分離之一單一的半導體晶片或未切割的一半導體晶圓中的一個晶片。
  3. 如申請專利範圍第1項所述之銲球凸塊結構,其中該晶片更包括一銲墊,且該銀合金銲球凸塊位於該銲墊上。
  4. 一種封裝結構,包含:一第一晶片,具有一晶片上銲墊; 一晶片上銀合金銲球凸塊,設置於該第一晶片的該晶片上銲墊上;以及一基板,藉由與該第一晶片覆晶接合的形式,以其一基板上銲墊電性連接於該晶片上銀合金銲球凸塊;其中該晶片上銀合金銲球凸塊是選自下列組成之族群之一:(1)0.01~10重量%的鈀、10至800ppm的微量金屬與餘量的銀,其中上述微量金屬包含10至600ppm的鈹、10至100ppm的鈰、10至100ppm的鑭中的至少一種;(2)0.01~10重量%的鈀、0.01至10重量%的鉑、10至800ppm的微量金屬與餘量的銀,其中上述微量金屬包含10至600ppm的鈹、10至100ppm的鈰、10至100ppm的鑭中的至少一種;以及(3)0.01~10重量%的鈀、0.01至10重量%的鉑、0.01至10重量%的金、10至800ppm的微量金屬與餘量的銀,其中上述微量金屬包含10至600ppm的鈹、10至100ppm的鈰、10至100ppm的鑭中的至少一種。
  5. 如申請專利範圍第4項所述之封裝結構,其中該第一晶片包括一已被分離之一單一的半導體晶片或未切割的一半導體晶圓中的一個晶片。
  6. 如申請專利範圍第4項所述之封裝結構,其中該基板包括一矽中介層之第二晶片、一矽中介層晶圓、一陶瓷中介層基板或一印刷電路板。
  7. 如申請專利範圍第4項所述之封裝結構,其中該晶片上銀合金銲球凸塊與該基板上銲墊之間是經由一黏膠而電性接 合、經由一銲錫而電性接合或直接熱壓而電性接合。
  8. 如申請專利範圍第7項所述之封裝結構,其中該黏膠是等方性導電膠或異方性導電膠。
  9. 如申請專利範圍第7項所述之封裝結構,其中該晶片上銀合金銲球凸塊與該基板上銲墊是藉由一非導電膠的支持而直接接觸。
  10. 如申請專利範圍第7項所述之封裝結構,其中該晶片上銀合金銲球凸塊與該基板上銲墊是藉由直接加熱及加壓使銀合金銲球凸塊塑性變形並與銲墊材料進行反應形成接合界面。
  11. 如申請專利範圍第7項所述之封裝結構,其中在該晶片上銀合金銲球凸塊與該基板上銲墊的直接接觸的界面,包含具有銲錫合金或含錫的介金屬化合物。
  12. 一種封裝結構的形成方法,包含:提供一銀合金銲線;燒熔該銀合金銲線的一端以形成一球狀物;將該球狀物接合至一第一晶片的一晶片上銲墊上;截斷該銀合金銲線,使得該球狀物留在該晶片上銲墊上以形成一晶片上銀合金銲球凸塊;以及以覆晶接合,將該第一晶片經由該晶片上銀合金銲球凸塊電性接合於一基板的一基板上銲墊;其中該銀合金銲線是選自下列組成之族群之一:(1)0.01~10重量%的鈀、10至800ppm的微量金屬與餘量的銀,其中上述微量金屬包含10至600ppm的鈹、10至100ppm的鈰、10至100ppm的鑭中的至少一種; (2)0.01~10重量%的鈀、0.01至10重量%的鉑、10至800ppm的微量金屬與餘量的銀,其中上述微量金屬包含10至600ppm的鈹、10至100ppm的鈰、10至100ppm的鑭中的至少一種;以及(3)0.01~10重量%的鈀、0.01至10重量%的鉑、0.01至10重量%的金、10至800ppm的微量金屬與餘量的銀,其中上述微量金屬包含10至600ppm的鈹、10至100ppm的鈰、10至100ppm的鑭中的至少一種。
  13. 如申請專利範圍第12項所述之封裝結構的形成方法,其中該覆晶接合更包含:將該第一晶片翻覆而將該晶片上銲墊上的該晶片上銀合金銲球凸塊放置在該基板的銲墊上;以及將該晶片上銀合金銲球凸塊與該基板上銲墊以一黏膠接合。
  14. 如申請專利範圍第12項所述之封裝結構的形成方法,其中該黏膠是等方性導電膠或異方性導電膠。
  15. 如申請專利範圍第12項所述之封裝結構的形成方法,其中該黏膠是一非導電膠,且該覆晶接合更包含:以該黏膠接合後,經由冷卻使該非導電膠在冷卻過程體積收縮,使該晶片上銀合金銲球凸塊與該基板上銲墊緊密接觸而電性接合。
  16. 如申請專利範圍第12項所述之封裝結構的形成方法,其中該覆晶接合更包含: 將該第一晶片翻覆而將該晶片上銲墊上的該晶片上銀合金銲球凸塊放置在該基板的該基板的銲墊上;以及將該晶片上銀合金銲球凸塊與該基板上銲墊以一銲錫接合。
  17. 如申請專利範圍第16項所述之封裝結構的形成方法,其中該銲錫為厚度10μm以上之填料,在接合該晶片上銀合金銲球凸塊與該基板上銲墊時,該銲錫填料一部份與該基板上銲墊反應,剩餘銲錫填料留存在該晶片上銀合金銲球凸塊與該基板上銲墊的界面。
  18. 如申請專利範圍第17項所述之封裝結構的形成方法,其中該銲錫填料接合的條件是在大氣或氮氣環境下,不加壓力、溫度高於銲錫填料熔點10℃,持續進行1-3分鐘。
  19. 如申請專利範圍第16項所述之封裝結構的形成方法,其中該銲錫亦可為厚度10μm以下之薄膜,在接合該晶片上銀合金銲球凸塊與該基板上銲墊時,該銲錫完全消耗並與該基板上銲墊反應,在該晶片上銀合金銲球凸塊與該基板上銲墊的界面形成含錫的介金屬化合物。
  20. 如申請專利範圍第19項所述之封裝結構的形成方法,其中該銲錫薄膜接合的條件是在10-3-10-6Torr真空環境下,以壓力0.1-1Kg/mm2、溫度高於銲錫薄膜材料熔點10℃,持續進行5-30分鐘的加熱、加壓。
  21. 如申請專利範圍第12項所述之封裝結構的形成方法,其中該覆晶接合更包含: 將該第一晶片翻覆而將該晶片上銲墊上的該晶片上銀合金銲球凸塊放置在該基板的該基板上銲墊上;以及以一熱壓方式直接對該第一晶片、該晶片上銀合金銲球凸塊與該基板的該基板上銲墊進行熱壓接合。
  22. 如申請專利範圍第21項所述之封裝結構的形成方法,其中該熱壓接合的條件是在大氣環境下,以壓力0.5-3Kg/mm2、溫度300-600℃,持續進行3-60秒的加熱、加壓。
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Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7142909B2 (en) * 2002-04-11 2006-11-28 Second Sight Medical Products, Inc. Biocompatible bonding method and electronics package suitable for implantation
TWI538762B (zh) * 2014-01-03 2016-06-21 樂金股份有限公司 銲球凸塊與封裝結構及其形成方法
JP6380539B2 (ja) * 2014-08-22 2018-08-29 株式会社豊田自動織機 接合構造、接合材、及び接合方法
US9718677B1 (en) * 2016-01-19 2017-08-01 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US9754914B1 (en) * 2016-05-10 2017-09-05 Rosemount Aerospace Inc. Method to provide die attach stress relief using gold stud bumps
US20180019234A1 (en) * 2016-07-13 2018-01-18 Innolux Corporation Display devices and methods for forming the same
JP6680239B2 (ja) * 2017-02-20 2020-04-15 日亜化学工業株式会社 発光装置の製造方法
RU2671383C1 (ru) * 2017-12-20 2018-10-30 Акционерное общество "Научно-исследовательский институт электронной техники" Способ формирования шариковых выводов на алюминиевой металлизации контактных площадок кристалла
JP7148300B2 (ja) * 2018-07-12 2022-10-05 上村工業株式会社 導電性バンプ、及び無電解Ptめっき浴
US10347602B1 (en) * 2018-07-23 2019-07-09 Mikro Mesa Technology Co., Ltd. Micro-bonding structure
US10388627B1 (en) * 2018-07-23 2019-08-20 Mikro Mesa Technology Co., Ltd. Micro-bonding structure and method of forming the same
RU2717264C1 (ru) * 2019-02-12 2020-03-19 Акционерное общество "Научно-исследовательский институт электронной техники" Способ применения платиновой металлизации в системе перераспределения контактных площадок кристаллов интегральных микросхем и полупроводниковых приборов
DE102020130638A1 (de) * 2019-12-11 2021-06-17 Infineon Technologies Ag Lotmaterial, schichtstruktur, chipgehäuse, verfahren zum bilden einer schichtstruktur, verfahren zum bilden eines chipgehäuses, chipanordnung und verfahren zum bilden einer chipanordnung
CN113140660A (zh) * 2020-01-20 2021-07-20 光宝光电(常州)有限公司 封装结构与封装结构的制作方法
JP2023044582A (ja) * 2021-09-17 2023-03-30 株式会社東芝 半導体装置
TWI799285B (zh) * 2022-06-07 2023-04-11 友達光電股份有限公司 顯示裝置及其製造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3527356B2 (ja) * 1996-04-04 2004-05-17 新日本製鐵株式会社 半導体装置
KR100352865B1 (ko) * 1998-04-07 2002-09-16 신꼬오덴기 고교 가부시키가이샤 반도체 장치 및 그 제조방법
US20030001286A1 (en) * 2000-01-28 2003-01-02 Ryoichi Kajiwara Semiconductor package and flip chip bonding method therein
US6919646B2 (en) * 2002-03-12 2005-07-19 Nec Electronics Corporation Semiconductor device with contacting electrodes
JP3609076B2 (ja) * 2002-03-12 2005-01-12 Necエレクトロニクス株式会社 半導体装置およびその製造方法
KR101001700B1 (ko) * 2007-03-30 2010-12-15 엠케이전자 주식회사 반도체 패키지용 은합금 와이어
JP2010087052A (ja) * 2008-09-30 2010-04-15 Panasonic Corp フリップチップ実装構造体
US8389328B2 (en) * 2008-11-06 2013-03-05 Sumitomo Bakelite Co., Ltd. Method of manufacturing electronic device and electronic device
KR101641102B1 (ko) * 2009-04-01 2016-07-20 쿨리케 앤드 소파 인더스트리즈, 인코포레이티드 도전성 범프, 와이어 루프 및 그 형성 방법
JP5165810B1 (ja) * 2012-09-12 2013-03-21 田中電子工業株式会社 銀金パラジウム系合金バンプワイヤ
TWI395313B (zh) * 2012-11-07 2013-05-01 Wire technology co ltd 銲球凸塊結構及其形成方法
TWI538762B (zh) * 2014-01-03 2016-06-21 樂金股份有限公司 銲球凸塊與封裝結構及其形成方法

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