JP2010161252A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2010161252A JP2010161252A JP2009003154A JP2009003154A JP2010161252A JP 2010161252 A JP2010161252 A JP 2010161252A JP 2009003154 A JP2009003154 A JP 2009003154A JP 2009003154 A JP2009003154 A JP 2009003154A JP 2010161252 A JP2010161252 A JP 2010161252A
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- Prior art keywords
- gold
- bump electrode
- tin
- layer
- circuit board
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
Abstract
【解決手段】半導体チップ31に形成された金バンプ電極31Aの表面にスズを主成分とする層を付着させる工程と、前記金バンプ電極の表面と前記スズを主成分とする層を反応させて、前記金バンプ電極の表面に原子比で金の割合がスズの割合以上である金−スズ化合物の層31Abを、3μm〜10μmの範囲の一様な厚さで形成する工程と、前記半導体チップを回路基板21上に、表面に前記金―スズ化合物の層が形成された前記金バンプ電極が、前記回路基板上の配線パターン21Aに、スズを主成分とするはんだ層21aを介して接するように配設する工程と、前記はんだ層を溶融させ前記金バンプ電極を前記配線パターンに接合することで、前記半導体チップを前記回路基板にフリップチップ実装する工程と、を含む。
【選択図】図8
Description
21A 配線パターン
21a Snはんだ層
31 半導体チップ
31A 金バンプ電極
31B 端子面
31a パッド電極
31b ソルダレジスト層
31Aa Snを主成分とする層
31Ab AuSn化合物層
31F アンダーフィル樹脂
Claims (6)
- 配線パターンを担持した回路基板と、
金バンプ電極を有し、前記回路基板上に前記金バンプ電極を前記配線パターンに接合してフリップチップ実装された半導体チップと、を含み、
前記金バンプ電極は前記配線パターンに、スズを主成分とするはんだ層により接合されており、前記金バンプ電極には、前記はんだ層との界面に、原子比で金の割合がスズの割合以上である金−スズ化合物の層形成されていることを特徴とする半導体装置。 - 前記金−スズ化合物は、Au5SnまたはAuSnであることを特徴とする請求項1記載の半導体装置。
- 前記はんだ層はスズおよび金の他に第3の元素を含み、前記はんだ層中の前記第3の元素の割合は、重量比で前記はんだ層中に含まれるスズの割合よりも少ないが金の割合よりも多く、前記第3の元素は、銀、パラジウム、ニッケルよりなる群より選ばれることを特徴とする請求項1記載の半導体装置。
- 半導体チップに形成された金バンプ電極の表面に、スズを主成分とする層を付着させる工程と、
前記金バンプ電極の表面と前記スズを主成分とする層を反応させて、前記金バンプ電極の表面に、原子比で金の割合がスズの割合以上である金−スズ化合物の層を形成する工程と、
前記半導体チップを回路基板上に、表面に前記金―スズ化合物の層が形成された前記金バンプ電極が、前記回路基板上の配線パターンに、スズを主成分とするはんだ層を介して接するように配設する工程と、
前記はんだ層を溶融させ、前記金バンプ電極を前記配線パターンに接合することで、前記半導体チップを前記回路基板にフリップチップ実装する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記金−スズ化合物はAuSnまたはAu5Snであることを特徴とする請求項4記載の半導体装置の製造方法。
- 前記金−スズ化合物の層を形成する工程は、前記半導体チップを、前記金バンプ電極の表面に前記スズを主成分とする層が付着した状態で、300℃以上、400℃以下の温度まで急速加熱することにより実行されることを特徴とする請求項4または5記載の半導体装置の製造方法。
Priority Applications (1)
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JP2009003154A JP5401996B2 (ja) | 2009-01-09 | 2009-01-09 | 半導体装置の製造方法 |
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JP2009003154A JP5401996B2 (ja) | 2009-01-09 | 2009-01-09 | 半導体装置の製造方法 |
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JP2010161252A true JP2010161252A (ja) | 2010-07-22 |
JP5401996B2 JP5401996B2 (ja) | 2014-01-29 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8853006B2 (en) | 2012-01-30 | 2014-10-07 | Toyoda Gosei Co., Ltd. | Method of manufacturing semiconductor device and semiconductor device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0878475A (ja) * | 1994-09-07 | 1996-03-22 | Mitsubishi Materials Corp | 半導体チップの実装方法 |
-
2009
- 2009-01-09 JP JP2009003154A patent/JP5401996B2/ja not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0878475A (ja) * | 1994-09-07 | 1996-03-22 | Mitsubishi Materials Corp | 半導体チップの実装方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8853006B2 (en) | 2012-01-30 | 2014-10-07 | Toyoda Gosei Co., Ltd. | Method of manufacturing semiconductor device and semiconductor device |
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