TWI538252B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI538252B
TWI538252B TW100116209A TW100116209A TWI538252B TW I538252 B TWI538252 B TW I538252B TW 100116209 A TW100116209 A TW 100116209A TW 100116209 A TW100116209 A TW 100116209A TW I538252 B TWI538252 B TW I538252B
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passivation layer
semiconductor
light emitting
layer
wafer
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佛瑞德瑞克S 戴安那
亨利 廣興 邱
莫慶偉
塞吉L 路達斯
法蘭克L 衛
丹尼爾A 史坦格沃
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皇家飛利浦電子股份有限公司
飛利浦露明光學公司
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Description

半導體裝置及其製造方法
本發明係關於一種在一半導體發光裝置上之鈍化層。
半導體發光裝置係目前可用的最有效光源之一,該等半導體發光裝置包含發光二極體(LED)、諧振腔發光二極體(RCLED)、垂直腔雷射二極體(VCSEL)及邊射型雷射。目前在製造能夠跨可見光譜操作之高亮度發光裝置中受關注的材料系統包含III至V族半導體,尤其係鎵、鋁、銦及氮的二元、三元及四元合金,亦稱為III族氮化物材料。通常,藉由憑藉金屬有機化學氣相沈積(MOVCD)、分子束磊晶(MBE),或其他磊晶技術在藍寶石、碳化矽、III族氮化物或其他適合基板上磊晶生長具不同組合物與摻雜濃度之一半導體層堆疊而製造III族氮化物發光裝置。該堆疊常常包含形成於該基板上摻雜有(例如)矽之一或多個n型層、在一作用區域中形成於該n型層或該等n型層上之一或多發光層及形成於該作用區域上摻雜有(例如)鎂之一或多個p型層。電接觸件係形成於該n型區域與該p型區域上。
US 2006/0281203描述「techniques for mounting LEDs for packaging and for removing the growth substrate of the LEDs」。在載體與晶粒之間注射側填滿材料以在基板移除期間對磊晶結構提供支撐。半導體結構之一部分由晶粒與載體之間的互連件支撐,並且一部分由該側填滿材料支撐。當該半導體結構曝露於應力時(例如在基板移除期間),為防龜裂,互連件與側填滿材料之機械柔度及熱膨脹係數係較佳地匹配。適合的側填滿材料之實例包含可購自Henkel公司之FB4511環氧樹脂,及聚矽氧以及負載有無機材料(諸如氧化矽或氧化鋁)以達到所需之熱膨脹係數與機械柔度之其他環氧樹脂。既然該側填滿材料為磊晶層提供支撐,則側填滿材料需要填充互連件之間的所有間隙並且避免在基板移除期間形成可能促使磊晶結構龜裂之氣泡。因此,該側填滿材料的表面張力可經選擇使得該側填滿材料填充互連件之間的所有間隙。或者,可在載體與晶粒之間之間隙之與注射該側填滿材料的側相對的一側上建立一局部真空,以將該側填滿材料汲取至連接件之間的所有間隙中。
本發明的一目的係提供一種用於一半導體發光裝置之鈍化層。
在根據本發明之一些實施例的一方法中,提供一結構。該結構包含包括複數個半導體發光裝置之一晶圓,各發光裝置包括設置於一n型區域與一p型區域之間的一發光層。該結構進一步包含設置在該等半導體發光裝置之至少一者的一側上之一鈍化層及設置於兩個半導體發光裝置之間之該晶圓上的一第一材料。該方法進一步包含在該結構與一基座之間設置一第二材料。該第一材料經組態以黏附至該第二材料。該結構係附接至該基座。
在本發明之一些實施例中,一裝置包含一半導體結構,該半導體結構包括設置於一n型區域與一p型區域的一發光層。一鈍化層係設置於該半導體結構之一側壁的至少部分上。經組態以黏附至一側填滿材料的一材料係設置於該半導體結構之一經蝕刻表面上。
在本發明之一些實施例中,一結構包含包括複數個半導體發光裝置之一晶圓,各發光裝置包括設置於一n型區域與一p型區域的一發光層。一鈍化層係設置在該等半導體發光裝置之至少之一者的一側上。經組態以黏附至一側填滿材料之一材料係設置於兩個半導體發光裝置之間之該晶圓上。
在一些實施例中,該鈍化層可為該側填滿材料、一介電層或一多層堆疊。該鈍化層可經組態以防止污染物接觸該半導體發光裝置,此可改良一裝置的效能並且避免裝置故障。設置於兩個半導體發光裝置之間之該晶圓上之材料改良該側填滿材料至該晶圓之黏附性,此亦可改良該裝置的鈍化。
雖然在下文實例中,該半導體發光裝置係發射藍光或UV光之一III族氮化物LED,但可使用除LED外之半導體裝置(諸如雷射二極體)及由其他材料系統(諸如其他III至V族材料、III族磷化物、III族砷化物、II至VI族材料或基於矽的材料)製造之半導體裝置。
圖1圖解說明薄膜覆晶發光裝置之一晶圓的一部分。為了形成圖1所示之結構,首先在一生長基板上生長一半導體結構20。半導體結構20包含夾置於n型區域22與p型區域26之間之一發光區域或作用區域24。一n型區域22通常首先生長於該生長基板上並且可包含具不同組合物與摻雜濃度之多個層,包含(例如)可為n型或非有意摻雜之製備層(諸如緩衝層或成核層)及針對發光區域高效發光所需之特定光學或電性質的n型或甚至p型裝置層。一發光區域或作用區域24係生長在n型區域22上。合適發光區域之實例包含一單一厚或薄發光層,或包含由障壁層分離之多個薄或厚發光層之一多重量子井發光區域。一p型區域26係生長在發光區域24上。與n型區域22一樣,p型區域26可包含具有不同組合物、厚度及摻雜濃度之多個層,包含非有意摻雜之諸層或n型層。
於p型區域26上沈積一或多個p接觸件金屬28(舉例而言,諸如,銀),然後蝕除p型區域與作用區域之部分以曝露一n型層之一部分35,隨後於該n型層上形成一n接觸件40。p接觸件28可由沈積於p接觸件28旁邊及上方之一或多個防護層30及32密封。防護層30及32可為(例如)具有曝露p接觸件28之開口的一介電層或如圖1中所示,一或多個金屬層(諸如TiW)。一或多個介電層34(舉例而言,諸如藉由(例如)電漿增強化學氣相沈積(PECVD)形成之Si3N4係沈積於防護層30上以電隔離連接至該p型區域(包含p接觸件28與防護層30及32)與n接觸件40之導電結構。開口形成於n接觸件40電接觸n型區域22之區域35中之介電層34中,然後n接觸件40(舉例而言,諸如鋁)形成。一接合金屬42(舉例而言,諸如金)形成於n接觸件40上以促進將各裝置接合至一基座56並且電接觸該基座。
p接觸件28與n接觸件40形成於半導體結構的同一側上。在一些實施例中,n接觸件40與p接觸件28之任一者或兩者係反射性的並且裝置經安裝使得光經提取通過呈圖1所示之定向之該裝置的頂部。在一些實施例中,該等接觸件可在範圍上可受限制或可被製成透明,並且該裝置可經安裝使得光經提取通過上面形成有該等接觸件之表面。
裝置晶圓係(例如)藉由將接合層42超音波接合、熱音波接合,或熱壓縮接合至形成於基座56上之一接合層(圖1中未示)而附接至基座56。在將晶圓10附接至基座56之前、期間、之後,於半導體裝置晶圓10與基座56之間的任一區域(在該區域處半導體裝置晶圓10不是由該等接合層支撐)中設置一側填滿材料58。側填滿材料58可為(例如)沈積於晶圓10或基座56上並且經圖案化之一介電層或其他固體層,或在接合後注射於晶圓10與基座56之間、隨後固化成一固體之諸如聚矽氧、環氧樹脂或任何其他合適材料。側填滿材料58在該半導體裝置處理與操作期間(尤其在移除該生長基板期間)支撐晶圓10。例如,可藉由使一雷射照射透過該基板以熔化與該基板直接接觸之一半導體材料層(其為可在半導體結構中產生應力之一程序)而移除一藍寶石基板。在一些實施例中,藉由移除該生長基板而曝露之該半導體層被圖案化或粗糙化,此可改良從該裝置之光提取。在一些實施例中,該生長基板可仍為該裝置之部分。
如圖1中所示,在兩個裝置之間之一區域36(稱為「溝道」)中留下上述介電層34之一部分38。如圖1中所示,溝道中之介電層34之部分38係設置於半導體結構20之一經蝕刻表面(即,藉由蝕刻一台面而曝露之n型區域22之表面)上。該溝道之寬度可為(例如)在1微米與10微米之間並且常常係大約5微米。該溝道係(例如)藉由鋸切、雷射刻線、或雷射刻線及分裂而切割以將該晶圓單切成個別晶粒。例如,可在一裝置晶圓附接至一基座晶圓之後或在附接至該基座之前,將該晶圓切成小塊。介電部分38可改良側填滿材料58至晶圓10之黏附性,尤其改良在半導體材料(n型區域22)與側填滿材料58之間的界面處的黏附性。改良側填滿材料至晶圓之黏附性可藉由形成防止污染物到達裝置之一密封改良半導體裝置的可靠性,並且可減小損害或避免由對晶圓10支撐不足引起的故障。
圖2圖解說明薄膜覆晶發光裝置之一晶圓的一部分。圖2中所示之結構包含一鈍化層44。生長半導體結構20,然後如上文參考圖1所述形成並圖案化p接觸件28、防護層30及32、介電質34、n接觸件40及接合層42。於接合層42上沈積鈍化層44。鈍化層44可為任何合適材料,舉例而言,諸如由任何合適方法形成之一絕緣層或介電層、AlN、TiN、SiO2、SiNxOy、SiNx或Si3N4,該等方法包含濺鍍、電子束蒸鍍、CVD、PECVD或用適當的前驅物材料旋塗或浸漬塗佈該結構,然後使該前驅物材料固化以形成一高密度絕緣介電質。鈍化層44可為一單層或一多層結構。藉由習知微影技術圖案化鈍化層44以形成一或多個開口46,藉由(例如)如上文參考圖1所描述將接合層42附接至形成於一基座上之一接合層,該一或多個開口46允許該結構連接至一基座(圖2中未展示)。鈍化層44可留在相鄰裝置之間的溝道36中。
鈍化層44覆蓋裝置,除了在需要導電路徑以附接至該基座上之電極的區域中的裝置外。鈍化層44藉由塗佈接合層42與n接觸件40之側將裝置之側密封。在形成鈍化層44之區域中,鈍化層44藉由保護該裝置使之免受腐蝕、蝕刻、氧化及在操作或處理期間可能損害該裝置的其他程序而使該結構鈍化。例如,鈍化層44可減小或防止腐蝕物種(諸如水蒸氣)的入侵,此可改良該裝置之效能及/或減少故障比率。在一些實施例中,鈍化層44之厚度經選擇以反射由作用區域24所發射之可能入射在鈍化層44上之任何光。鈍化層44可改良一側填滿材料至晶圓之黏附性,如上文參考圖1所描述。
在圖3中,由一多層介電堆疊48取代圖2之鈍化層44。多層介電堆疊48可包含具有不同折射率之兩材料50與52的若干對交替層。合適材料實例包含(例如)藉由(例如)上述用於形成圖2之鈍化層44之技術,或任何其他合適技術形成之SiNx、Si3N4及SiO2。材料50與52經選擇以形成一堆疊48,該堆疊48反射來自作用區域24之入射在堆疊48上之任何光。開口54形成於需要電及/或實體接觸接合層42之堆疊48內。多層堆疊48可改良一側填滿材料至該晶圓之黏附性,如上文參考圖1所描述。
在一些實施例中,如圖3所示,在台面蝕刻可被移除以曝露生長基板(圖3中未展示)之後,在溝道36中或鄰近溝道36處,保留該半導體結構或之所有或一部分35。該鈍化層(圖1中之側填滿材料58、圖2中之鈍化層44及圖3中之堆疊48)可延伸到半導體結構之側(其中半導體結構20之整個厚度被移除)上,如圖3所示。延伸該鈍化層到半導體結構20之邊上可藉由反射入射在n型區域22與堆疊48之界面上之光進一步改良該結構之鈍化及從該裝置之提取。
已詳細描述本發明,熟習此項技術者應瞭解的是考慮到本揭示內容,可在不脫離本文所描述之發明性概念之精神的情況下,對本發明作出修改。因此,不希望將本發明的範疇限制於所圖解說明與所描述之特定實施例。
10...晶圓
20...半導體結構
22...n型區域
24...發光區域/作用區域
26...p型區域
28...p接觸件
30...防護層
32...防護層
34...介電層
35...n型層之部分
36...溝道
38...介電層34之部分
40...n接觸件
42...接合層
44...鈍化層
46...開口
48...介電堆疊
50...材料
52...材料
54...開口
56...基座
58...側填滿材料
圖1圖解說明覆晶發光裝置之一晶圓的一部分,一介電層設置於相鄰裝置之一溝道中(相鄰裝置未展示)。
圖2圖解說明覆晶發光裝置之一晶圓的一部分,一介電層設置於一接合金屬上及相鄰裝置之間之一溝道中(相鄰裝置未展示)。
圖3圖解說明覆晶發光裝置之一晶圓的部分,一反射介電堆疊設置於相鄰裝置之間之一溝道中(相鄰裝置未展示)。
10...晶圓
20...半導體結構
22...n型區域
24...發光區域/作用區域
26...p型區域
28...p接觸件
30...防護層
32...防護層
34...介電層
35...n型層之部分
36...溝道
38...介電層34之部分
40...n接觸件
42...接合層
56...基座
58...側填滿材料

Claims (15)

  1. 一種用於製造一半導體裝置的方法,其包括:提供一結構,該結構包括:包括複數個半導體發光裝置之一晶圓,各發光裝置包括設置於一n型區域與一p型區域之間的一發光層;及一鈍化層(passivation layer),其係設置在該等半導體發光裝置之至少之一者的一側上及在該晶圓上之兩個半導體發光裝置之間;及在該結構與一基座之間設置一側填滿材料(underfill),其中該鈍化層經組態以黏附至該側填滿材料;及將該結構附接至該基座;及於該結構與該基座之間設置該側填滿材料之後,藉由在設置該鈍化層之一區域中單切(singulating)該晶圓而分離該兩個半導體發光裝置。
  2. 如請求項1之方法,其中該鈍化層係一絕緣層、一介電層、AlN、TiN、SiO2、SiNxOy、SiNx及Si3N4之一者。
  3. 如請求項1之方法,其中該鈍化層經組態以反射由該發光層所發射之光。
  4. 如請求項1之方法,其中該鈍化層係一多層介電堆疊。
  5. 如請求項1之方法,其中該鈍化層經組態以防止污染物接觸該半導體發光裝置。
  6. 如請求項1之方法,其中單切包括下列一者:鋸切;及雷射刻線與分裂。
  7. 一種半導體裝置,其包括:一半導體結構,其包括設置於一n型區域與一p型區域之間之一發光層;一鈍化層,其係設置於該半導體結構之一側壁之至少部分上,其中該鈍化層經組態以黏附至一側填滿材料;及其中於該側壁處,該側填滿材料及該鈍化層形成防止污染物到達該半導體結構之一密封。
  8. 如請求項7之半導體裝置,其進一步包括附接至該半導體結構之一基座,其中該側填滿材料係設置於該半導體結構與該基座之間。
  9. 如請求項7之半導體裝置,其中該鈍化層係一絕緣層、一介電層、AlN、TiN、SiO2、SiNxOy、SiNx及Si3N4之一者。
  10. 如請求項7之半導體裝置,其中該鈍化層經組態以反射由該發光層所發射之光。
  11. 如請求項7之半導體裝置,其中該鈍化層係一多層介電堆疊。
  12. 如請求項7之半導體裝置,其中該鈍化層經組態以防止污染物接觸該半導體結構。
  13. 如請求項7之半導體裝置,其進一步包括一生長基板,其中該半導體結構係生長在該生長基板上。
  14. 一種半導體結構,其包括:包括複數個半導體發光裝置之一晶圓,各發光裝置包 括設置於一n型區域與一p型區域的一發光層;及一鈍化層,其係設置在該等半導體發光裝置之至少一者的一側上及在該晶圓上之兩個半導體發光裝置之間;其中該鈍化層經組態以黏附至一側填滿材料,及在一區域處切割該晶圓以單切該兩個半導體發光裝置,該側填滿材料及該鈍化層形成防止污染物到達該半導體裝置之一密封。
  15. 如請求項14之半導體結構,其中該鈍化層經組態以反射由該發光層所發射之光。
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TWI578576B (zh) 2015-12-30 2017-04-11 隆達電子股份有限公司 發光二極體晶片

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