TWI536572B - 金氧半場效電晶體與其形成方法及積體電路 - Google Patents

金氧半場效電晶體與其形成方法及積體電路 Download PDF

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TWI536572B
TWI536572B TW102134451A TW102134451A TWI536572B TW I536572 B TWI536572 B TW I536572B TW 102134451 A TW102134451 A TW 102134451A TW 102134451 A TW102134451 A TW 102134451A TW I536572 B TWI536572 B TW I536572B
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楊崇淵
王仁磐
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台灣積體電路製造股份有限公司
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers

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Description

金氧半場效電晶體與其形成方法及積體電路
本發明係關於積體電路，更特別關於金氧半場效電晶體(MOSFET)。
隨著積體電路的尺寸縮小，進階技術中用以形成積體電路的微影疊對容錯率更低。由於關鍵尺寸縮小，MOSFET製程可能會形成橋接的源極/汲極與閘極，或形成漏電流路徑。
本發明一實施例提供之金氧半場效電晶體，包括：基板；源極，位於基板中；汲極，位於基板中；閘極，位位於源極與汲極之間的基板上；內部間隔物，位於至少部份閘極上；以及外部間隔物，與閘極之側壁相鄰。
本發明一實施例提供之金氧半場效電晶體的形成方法，包括：形成源極與汲極於基板中；形成閘極於源極與汲極之間的基板上；以及形成內部間隔物與外部間隔物，內部間隔物位於至少部份閘極上，且外部間隔物與閘極之側壁相鄰。
本發明一實施例提供之積體電路，包括：金氧半場效電晶體，且金氧半場效電晶體包括：基板；源極，位於基板中；汲極，位於基板中；閘極介電層，位於源極與汲極之間的基板上；閘極，位於閘極介電層上；補償間隔物，與閘極之 側壁相鄰；內部間隔物，位於至少部份閘極上；外部間隔物，與補償間隔物相鄰；以及至少淺溝槽隔離結構，位於基板中並與源極或汲極相鄰。
Ds‧‧‧間隔物寬度
100‧‧‧MOSFET
102‧‧‧基板
104‧‧‧淺溝槽隔離結構
106‧‧‧源極/汲極區
108‧‧‧輕掺雜區
110‧‧‧閘極
112‧‧‧閘極介電層
114‧‧‧四乙氧矽烷層
116‧‧‧補償間隔物
118‧‧‧內部間隔物
120‧‧‧外部間隔物
202‧‧‧間隔物
204‧‧‧介電層
第1圖係本發明某些實施例中，MOSFET的示意圖。
第2A至2F圖係第1圖中的MOSFET之製程示意圖。
下述內容為製作與使用本發明的實施例。可以理解的是，這些實施例提供許多可實施的發明概念，以應用於多種特定方向。然而這些特定實施例僅用以說明而非侷限本發明範疇。
另一方面，下述內容的不同實施例可能採用相同標號及/或符號，但重複的標號及/或符號僅為了使說明簡單清楚，並不代表不同實施例中相同標號的單元具有相同的對應關係。此外，某一元件「位於另一元件上」、「連接至另一元件-」、或「耦合至另一元件」可以是某一元件直接位於另一元件上、直接連接至另一元件、或直接耦合至另一元件，或者兩元件間隔有其他元件。空間性的相對用語如「較下方」、「較上方」、「水平」、「垂直」、「位於...其上」、「位於...其下」、「上」、「下」、「頂部」、「底部」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。可以理解的是，空間性的相對用語可延伸至以其他方向使用之元件。
第1圖係某些實施例中，MOSFET 100的示意圖。 MOSFET 100包含基板102、淺溝槽隔離(STI)結構104、源極/汲極區106、輕掺雜區108、閘極110、閘極介電層112、四乙氧矽烷(TEOS)層114、補償間隔物116、內部間隔物118、與外部間隔物120。
基板102提供支撐，並可作為形成其上之積體電路的基座。基板102可為矽、氧化矽、氧化鋁、藍寶石、鍺、砷化鎵(GaAs)、矽鍺合金、磷化銦(InP)、絕緣層上矽、或任何其他合適材料。淺溝槽隔離結構104提供MOSFET與其相鄰元件之間的電性隔離。淺溝槽隔離結構104可為氧化矽，其形成方法可為蝕刻基板以形成溝槽，再沉積氧化矽及/或其他介電材料以填入溝槽。此外亦可採用其他隔離結構如場氧化物(FOX)。
閘極110可為多晶矽、金屬、或任何其他合適材料。閘極介電層112可為氧化矽，金屬氧化物如氧化鉿、氧化鉭、或類似物，或任何其他合適的介電材料。輕掺雜區108與閘極110相鄰，可避免短通道效應。輕掺雜區108位於閘極110與基板102表面中的源極/汲極區106之間。輕掺雜區108掺雜有n型或p型掺質，比如離子佈植的磷或硼。
四乙氧矽烷層114與補償間隔物116與閘極110之側壁相鄰。舉例來說，補償間隔物116可為氮化矽。在某些實施例中，補償間隔物116係用以定義輕掺雜區108，並可作為自我對準形成的輕掺雜區108之遮罩。源極/汲極區106掺雜有n型或p型掺質，比如離子佈植的磷或硼。
內部間隔物118與外部間隔物120可為氧化矽、氮化矽、其他介電層、或任何其他合適材料。內部間隔物118位 於至少部份的閘極110上。舉例來說，內部間隔物118覆蓋閘極110的多寡取決於元件與製程的設計。如第1圖所示，內部間隔物118部份覆蓋閘極110。在某些實施例中，內部間隔物118可完全覆蓋閘極110，但這些實施例中的部份閘極110自被覆蓋的區域向外延伸至電性連接墊，或稍後露出閘極110的至少某些部份以容許閘極的電性連接。外部間隔物120與補償間隔物116及閘極110之側壁相鄰。
當內部間隔物118附加外部間隔物120時，可增加間隔物寬度Ds，進而增加MOSFET 100之製程的微影疊對容忍度，除了在製作小尺寸元件時降低源極/汲極區106與閘極110之橋接風險外，也可避免形成漏電流路徑。
第2A至2F圖係第1圖中的MOSFET之製程示意圖。
在第2A圖中，可由習知技藝中任何合適的方法形成淺溝槽隔離結構104、閘極介電層112、閘極110、四乙氧矽烷層114、及補償間隔物116於基板102上。在一實施例中，先成長或形成作為閘極介電層112之氧化矽層於基板102上，再沉積作為閘極110之多晶矽層於氧化矽層上。接著圖案化氧化矽層與多晶矽層，以形成閘極介電層112與閘極110。在某些實施例如閘極後製的製程中，閘極110可為虛置閘極，在後續製程中可被移除並置換為金屬閘極。
舉例來說，補償間隔物116如氮化矽或氧化矽的形成方法可為化學氣相沉積法與蝕刻。在某些實施例中，輕掺雜區108之形成方法係以閘極110與補償間隔物116作為遮罩進行的離子佈植，因此輕掺雜區108自我對準補償間隔物116的邊 緣。
在某些實施例中，可形成另一間隔物202如氮化矽或氧化矽如第2B圖所示，其形成方法可為化學氣相沉積法與蝕刻。
在某些實施例中，以閘極110與間隔物202作為遮罩進行離子佈植以形成源極/汲極區106如第2C圖所示，因此源極/汲極區自我對準間隔物202的邊緣。
在某些實施例中，移除間隔物202，並以乾蝕刻或濕蝕刻蝕刻閘極110如第2D圖所示。舉例來說，蝕刻深度取決於閘極110的尺寸與製程。
在第2E圖中，沉積介電層204如氧化矽層或氮化矽層。
在第2F圖中，蝕刻介電層240以形成內部間隔物118與外部間隔物120。內部間隔物118位於至少部份的閘極110上。外部間隔物120與補償間隔物116及閘極110的側壁相鄰。舉例來說，內部間隔物118覆蓋閘極110的多寡取決於元件與製程的設計。即使第2F圖中的內部間隔物118部份覆蓋閘極110,某些實施例中的內部間隔物118可完全覆蓋閘極110。
MOSFET 100之製程藉由新增內部間隔物118至閘極110上，可增加間隔物寬度Ds(見第1圖)，進而改善微影疊對容忍度如源極/汲極區106及閘極110的接點容忍度。在縮小元件的關鍵尺寸時，上述製程可降低源極/汲極區106與閘極110之橋接風險，亦可避免形成漏電流路徑。
在某些實施例中，金氧半場效電晶體(MOSFET)包 括基板，位於基板中的源極與汲極，與位於源極與汲極之間的基板上之閘極。內部間隔物，位於至少部份閘極上。外部間隔物與閘極之側壁相鄰。
在某些實施例中，金氧半場效電晶體(MOSFET)的形成方法包括形成源極與汲極於基板中。形成閘極位於源極與汲極之間的基板上。形成內部間隔物與外部間隔物，內部間隔物位於至少部份閘極上，且外部間隔物與閘極之側壁相鄰。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
Ds‧‧‧間隔物寬度
100‧‧‧MOSFET
102‧‧‧基板
104‧‧‧淺溝槽隔離結構
106‧‧‧源極/汲極區
108‧‧‧輕掺雜區
110‧‧‧閘極
112‧‧‧閘極介電層
114‧‧‧四乙氧矽烷層
116‧‧‧補償間隔物
118‧‧‧內部間隔物
120‧‧‧外部間隔物

Claims (10)

  1. 一種金氧半場效電晶體，包括：一基板；一源極，位於該基板中；一汲極，位於該基板中；一閘極，位於該源極與該汲極之間的該基板上；一內部間隔物，位於至少部份該閘極上；以及一外部間隔物，與該閘極之側壁相鄰，其中該內部間隔物與該外部間隔物係由相同的介電層形成。
  2. 如申請專利範圍第1項所述之金氧半場效電晶體，更包括一輕掺雜區位於該基板中，且該輕掺雜區與該閘極相鄰。
  3. 如申請專利範圍第1項所述之金氧半場效電晶體，更包括一補償間隔物位於該閘極之側壁與該外部間隔物之間。
  4. 如申請專利範圍第3項所述之金氧半場效電晶體，更包括一四乙氧矽烷層位於該補償間隔物與該閘極的側壁之間。
  5. 一種金氧半場效電晶體的形成方法，包括：形成一源極與一汲極於一基板中；形成一閘極於該源極與該汲極之間的該基板上；以及同時形成一內部間隔物與一外部間隔物，該內部間隔物位於至少部份該閘極上，且該外部間隔物與該閘極之側壁相鄰。
  6. 如申請專利範圍第5項所述之金氧半場效電晶體的形成方法，更包括形成至少一輕掺雜區於該基板中，且該輕掺雜 區與該閘極相鄰。
  7. 如申請專利範圍第5項所述之金氧半場效電晶體的形成方法，更包括在形成該外部間隔物之前先形成一補償間隔物，且該補償間隔物與該閘極之側壁相鄰。
  8. 如申請專利範圍第7項所述之金氧半場效電晶體的形成方法，更包括在形成該補償間隔物之前先形成一四乙氧矽烷層，且該四乙氧矽烷層與該閘極之側壁相鄰。
  9. 如申請專利範圍第7項所述之金氧半場效電晶體的形成方法，更包括以該補償間隔物作為遮罩以形成至少一輕掺雜區於該基板中，且該輕掺雜區與該閘極相鄰。
  10. 一種積體電路，包括：一金氧半場效電晶體，且該金氧半場效電晶體包括：一基板；一源極，位於該基板中；一汲極，位於該基板中；一閘極介電層，位於該源極與該汲極之間的基板上；一閘極，位於該閘極介電層上；一補償間隔物，與該閘極之側壁相鄰；一內部間隔物，位於至少部份該閘極上；一外部間隔物，與該補償間隔物相鄰；以及至少一淺溝槽隔離結構，位於該基板中並與該源極或該汲極相鄰，其中該內部間隔物與該外部間隔物係由相同的介電層形成。
TW102134451A 2012-10-25 2013-09-25 金氧半場效電晶體與其形成方法及積體電路 TWI536572B (zh)

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