TWI222175B - Method for fabricating MOS transistor having gate side-wall spacer thereon - Google Patents

Abstract

A method for fabricating a MOS transistor having gate side-wall spacer thereon. The method includes the steps of providing a semiconductor substrate with a gate structure thereon. Thereafter, a lightly ion implantation is carried out using the gate structure as a mask to form lightly doped drain (LDD) regions in the substrate. Subsequently, a first oxide layer is conformally formed on the semiconductor substrate and gate structure using a batch-type furnace. Then, a blanket nitride layer and a second oxide layer are sequentially formed on the first oxide layer using a single wafer tool. A composite spacer is formed by anisotropically etching the second oxide, the nitride and the first oxide layers. Finally, heavy ion implantation is carried out using the gate structure and the composite spacer as a mask to form source/drain regions in the substrate.

Description

1222175

FIELD OF THE INVENTION The present invention relates to a fabrication method, and more particularly to a method for utilizing metal-oxide half-elements with a gap wall. With the critical dimension of the semiconductor integrated circuit, the prior art has been changed from 0 to 0.13m. Traditionally, a layer of nitrogen barrier with a thickness of 0.25 / zm up to 2500 A. However, depositing such a thick insulating layer for a 0. 18 / zm or 0. 13 μm element to form a spacer would be a 0. 18 / zm or 0.13 element, a composite spacer method. Reduced, the minimum line width of the component (CD; .25 / zm reduced to 0 · M, even the method of the spacer wall of the component, only the silicon nitride is deposited, and then dry etching to form silicon nitride requires a high temperature If this kind of high-temperature deposition of thick silicon nitride elements is also used to cause damage. Therefore, at present, composite spacers are generally used.

The importance of Rapid Thermal Processing (RTP) in future semiconductor processes is beyond doubt. The massive introduction of this technology originated from single wafer processing (singl e wafer

At the same time, the rise of the concept of processing tools and cluster tools. At the same time, a number of studies have shown that in the large-area, high-density wafer integrated circuit manufacturing process (over 20 0 mm), the temperature control of RTP will achieve these. The key to the process. In addition, the manufacturing steps reduced from 0 · 2 5 // m to 0.1 3 // m have been increased from 240 to 360. Therefore, cycle time becomes an improvement.

0503-9847TWf (Nl); TSMC2002-1183; jamngwo.ptd page 6 1222175 V. Description of the invention (2) The main factors of κιη. The time required for the thermal process has already accounted for the total production time. Crystal 2 / load-Here's how to reduce the time of the thermal process has become a key issue in improving the operational efficiency of modern production plants. The aforementioned RTP originates from the concept of single wafer processing (single wafer p = essing) and cluster (cluster). Traditional or large ^ ^ The processes currently used are batch processing (batch prOcessing), that is, the single-machine can usually only process the single-system, in order to achieve the requirements of efficiency and flexibility, generally Batch wafers are processed simultaneously. After processing < ^ Remove wafer and transport to next machine. For the 200 ~ 300 procedures, there must be a clean room (clean room) to ensure zero pollution during the transportation. Secondly, batch processing has a low degree of flexibility, especially under the trend of large-area (300 mm) wafers and flexible production, which will have extremely negative impact on production capacity. For large-area wafer processing, traditional batch-type hot-wall furnaces may not be as efficient as single-wafer RTp machines in terms of process efficiency and cost. From traditional batch processing to single wafer processing, single wafer processing can indeed reduce the process time, and single wafer processing is also more suitable for handling complex processes. However, when a single-day yen process (single wafer pr0cessing) is used to fabricate a metal-oxide half-element with a gate gap, the results of excessive base current and body effect occur, leading to Decrease in reliability and process yield. Figures 1A and 1B show a conventional method for manufacturing a composite partition wall. First, please refer to FIG. 1A, a semiconductor substrate 10, such as a silicon substrate, on which

1222175 V. Description of the invention (3) ---- It has a gate structure 50, including a gate oxide layer 52 and a gate conductive layer 54, such as a polycrystalline silicon layer. First, the gate structure 50 is used as a mask, and ions are implanted into the semiconductor substrate 10 using a low-energy, mass ion implantation method to form a lightly doped drain (LDD) region 12. Next, a first oxide layer 22, a nitride layer 24, and a second oxide layer 26 are sequentially and compliantly formed on the semiconductor substrate 10 to cover the semiconductor substrate 10 and the gate structure 50. And sidewalls. Next, referring to FIG. 1B, the gate structure is sequentially removed by anisotropic etching, such as reactive ion etching, in order to remove the first oxide layer 22, the nitride layer 24, and the second oxide layer 26 '. A residual gate gap-wall is formed on the side wall of 50 and a composite gap wall 20 is formed. Finally, using the gate structure 50 and the compound gap wall 20 as a mask, high-dose ions (HDD) are implanted into the semiconductor substrate 10 to form a source / drain region 14 to complete the gate gap. Fabrication of Metal Oxygen Half Element. FIG. 2 shows a process flow chart of a conventional composite partition wall. The conventional composite partition wall is processed by batch furnace tubes, and generally a batch of wafers are processed simultaneously. U.S. Patent No. 6,451,704 discloses a method for manufacturing a composite spacer ' and reduces the lateral diffusion of doped ions. In addition, U.S. Patent No. 625 51 52 also discloses a method for manufacturing a metal-oxygen half element with a composite spacer wall to increase the source / drain extension interface and reduce the effect of hot carriers. 0 Summary of the Invention

1222175 V. Description of the invention (4) In view of this, the metal-oxygen half element of the present invention and its manufacture are metal-oxygen half with a gate gap. According to the above purpose, the method for manufacturing the half-element of the present invention includes A gate structure; entering the semiconductor substrate, forming a furnace tube on the semiconductor substrate above and on the side wall; using a layer to form a second gap wall; and the first gap wall to form a structure and the The gate gap wall is used as a cover to form a source electrode; and the electrode region C. According to the above purpose, the method for manufacturing an oxygen generating half-element includes a bottom, which has a gate structure entering the semiconductor substrate. Batch furnace tubes heat-treat the semiconductors to form a side wall on the semiconductor substrate; and enter the semiconductor substrate with the gate junction. According to the above purpose, the oxygen-generating half-element includes: a half-conductor oxide layer and a gate electrode The purpose of the conductive layer is to provide a method that uses a single piece of 70 pieces to obtain electricity. Provide a step with gates. Provide the gate structure to form a lightly doped drain to form a first gap. A single wafer processing chamber with anisotropy > 1 worm engraving a gate gap wall; implanted ions enter this kind of element with a gate gap wall wafer processing chamber with stable shape. The metal oxide-semiconductor substrate of the electrode gap wall enters the ions into the curtain and implants the area; a batch of walls is used to cover the gate body in the first oxidation the second and the semiconductor gap wall in the gate junction substrate. In addition, the following steps are provided to form an integrated substrate with the spacer; a spacer wall, and the gate to form a gate gap step: providing a half-conductor structure as a mask, a lightly doped drain region using a single The wafer is covered with a gate structure electrode gap wall as a cover, and a source / inverter region (where the body substrate is provided on the semiconductor substrate); Ion: Use the upper part of the cavity to implant the gold from the wall containing a lightly doped Φ

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The drain region is located in the semiconductor substrate on both sides of the Lanquan / Hole / 3-pole μ structure; multiple; two:;, soil: standing on the side wall of the gate structure; and-the source / Drain: "Person: In the semiconductor substrate on both sides of the composite gap wall; in which a single wafer is used to process the cavity shape & to reduce the ^ 〇y effect (Gamma) and the substrate current (substrate-current, Isub). The following is a detailed description of the first embodiment of the present invention in conjunction with the drawings and preferred embodiments. Example 1 || Figures 3A and 3B show a polar wall with a pole according to a preferred embodiment of the present invention. Firstly, please refer to FIG. 3A to provide a semiconductor substrate 100 having a gate structure 150, such as a silicon substrate. The above gate structure 150 includes a gate dielectric layer. 152, such as a silicon oxide layer, and gate conductive layer 154, such as a polycrystalline silicon layer. The surface of the semiconductor substrate 100 has a shallow trench isolation region (not shown) to isolate components. Second, low-energy ion implantation Implantation of ions into semiconductor substrates to form lightly doped Impedance (LDD) region 11 2. The formation of a lightly doped ldd region 400 forms NLDD with arsenic or phosphorus ions or f PLDD with indium or boron ions. The implantation energy ranges from 10 to 10 keV and the implantation concentration is 1E12 to 1 £ 14 atoms / cm2, and the implantation depth is 2000 to 80 A. Then, a first barrier wall (eg, silicon oxide) is formed on the semiconductor substrate 100 in order to conform 122, a Second partition wall (for example, nitrided stone) 124 ·

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And a second partition wall (eg, oxidized stone) 1 2 6 to cover the top and side walls of the semiconductor substrate 100 and the gate structure 2000. The first partition wall i22 is a TE0S-Si02 deposited by a chemical vapor deposition (CVD) method using a batch of furnace tubes, and has a thickness of 100 to 200 a, for example, 15α. The batch temperature of the above batch furnaces is 600 ° C-700 ° C, and the time is 4 to 5 hours. The second spacer wall 124 is a silicon nitride deposited by a chemical vapor deposition (CVD) method using a single wafer processing chamber, and has a thickness of 200 A to 400 A, for example, 300 A. The single-wafer processing chamber has a process temperature of 700 ° C. 〇800 ° C, 2 to 3 minutes. ^ Three The spacer 126 is SiH4-Si02 deposited by a chemical vapor deposition (CVD) method using a single wafer processing chamber and has a thickness of 800 A to 1 200 A, for example, 1000 A. The temperature of the single-wafer processing chamber is 70 ° c_80 ° c, and the time is 5 ° to 6 minutes. · «Monthly reference 3B 'to etch the first spacer 丨 22, the second spacer 丨 24, and the second spacer with an anisotropic etch, such as reactive ion etch or plasma etching. 12 6 ′ to form a composite spacer wall 120, exposing the top surface and sidewalls of the gate structure 150. High-dose ions (HDD) are re-implanted into the semiconductor substrate to form a source / drain region 114. The source / drain region 114 is formed to form NMOS with arsenic or phosphorus ions or pMOS with indium or boron ions. The implantation energy is 5 to 60 keV, and the implantation concentration is 1E15 to 5E15 atoms / cm2. After the source / drain region 410 is formed, an annealing process is performed. The temperature is 600 to 800 ° C, the time is 20 to 40 seconds, and the pressure is 10.6 Torr. FIG. 4 is a flowchart showing a first embodiment of the present invention. The present invention ♦ The first embodiment of the present invention is to first use batch furnace tubes for chemical vapor deposition (CVD).

0503-9847TWf (Nl) TSMC2002-1183; jamngwo.ptd page 11 1222175

Method to form a first gap wall (such as silicon oxide) 1 2 2 and then use a single wafer processing chamber to form a second gap wall (such as nitride nitride) 1 2 4 and a third gap by a chemical vapor deposition (CVD) method Wall (such as oxidized stone) 1 2 6 so that both process efficiency and cost can be improved while avoiding excessive substrate current (Isub) and body effect (Gamma) results to improve reliability And process yield. According to a preferred embodiment of the present invention, due to the large thermal mass of the traditional furnace tube, although it can maintain a uniform temperature, its speed is slower during the transient process of temperature rise, and the growth of high-quality oxides needs to be fast. In the case of temperature rise, it is easy to cause uneven results and even warp the wafer. Single-wafer wafers have been used because of their thermal mass (small thermal circle, rapid torsional temperature rise), and low sensitivity to average temperature in the transient state. Therefore, gates with very high growth (< 100A) have been used. Oxides, even multi-layer processes such as reoxidized oxynitridfe (0N0). The difference between the two methods is that the annealing time of the batch furnace tube is much longer than that of the single wafer RTp (batch furnace tube is calculated in hours, while The single-wafer RTp is calculated in seconds. The results show that the single-wafer RTp with a smaller thermal budget has fewer dislocations or oxide stacking errors (〇xidati〇n stacking fau 11).

Embodiment 2 FIG. 5 is a flowchart showing Embodiment 2 of the present invention. The second embodiment of the present invention mainly uses a batch of furnace control processes to perform annealing heat treatment on the semiconductor substrate 100 first. Next, three semiconductors are formed on the semiconductor substrate G.

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The partition wall 1 2 0 includes a potential ^, a stack structure of the first silicon oxide 122 / silicon nitride 124 / second oxide: 126, and the upper and side walls of the gate structure are covered. The steps are sequential compliance formation _ exhaustion. An 0 p lice-resistant silicon layer 122, a silicon nitride layer 124, and a stone said to cover the semiconductor substrate 100 and the gate structure 200 ^ f ° where oxygen The slicing layer 122 is SiH4-Si02 deposited by a chemical emulsion deposition (CVD) method in a single wafer processing chamber, with a thickness of 100 to 200 A, and a column such as 150 A. The single-wafer processing chamber has a process temperature of 7000c 800 C '% · for 2 to 3 minutes. Nitrile stone layer! 24 for single wafer processing

The nitride is deposited by a chemical vapor deposition (CVD) method in the cavity and has a thickness of 200 to 400 A, for example, 300 A. The single-wafer processing chamber has a process temperature of 700 ° C. (: -80 (TC, time 2 to 3 minutes. The oxide oxide layer 126 is a SiH ^ s deposited by a chemical vapor deposition (CVD) method using a single wafer processing chamber with a thickness of 800 A to 1 20 0 A ' For example, 1 000 a. The process temperature of the single-wafer processing chamber is 700 ° C-800 ° C, and the time is 5 to 6 minutes. Next, anisotropic etching, such as reactive ion etching or The plasma etching method etches the silicon oxide layer 22, the silicon nitride layer 24, and the silicon oxide layer 126 to form a composite spacer wall 120, exposing the top surface and side walls of the gate structure 150.

A high-dose ion (HDD) is re-implanted into the semiconductor substrate to form a source / drain region 114. Forming the source / drain region 14 forms NMOS with arsenic or phosphorus ions or PMOS with indium or boron ions. The implantation energy is 5 to 60 keV, and the implantation concentration is 1E15 to 5E15 atoms / cm2. After forming the source / drain region 410, an annealing process is performed, the temperature of which is from 600 to 800 ° C, the time is from 20 to 40 seconds, and the pressure is from i0 to 6 Torr.

1222175 V. Description of the invention (9) Figure 6 shows the results of the matrix effect according to the conventional technology and the embodiment of the present invention (utility: 1 / Gamma). Among them, the batch furnace tube 〇N〇 is significant. It is known that the oxidation-Iization-oxidation (0N0) structure deposited by the chemical vapor deposition (cvD) method using the batch furnace tube is implemented 7 times according to the present invention. Furnace tube 0 + single wafer processing N0) and the second embodiment (batch furnace tube annealing + early sun round processing 0N0) can effectively reduce the matrix effect (b〇dy to Gamma). Figure 7 Shows the results of a substrate current (substrate current, Isub) according to conventional techniques and embodiments of the present invention. The batch furnace tube 0N0 does not use the conventional oxidation-nitridation-oxide (0N0) structure deposited by a chemical vapor deposition (CVD) method using a batch furnace tube. ^ The furnace tube 0 + single wafer processing N0) and the second embodiment (batch furnace annealing + single wafer processing 0N0) can effectively reduce the substrate current (Isub) results. As shown in FIG. 3B, a metal-oxide semiconductor device having a gate spacer 120 includes a semiconductor substrate 100 and a gate structure 150, which are located on the semiconductor substrate 100. A lightly doped drain (LDD) region 112 is located in the semiconductor substrate on both sides of the gate structure 150. A composite spacer wall 120 is located on the side wall of the gate structure 150; and a source / drain region 114 is located in the semiconductor substrate 100 on both sides of the composite spacer wall 120. Wherein, the composite spacer wall 120 is formed by heat treatment to reduce the matrix effect (Gamma) and substrate current (Lb). Features and effects of the case

0503-9847TWf (Nl); TSMC2002.1183; jamngwo.ptd Page 14 1222175 V. Description of the invention (ίο) The invention's interest rate of the invention and the process of reducing the production process can also be improved by using the body effect Isub. Although the present invention limits the present invention, within the scope of Shenhe, the characteristics and effects of the application are as follows: The processing of the cavity system with a single wafer effectively improves the process duration, and the single wafer processing is also more suitable for Process yields to handle complex conventional methods. According to the embodiment of the present invention, it is possible to reduce the matrix effect 'Gamma' and the substrate current (substrate current) to improve the reliability and process yield.:: The best embodiment is disclosed above, but it is not used = the artist does not leave The essence and finish of the present invention, therefore, the scope of protection of the present invention is defined by the scope of the patent in January.

1222175 The diagram briefly illustrates that FIGS. 1A and 1B show the traditional manufacturing method of the composite partition wall; FIG. 2 shows the process flow chart of the traditional composite partition wall; and FIGS. 3A and 3B show a preferred method according to the present invention. Method for manufacturing metal-oxygen half element with interlayer gap according to an embodiment; FIG. 4 is a flowchart showing a process according to the first embodiment of the present invention; FIG. 5 is a flowchart showing a process according to the second embodiment of the present invention Figure 6 shows the results of the body effect (Gamma) according to the conventional technology and the embodiment of the present invention; and Figure 7 shows the substrate current (substrate current, according to the conventional technology and the embodiment of the present invention) Isub). Explanation of symbols: conventional part 10 ~ semiconductor substrate; 14 ~ source / drain region; 22 ~ first oxide layer; 26 ~ second oxide layer; 5 2 ~ gate oxide layer; part 100 ~ semiconductor substrate in this case; 114 ~ Source / drain region; 122 ~ first oxide layer; 126 ~ second oxide layer; 15 2 ~ gate oxide layer; 12 ~ lightly doped drain (LDD) region; 2 ~ composite gap 2 4 ~ nitride layer; 5 0 ~ gate structure; 54 ~ gate conductive layer. 112 ~ lightly doped drain (1 ^ 0) region; 120 ~ composite spacer; 1 2 4 ~ nitride layer; 150 ~ gate structure; 154 ~ gate conductive layer.

Claims (1)

1222175 MM 92118680 6. Scope of patent application The following steps insert the M type of metal-oxide half-elements with gate spacers ^ The amendment includes providing a semiconductor substrate with a gate structure thereon; and using the gate structure as a cover Screen, implanted ions enter the semiconductor cavity to form a lightly doped drain region; ^ forming a first gap wall on the semiconductor substrate with a batch of furnace tubes to cover the upper and side walls of the gate structure; Forming a gap wall on the first oxide layer by using a single wafer processing chamber;% ^ anisotropically etching the second gap wall and the first gap wall to form a gate gap wall; and Using the gate structure and the gate gap wall as a mask, implanted ions enter the semiconductor substrate to form a source / drain region. ^ 2. The manufacturing method of the metal-oxygen half 70 with gate gap wall as described in item 1 of the scope of patent application, wherein the single-wafer processing chamber system is a rapid temperature heat treatment (RTA) furnace. 3. The method for manufacturing a metal-oxygen half element with a gate spacer according to item 1 of the scope of the patent application, wherein the first spacer is TEOS-Si deposited by a chemical vapor deposition (CVD) method. 〇2. 4. The method for manufacturing a metal-oxygen half element with a gate partition wall as described in item 1 of the scope of patent application, wherein the thickness of the first partition wall is from 〇〇〇 to 20 0 A 〇5. The method for manufacturing a metal-oxygen half element with a gate spacer according to item 1, wherein the second spacer is formed by chemical vapor deposition 0503-9847TWFl (Nl) .ptc 1222175— 篆 号 _ 手 Month 1st Amendment _ 6. Silicon nitride deposited by patent application (CVD) method. 1. 6 · The manufacturing method of 70 metal-oxygen halves with gate spacers as described in item 1 of the scope of patent application, wherein the thickness of the second spacer is 200 A to 400 A 〇7. The method for manufacturing a metal-oxide-semiconductor element with a gate spacer according to item 1, wherein the second spacer further includes a third spacer. ， -8 · The manufacturing method of 70 metal-oxygen halves with gate spacers as described in item 7 of the scope of the patent application, wherein the third spacer is SiH4 deposited by chemical vapor deposition (CVD) method -Si02. ≫ _ 9 · The method for manufacturing a metal-oxygen half element with a gate gap wall as described in item 7 of the scope of patent application, wherein the thickness of the third gap wall is 800 A to 1 200 A. 1-1 〇. The method for manufacturing a metal-oxygen half element with a gate spacer according to item 1 of the scope of the patent application, wherein the anisotropic etching is a dry etching method or a reactive ion etching method. 11 · A method for manufacturing metal-oxygen half element with gate gap wall, including the following steps: bottom gap Provide a semiconductor substrate with a gate structure thereon; use the gate structure as a mask to implant ions into the semiconductor substrate to form a lightly doped drain region; use a batch of furnace tubes to heat treat the semiconductor A substrate; forming a wall on the semiconductor substrate using a single wafer processing cavity to cover the upper and side walls of the gate structure; and 1222175 -------— No. 1 92118680 _ year, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, week, month, month, month, month, month, month, month, month, month To form a source / drain region. 1. 12 · The method for manufacturing a metal-oxide-semiconductor device with a gate gap wall as described in item 11 of the scope of patent application, wherein the single-wafer processing chamber system is a rapid temperature rise heat treatment (RTA) furnace. 1, 3 · The method for manufacturing a metal-oxygen half element with a gate gap wall as described in item 11 of the scope of patent application, wherein the batch of furnace tubes is heat-treated at 600-800 ° C. 4. The method for manufacturing a metal-oxide-semiconductor device with a gate spacer according to item 11 of the scope of patent application, wherein the spacer comprises a first silicon oxide / silicon nitride / second silicon oxide stacked structure. _ U • The method for manufacturing a metal-oxide-semiconductor device with a gate spacer as described in item 14 of the scope of patent application, wherein the first silicon oxide is SiHrSi02 deposited by a chemical vapor deposition (CVD) method. I. > \ 6 · The method for manufacturing a metal-oxygen half element with a gate spacer as described in item 14 of the scope of patent application, wherein the thickness of the first silicon oxide is 100A to 20 0 A 〇 ^ The method for manufacturing a metallurgical half-piece with a gate spacer according to item 14 of the scope of the patent application, wherein the second silicon oxide is SiH4-Si02 deposited by a chemical vapor deposition (CVD) method. 18. The manufacturing method of gold with gate spacers to it0 ^ 1 as described in item 4 of the patent application scope, wherein the thickness of the second silicon oxide is 80 Å 19. Gold with gate gap 〇503.9847TWFl (Nl) .ptc Page 19 1222175 A method for manufacturing an oxygen half element, wherein the silicon nitride is formed by a chemical vapor deposition (CVD) method. 1. 20 · The method for manufacturing a metal-oxygen half element with a gate spacer as described in item 14 of the scope of patent application, wherein the thickness of the nitrided layer is 2000A to 400A 〇 2 1 -A kind of metal-oxide half-element with a gate gap, including: a semiconductor substrate; a gate structure including a gate oxide layer and a gate conductive layer on the semiconductor substrate; a lightly doped region Inside the semiconductor substrate on both sides of the gate structure; a composite spacer on the side wall of the gate structure; and a source / drain region on the semiconductor substrate on both sides of the composite spacer Inside. 2 2 The metal-oxygen half element with a gate gap wall as described in item 21 of the scope of the patent application, which claims that the composite gap wall consists of a first silicon oxide / nitride stone / second silicon oxide stacked structure Made up. 2 3 · The metal-oxide-semiconductor device with a gate spacer as described in item 22 of the scope of the patent application, wherein the first oxide layer is SiH4-SiO2 deposited by a chemical vapor deposition (CVD) method. 24. The metal-oxide-semiconductor element with a gate spacer as described in item 22 of the scope of the patent application, wherein the thickness of the first oxide layer is 100A to 200A. 2 5 · The metal-oxide-semiconductor device with a gate spacer as described in item 22 of the patent application scope, wherein the second oxide layer is formed by a chemical vapor deposition (CVD) method. 0503-9847TWFl (Nl) .ptc Page 20 1222175 No. 92118ftftn patent application scope deposited SiH4-Si02. 26. If the scope of application for patent No. 22 丨 4 < Gate barrier wall ' wherein a thickness of the first lice formation layer is 800 to 1200. Si jfe:-· Claimed gold with gate spacers as described in item 22 of the patent scope 70 ^ where the nitrided layer is formed by chemical vapor deposition (CVD) method. 2 8 · The gate spacer according to item 22 of the patent application scope, wherein the thickness of the nitride layer is 200 A to 400 A. Eight Page 21 0503-9847TWFl (Nl) .ptc