TWI536472B - Method for manufacturing tin alloy bumps - Google Patents
Method for manufacturing tin alloy bumps Download PDFInfo
- Publication number
- TWI536472B TWI536472B TW101102246A TW101102246A TWI536472B TW I536472 B TWI536472 B TW I536472B TW 101102246 A TW101102246 A TW 101102246A TW 101102246 A TW101102246 A TW 101102246A TW I536472 B TWI536472 B TW I536472B
- Authority
- TW
- Taiwan
- Prior art keywords
- tin
- layer
- alloy
- silver
- bump
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- C—CHEMISTRY; METALLURGY
- C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
- C22C—ALLOYS
- C22C13/00—Alloys based on tin
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/02—Electroplating of selected surface areas
- C25D5/022—Electroplating of selected surface areas using masking means
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/10—Electroplating with more than one layer of the same or of different metals
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/48—After-treatment of electroplated surfaces
- C25D5/50—After-treatment of electroplated surfaces by heat-treatment
- C25D5/505—After-treatment of electroplated surfaces by heat-treatment of electroplated tin coatings, e.g. by melting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3473—Plating of solder
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/12—Semiconductors
- C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/0346—Plating
- H01L2224/03462—Electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/0347—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05023—Disposition the whole internal layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05655—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/1146—Plating
- H01L2224/11462—Electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/115—Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
- H01L2224/11502—Pre-existing or pre-deposited material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
- H01L2224/11849—Reflowing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
- H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13023—Disposition the whole bump connector protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
- H01L2224/13082—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
- H01L2224/13083—Three-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/04—Soldering or other types of metallurgic bonding
- H05K2203/043—Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Organic Chemistry (AREA)
- Metallurgy (AREA)
- Materials Engineering (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrochemistry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Mechanical Engineering (AREA)
- Electroplating Methods And Accessories (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Electroplating And Plating Baths Therefor (AREA)
Description
本發明係關於一種適用於將電子零件安裝於基板的倒裝晶片安裝等時的錫合金凸塊之製造方法。
目前,在將電子零件安裝於印刷基板等之情況下,大多採用有藉由使用有凸塊的倒裝晶片安裝而進行表面安裝的方法。就形成上述凸塊的方法而言,例如,藉由電解電鍍來將焊錫層,形成於形成在基板上的光阻開口部內的電極墊上,並在去除光阻之後進行回焊,以使焊錫層熔融而形成略球狀的凸塊。
近年來,由於含有鉛(Pb)的焊錫材料對於環境面而言較為不利,因此於電子零件之接合中所使用的焊錫,係邁向無鉛化,且針對凸塊的材料也對以錫為主成分的錫-銀或者是錫-銅二元系焊錫或錫-銀-銅三元系焊錫等作探討。
例如,於專利文獻1中,係記載有將錫-銀-銅三元系薄膜形成於基材上的方法,其係將基材浸漬於含有錫化合物、銀化合物以及銅化合物的電鍍浴中,並藉由電鍍而形成的方法。
此外,於專利文獻2中,係提案有在進行錫-銀合金電鍍,接著進行錫-銅合金電鍍之後,對所得之多層合金電鍍層作回焊之形成錫-銀-銅焊錫合金的方法。
〔專利文獻1〕日本特開2006-291323號公報
〔專利文獻2〕日本特開2003-342784號公報
於上述先前技術中,仍存在有以下之課題。
亦即,於在近年來因微細化而節距縮細化並成為高縱橫比圖案的光阻之開口部(洞)處形成合金電鍍的情況下,且於使用錫-銀-銅合金電鍍液的情況或者是以錫-銀與錫-銅之電鍍液所進行的二層電鍍的情況中,由於在開口部之底部銀或銅的析出會受到抑制,因而導致越底部銀或銅越少而錫的析出越多之缺陷產生。因此,在開口部的高度方向會產生組成之不均,結果產生了錫合金凸塊之組成控制為困難的問題。特別是,若多次反覆進行電解電鍍,則電鍍液中的酸性濃度會提高導致黏度上升,而使銀變得更加難以在底部析出,因此,欲在回焊後得到安定的組成係有困難。
本發明係鑑於前述之課題而完成者,其目的為提供一種於錫合金凸塊的高度方向之組成控制為容易的錫合金凸塊之製造方法。
本發明係為了解決前述課題而採用了以下之構造。亦即,本發明之錫合金凸塊之製造方法,係以錫與其他一種或二種以上的金屬之合金所形成的錫合金凸塊之製造方法,其特徵為具有:藉由電解電鍍來將錫層形成於形成在基板上之光阻開口部內的電極上之工程;藉由電解電鍍來將錫與前述其他金屬之合金層,層積於前述錫層上之工程;以及在去除前述光阻之後,將前述錫層與前述合金層進行熔融,而形成錫合金凸塊之工程。
於該錫合金凸塊之製造方法中,係藉由電解電鍍來將錫層形成於電極上,且藉由電解電鍍來將錫與前述其他金屬(前述其他一種或二種以上之金屬)之合金層,層積於該錫層上,故藉由在電鍍合金層時所預先形成的錫層,而減輕開口部的深度,因此能夠抑制高度方向之其他金屬的組成之不均。另外,於所層積的合金層中之其他金屬,係因應於將錫層與合金層進行熔融並作成錫合金凸塊時的目標組成,而將組成設定成較僅有錫與其他金屬之合金電鍍的情況更高,藉此可進行錫合金凸塊之組成控制。
此外,本發明之錫合金凸塊之製造方法,其中,前述其他金屬為銀,且該製造方法係具有:藉由電解電鍍來將作為前述合金層之錫-銀層形成於前述錫層上之工程;和在去除前述光阻之後,將前述錫層與前述錫-銀層進行熔融,而形成作為前述錫合金凸塊之錫-銀凸塊之工程。
亦即,於該錫合金凸塊之製造方法中,係藉由電解電鍍來將錫-銀層形成於錫層上,且使錫層與錫-銀層熔
融,故可形成將由銀析出所致之高度方向的銀組成之不均作了減低的錫-銀合金凸塊。
此外,本發明之錫合金凸塊之製造方法,其中,前述其他金屬為二種金屬,且該製造方法係具有:藉由電解電鍍來將錫與前述二種之其中一種的合金層及錫與前述二種之另一種的合金層之二層,層積於前述錫層上之工程;和在去除前述光阻之後,將前述錫層與所層積的二層之前述合金層進行熔融,而形成錫合金凸塊之工程。
亦即,於該錫合金凸塊之製造方法中,係藉由電解電鍍來將錫與前述二種之其中一種的合金層及錫與前述二種之另一種的合金層之二層,層積於該錫層上,故藉由在電鍍二層之合金層時所預先形成的錫層,而減輕開口部的深度,因此能夠抑制高度方向之二種金屬的組成之不均。
進而,本發明之錫合金凸塊之製造方法,其中,前述二種之其中一種金屬為銀且另一種金屬為銅,且該製造方法係具有:藉由電解電鍍來將錫-銀層與錫-銅層之二層,形成於前述錫層上之工程;和在去除前述光阻之後,將前述錫層、前述錫-銀層以及前述錫-銅層進行熔融,而形成作為前述錫合金凸塊之錫-銀-銅凸塊之工程。
亦即,於該錫合金凸塊之製造方法中,係藉由電解電鍍來將錫-銀層與錫-銅層之二層形成於錫層上,且使錫層、錫-銀層以及錫-銅層熔融,故可形成將由銀或銅之析出所致之高度方向的銀或銅的組成之不均作了減低的錫-銀-銅合金凸塊。
依據本發明,可達成下述之效果。
亦即,依據本發明之錫合金凸塊之製造方法,由於係藉由電解電鍍來將錫層形成於電極上,且藉由電解電鍍來將錫與其他金屬的合金層層積於該錫層上,故可抑制高度方向之其他金屬的組成之不均,且可控制將各層熔融而形成的凸塊之組成。
因此,依據本發明之錫合金凸塊之製造方法,可得到與高縱橫比圖案相對應之組成均一性高的錫合金凸塊,且成為能夠與節距縮細化相對應。
以下,針對本發明之錫合金凸塊之製造方法的第1實施形態,參照第1圖來進行說明。
於第1實施形態中,本發明之錫合金凸塊之製造方法,係以錫與銀等之其他一種或二種以上的金屬之合金所形成的錫合金凸塊之製造方法,如第1圖所示,其係具有:藉由電解電鍍來將錫層4a形成於形成在基板1上之光阻2的開口部2a內的電極墊3上之工程;藉由電解電鍍來將錫與前述其他金屬之合金層4b,層積於錫層4a上之工程;以及在去除光阻2之後,藉由回焊處理來將錫層4a與所層積的合金層4b進行熔融,而形成錫合金凸塊5之工程。
例如,針對前述其他金屬為銀的情況進行說明時,如第1圖(a)所示,首先,藉由電解電鍍來將錫層4a形成於被形成在基板1上之光阻2的開口部2a內之電極墊3上。該錫層4a,係被形成為直至例如開口部2a之深度的一半為止。
上述基板1,係半導體晶圓、印刷基板或者是散熱基板等,且於表面上將光阻2圖案化,並以1.0以上之高縱橫比圖案設置凸塊用的開口部2a。
此外,上述電極墊3,係將例如銅電鍍膜3a與鎳電鍍膜3b作層積而成之金屬膜。
上述開口部2a,係例如將深度設為120μm、開口直徑設為70μm,且將縱橫比設為1.7之高縱橫比的圖案。另外,凸塊節距,係亦可為100數十μm之細節距。
接著,如第1圖(b)所示,藉由電解電鍍來將身為錫-銀層之合金層4b形成於錫層4a上。該身為錫-銀層之合金層4b,係被形成為:與錫層4a具有相同的高度且將開口部2a剩餘的另一半作填埋。亦即,以填埋因錫層4a而被墊高且實質上縱橫比變小之開口部2a的方式,來形成合金層4b(錫-銀層)。
另外,於所層積的合金層4b中之前述其他金屬,係因應於將錫層4a與合金層4b進行熔融而作成錫合金凸塊時的目標組成,而將組成設定成較僅有錫與其他金屬之合金電鍍的情況更高,藉此可進行錫合金凸塊之組成控制。
亦即,於第1實施形態中,身為錫-銀層之合金層
4b,係與回焊處理後之錫層4a與已熔融的錫合金凸塊的銀組成相對應,而相較於僅以錫-銀電鍍來形成錫合金凸塊的情況,將其銀組成設定成較高。例如,在以錫合金凸塊為目標的銀組成為2.5wt%的情況下,於與錫層4a具有相同高度的錫-銀層(合金層4b)中,將銀組成設定為5wt%。
接著,去除上述光阻2,如第1圖(c)所示,藉由回焊處理來將錫層4a與合金層4b(錫-銀層)進行熔融,而形成略球狀之作為錫合金凸塊5的錫-銀凸塊。另外,就回焊處理而言,係在使用例如熱風式回焊爐,並於凸塊表面塗佈有用以去除氧化膜的助焊劑之狀態下,在氮氣環境下進行加熱。
於這樣的第1實施形態之錫合金凸塊之製造方法中,係藉由電解電鍍來將錫層4a形成於電極墊3上,且藉由電解電鍍來將錫與其他金屬之合金層4b,層積於該錫層4a上,故而,藉由在電鍍合金層4b時所預先形成的錫層4a,來減輕開口部2a的深度,而能夠抑制高度方向之前述其他金屬的組成之不均。因此,回焊處理後之錫合金凸塊5的組成控制會變得容易。
特別是,於第1實施形態中,係藉由電解電鍍來將身為錫-銀層之合金層4b形成於錫層4a上,且使錫層4a與合金層4b(錫-銀層)熔融,故可減低由銀析出所致之高度方向的銀組成之不均,且形成將銀組成作了控制的錫-銀合金凸塊。
接著,針對本發明之錫合金凸塊之製造方法的第2實施形態,係參照第2圖進行說明。另外,於以下之實施形態的說明中,對於已在上述實施形態中作了說明的相同之構成要素,係標示相同的符號,並省略其說明。
第2實施形態與第1實施形態不同之處在於:於第1實施形態中,係將錫與一種金屬(銀)之合金層4b形成於錫層4a上,並藉由回焊處理而形成錫合金凸塊,相對於此,於第2實施形態中,前述其他金屬係為二種金屬,且其係以錫與二種金屬之合金所形成之錫合金凸塊之製造方法,如第2圖所示,藉由電解電鍍來將錫與前述二種之其中一種的第1合金層24b及錫與前述二種之另一種的第2合金層24c之二層,層積於錫層4a上,並將其進行回焊處理。
例如,以針對前述二種之其中一種金屬為銀且另一種金屬為銅的情況作為第2實施形態來進行說明時,如第2圖(a)所示,首先,藉由電解電鍍來將錫層4a形成於形成在基板1上之光阻2的開口部2a內之電極墊3上。
接著,如第2圖(b)所示,藉由電解電鍍來將身為錫-銅層之第1合金層24b與身為錫-銀層之第2合金層24c之二層,層積於錫層4a上。
此等身為錫-銅層之第1合金層24b及身為錫-銀層之第2合金層24c,係被形成為:將開口部2a之剩餘的一半作填埋。
例如,上述各層的厚度,係以錫層4a:第1合金層
24b(錫-銅層):第2合金層24c(錫-銀層)=1:1:3之比率而形成。
另外,於第1合金層24b及第2合金層24c中之前述二種金屬,係因應於將錫層4a、第1合金層24b、以及第2合金層24c進行熔融並作成錫合金凸塊25時的目標之組成,而將組成設定成較僅有錫與前述二種金屬之合金電鍍的情況更高,藉此可進行錫合金凸塊之組成控制。
亦即,於第2實施形態中,第1合金層24b(錫-銅層)及第2合金層24c(錫-銀層),係對應於在回焊處理後與已熔融的錫合金凸塊之銀組成及銅組成,而相較於僅以錫-銀-銅電鍍來形成錫合金凸塊的情況,將銀組成及銅組成設定成較高。例如,在以錫合金凸塊25為目標之組成為錫-3銀-0.5銅(質量%)的情況中,將第1合金層24b(錫-銅層)之銅組成設定為2.5wt%,且將第2合金層24c(錫-銀層)之銀組成設定為5wt%。
接著,去除上述光阻2,如第2圖(c)所示,藉由回焊處理來將錫層4a、第1合金層24b以及第2合金層24c進行熔融,而形成略球狀之作為錫合金凸塊25的錫-銀-銅凸塊。
另外,於錫層4a上,雖依序層積有第1合金層24b(錫-銅層)、第2合金層24c(錫-銀層),但反過來依序層積第2合金層24c(錫-銀層)、第1合金層24b(錫-銅層)亦無妨。
於這樣的第2實施形態之錫合金凸塊之製造方法中,
係藉由電解電鍍來將錫與前述二種之其中一種的第1合金層24b及錫與前述二種之另一種的第2合金層24c之二層,層積於錫層4a上,故藉由在電鍍第1合金層24b時所預先形成的錫層4a,而減輕開口部2a的深度,並進一步藉由在電鍍第2合金層24c時所預先形成的第1合金層24b,而更加減輕開口部2a的深度,因此能夠抑制高度方向之前述二種金屬的組成之不均。
特別是,於第2實施形態中,係藉由電解電鍍來將錫-銀層之第1合金層24b與錫-銅層之第2合金層24c之二層形成於錫層4a上,且使錫層4a、第1合金層24b以及第2合金層24c熔融,故可減低由銀或銅之析出之所致之高度方向的銀或銅的組成之不均,且形成將銀組成及銅組成作了控制的錫-銀-銅合金凸塊。
接著,針對本發明之錫合金凸塊之製造方法,對藉由根據上述實施形態所製作出的實施例所評價的結果進行說明。
就基板而言,係使用直徑12英吋(30.48cm)的晶圓,且於其表面圖案形成有厚度為120μm之光阻,該光祖,係以200μm節距形成有開口直徑為80μm之高縱橫比圖案的開口部。
首先,就與第1實施形態相對應的實施例1而言,係使用錫電鍍液及錫-銀電鍍液的新液,並在以下之條件下
進行電解電鍍。
亦即,以錫電鍍為厚度60μm、錫-銀電鍍為厚度60μm來進行二層電鍍,且將錫層與合金層(錫-銀層)作層積。此時,以使回焊後之錫合金凸塊中之銀組成成為2.5wt%的方式來設定條件並進行電解電鍍。亦即,將電鍍液中之銀濃度調整成僅以錫-銀電鍍來形成錫合金凸塊之情況的2倍。
進而,在去除光阻後進行回焊處理,而形成實施例1之錫合金凸塊。此時之回焊處理,係藉由熱風式之回焊爐來實施,且為了去除凸塊表面之氧化膜而在凸塊表面塗佈助焊劑,並在氮氣環境下(氧濃度100ppm以下),在第3圖所示之回焊溫度曲線條件下作實施。
此外,比較例1,係僅以錫-銀電鍍而於與實施例1具有相同的高縱橫比圖案的開口部,形成厚度為120μm且為單層的錫-銀層,並藉由與實施例1相同的回焊處理而形成錫合金凸塊。此時,以使回焊後之錫合金凸塊中之銀組成成為2.5wt%的方式來設定條件並進行電解電鍍。
進而,實施例2及比較例2,係使用對約1000枚晶圓進行了電鍍處理之後的錫-銀電鍍液,且分別在與實施例1及比較例1相同的條件下實施電解電鍍,並藉由與上述相同的回焊處理而形成錫合金凸塊。另外,此等之液中的銀濃度,係設定成與實施例1及比較例1之條件相等的濃度。
針對上述實施例1、2及比較例1、2之錫合金凸塊,
利用XRF(螢光X射線分析)來測定銀組成的結果:平均凸塊組成為實施例1:2.5wt%、比較例1:2.5wt%、實施例2:2.4wt%、比較例2:2.0wt%。如上所述,於使用有新液的電鍍液之實施例1及比較例1中,係得到目標之銀組成,相對於此,於使用有相當於1000枚晶圓之電鍍處理後的電鍍液之情況下,在比較例2中,其銀組成會變得較目標之組成更低,相反地,在實施例1中,其目標之銀組成係被大致維持。
接著,就與第2實施形態相對應的實施例3而言,係使用錫電鍍液、錫-銅電鍍液及錫-銀電鍍液的新液,並在以下之條件下進行電解電鍍。
亦即,使用與實施例1相同的晶圓,以錫電鍍成為厚度24μm、膜中銅組成成為2.5wt%的條件,並以錫-銅電鍍成為厚度24μm、膜中銀組成成為5wt%的條件,而使錫-銀電鍍成為厚度72μm地來進行三層電鍍,再以使回焊處理後之錫合金凸塊之組成成為錫-3銀-0.5銅的方式實施電解電鍍。進而,在去除光阻後進行回焊處理,而形成實施例2之錫合金凸塊。
進而,在經過相當於約1000枚之晶圓電鍍處理後的電解之後,在相同的條件下實施上述的電鍍處理。利用XRF來測定上述之回焊處理後的錫合金凸塊中之銀組成,平均凸塊組成係不受電解所影響,而為固定。
另外,本發明之技術範圍,並不受限於上述實施形態及上述實施例,且在不脫離本發明之主旨的範圍內可加以
各種變更。
例如,雖以如上述第2實施形態般,將第1合金層24b(錫-銅層)與第2合金層24c(錫-銀層)之二層,層積於錫層上,並將此等藉由回焊處理來進行熔融,而形成錫-銀-銅三元系凸塊者較為理想,但將以錫-銀-銅層作為錫與身為二種金屬之銀及銅的合金層而層積於錫層上,並將此等藉由回焊處理來進行熔融,而形成錫-銀-銅三元系之凸塊亦無妨。
1‧‧‧基板
2‧‧‧光阻
2a‧‧‧開口部
3‧‧‧電極墊(電極)
4a‧‧‧錫層
4b‧‧‧合金層
5、25‧‧‧錫合金凸塊
24b‧‧‧第1合金層
24c‧‧‧第2合金層
〔第1圖〕係依工程順序展示:於本發明之錫合金凸塊之製造方法的第1實施形態中製造工程的概略性重要部分剖面圖。
〔第2圖〕係依工程順序展示:於本發明之錫合金凸塊之製造方法的第2實施形態中製造工程的概略性重要部分剖面圖。
〔第3圖〕係展示:於本發明之錫合金凸塊之製造方法的實施例中回焊溫度曲線的圖表。
1‧‧‧基板
2‧‧‧光阻
2a‧‧‧開口部
3‧‧‧電極墊(電極)
3a‧‧‧銅電鍍膜
3b‧‧‧鎳電鍍膜
4a‧‧‧錫層
4b‧‧‧合金層
5‧‧‧錫合金凸塊
Claims (2)
- 一種錫合金凸塊之製造方法,其係以錫與其他二種的金屬之合金所形成的錫合金凸塊之製造方法,其特徵為具有:藉由電解電鍍來將錫層形成於形成在基板上之光阻開口部內的電極上之工程;和藉由電解電鍍來將錫與前述二種的金屬中之其中一種的合金層及錫與前述二種的金屬中之另一種的合金層之二層,層積於前述錫層上之工程;以及在去除前述光阻之後,將前述錫層與所層積了的前述合金層之二層進行熔融,而形成錫合金凸塊之工程。
- 如申請專利範圍第1項所記載之錫合金凸塊之製造方法,其中,前述二種之其中一種金屬為銀且另一種金屬為銅,且該製造方法係具有:藉由電解電鍍來將錫-銀層與錫-銅層之二層,形成於前述錫層上之工程;和在去除前述光阻之後,將前述錫層、前述錫-銀層以及前述錫-銅層進行熔融,而形成作為前述錫合金凸塊之錫-銀-銅凸塊之工程。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011013661A JP5659821B2 (ja) | 2011-01-26 | 2011-01-26 | Sn合金バンプの製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201250883A TW201250883A (en) | 2012-12-16 |
TWI536472B true TWI536472B (zh) | 2016-06-01 |
Family
ID=46580555
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW101102246A TWI536472B (zh) | 2011-01-26 | 2012-01-19 | Method for manufacturing tin alloy bumps |
Country Status (7)
Country | Link |
---|---|
US (1) | US8822326B2 (zh) |
EP (1) | EP2669937B1 (zh) |
JP (1) | JP5659821B2 (zh) |
KR (1) | KR101842738B1 (zh) |
CN (1) | CN103339718B (zh) |
TW (1) | TWI536472B (zh) |
WO (1) | WO2012101975A1 (zh) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6059071B2 (ja) * | 2013-04-23 | 2017-01-11 | 東京応化工業株式会社 | 被膜形成方法 |
KR102233334B1 (ko) * | 2014-04-28 | 2021-03-29 | 삼성전자주식회사 | 주석 도금액, 주석 도금 장치 및 상기 주석 도금액을 이용한 반도체 장치 제조 방법 |
KR101778498B1 (ko) | 2014-10-10 | 2017-09-13 | 이시하라 케미칼 가부시키가이샤 | 합금 범프의 제조방법 |
CN107881534A (zh) * | 2017-11-10 | 2018-04-06 | 广州东有电子科技有限公司 | 一种具备金属电极的器件与基板的互连方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6638847B1 (en) * | 2000-04-19 | 2003-10-28 | Advanced Interconnect Technology Ltd. | Method of forming lead-free bump interconnections |
JP3682227B2 (ja) * | 2000-12-27 | 2005-08-10 | 株式会社東芝 | 電極の形成方法 |
JP3895638B2 (ja) | 2002-05-24 | 2007-03-22 | 株式会社荏原製作所 | すず−銀−銅はんだ合金の形成方法並びに当該合金を使用する鉛フリーバンプおよび半導体素子の製造方法 |
JP2005232484A (ja) * | 2004-02-17 | 2005-09-02 | Fcm Kk | 端子、それを有する部品および製品 |
EP1766673A1 (en) * | 2004-06-30 | 2007-03-28 | Unitive International Limited | Methods of forming lead free solder bumps and related structures |
JP3711141B1 (ja) | 2005-04-13 | 2005-10-26 | Fcm株式会社 | Sn−Ag−Cu三元合金薄膜を形成する方法 |
TWI250834B (en) * | 2004-11-03 | 2006-03-01 | Phoenix Prec Technology Corp | Method for fabricating electrical connections of circuit board |
TWI299896B (en) * | 2006-03-16 | 2008-08-11 | Advanced Semiconductor Eng | Method for forming metal bumps |
US8314500B2 (en) * | 2006-12-28 | 2012-11-20 | Ultratech, Inc. | Interconnections for flip-chip using lead-free solders and having improved reaction barrier layers |
JP4724192B2 (ja) * | 2008-02-28 | 2011-07-13 | 株式会社東芝 | 電子部品の製造方法 |
US20120325671A2 (en) * | 2010-12-17 | 2012-12-27 | Tel Nexx, Inc. | Electroplated lead-free bump deposition |
JP5927850B2 (ja) * | 2011-11-11 | 2016-06-01 | 富士通株式会社 | 半導体装置及びその製造方法 |
-
2011
- 2011-01-26 JP JP2011013661A patent/JP5659821B2/ja active Active
-
2012
- 2012-01-16 CN CN201280006685.XA patent/CN103339718B/zh active Active
- 2012-01-16 WO PCT/JP2012/000217 patent/WO2012101975A1/ja active Application Filing
- 2012-01-16 US US13/981,862 patent/US8822326B2/en active Active
- 2012-01-16 EP EP12739744.6A patent/EP2669937B1/en active Active
- 2012-01-16 KR KR1020137018729A patent/KR101842738B1/ko active IP Right Grant
- 2012-01-19 TW TW101102246A patent/TWI536472B/zh active
Also Published As
Publication number | Publication date |
---|---|
EP2669937B1 (en) | 2023-10-11 |
JP2012153939A (ja) | 2012-08-16 |
KR101842738B1 (ko) | 2018-03-27 |
EP2669937A1 (en) | 2013-12-04 |
TW201250883A (en) | 2012-12-16 |
KR20130142170A (ko) | 2013-12-27 |
US8822326B2 (en) | 2014-09-02 |
CN103339718B (zh) | 2016-05-25 |
EP2669937A4 (en) | 2016-07-27 |
CN103339718A (zh) | 2013-10-02 |
US20130309862A1 (en) | 2013-11-21 |
JP5659821B2 (ja) | 2015-01-28 |
WO2012101975A1 (ja) | 2012-08-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2005217388A (ja) | 半導体パッケージ基板のプリ半田構造及びその製法 | |
JP2013534367A (ja) | 基板上にはんだ堆積物および非溶融バンプを形成する方法 | |
JP5191616B1 (ja) | はんだバンプの形成方法及び実装基板の製造方法 | |
TWI536472B (zh) | Method for manufacturing tin alloy bumps | |
TWI453882B (zh) | 封裝基板及其製造方法 | |
US9662730B2 (en) | Bump electrode, board which has bump electrodes, and method for manufacturing the board | |
JP3434829B2 (ja) | 端子面のハンダ付け方法及びハンダ合金の製造方法 | |
JP2010265540A (ja) | リードフレーム及びこの製造方法、これを用いた電子部品及び電子デバイス、並びにこれに用いられるめっき材 | |
JP2010040691A (ja) | 鉛フリーバンプ形成方法 | |
KR100714774B1 (ko) | 합금 솔더 범프를 구비하는 인쇄회로기판 및 그 제작방법 | |
JP5147723B2 (ja) | 電極構造体 | |
TWI648835B (zh) | 有芯構造焊料凸塊及其製造方法 | |
KR101073485B1 (ko) | 기계적 신뢰성이 향상된 무연 솔더 범프의 제조방법 | |
JP2011096803A (ja) | 半導体装置とその製造方法 | |
TWI476844B (zh) | 導電凸塊的製造方法及具有導電凸塊的電路板結構 | |
JP2006294949A (ja) | 電極構造体及び突起電極並びにこれらの製造方法 | |
JP6156136B2 (ja) | はんだバンプの焼結芯を形成するための芯用ペースト | |
JP2017188488A (ja) | はんだバンプの製造方法、及び、分散めっき液 | |
TWI764727B (zh) | 凸塊電極基板的形成方法 | |
JP4328097B2 (ja) | スクリーン印刷用メタルマスク及びその製造方法及び印刷方法 | |
TW201304642A (zh) | 製造印刷電路板之方法 | |
JP2015201541A (ja) | バンプ電極の製造方法 | |
JP2015198193A (ja) | はんだバンプ用めっき方法及びバンプ電極の製造方法 | |
JP2009188264A (ja) | バンプ形成方法 | |
JP2011243746A (ja) | 半導体装置の製造方法 |