TWI527154B - 電接觸結構及其形成方法 - Google Patents

電接觸結構及其形成方法 Download PDF

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Publication number
TWI527154B
TWI527154B TW099126312A TW99126312A TWI527154B TW I527154 B TWI527154 B TW I527154B TW 099126312 A TW099126312 A TW 099126312A TW 99126312 A TW99126312 A TW 99126312A TW I527154 B TWI527154 B TW I527154B
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TW
Taiwan
Prior art keywords
wires
pitch
dielectric layer
layer
forming
Prior art date
Application number
TW099126312A
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English (en)
Chinese (zh)
Other versions
TW201123351A (en
Inventor
薩瑞亞 班薩朗提
丹尼爾Ｃ 艾戴斯坦
威廉Ｄ 海斯伯
金浩哲
史帝文 寇斯特
保羅Ｍ 所羅門
Original Assignee
萬國商業機器公司
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Publication date
Application filed by 萬國商業機器公司 filed Critical 萬國商業機器公司
Publication of TW201123351A publication Critical patent/TW201123351A/zh
Application granted granted Critical
Publication of TWI527154B publication Critical patent/TWI527154B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/18, H10D48/04 and H10D48/07, with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW099126312A 2009-08-13 2010-08-06 電接觸結構及其形成方法 TWI527154B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/540,759 US8247904B2 (en) 2009-08-13 2009-08-13 Interconnection between sublithographic-pitched structures and lithographic-pitched structures

Publications (2)

Publication Number Publication Date
TW201123351A TW201123351A (en) 2011-07-01
TWI527154B true TWI527154B (zh) 2016-03-21

Family

ID=43586394

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099126312A TWI527154B (zh) 2009-08-13 2010-08-06 電接觸結構及其形成方法

Country Status (7)

Country Link
US (1) US8247904B2 (enExample)
JP (1) JP5559329B2 (enExample)
CN (1) CN102473649B (enExample)
DE (1) DE112010003269B4 (enExample)
GB (1) GB2485493B (enExample)
TW (1) TWI527154B (enExample)
WO (1) WO2011019552A1 (enExample)

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US7405147B2 (en) * 2004-01-30 2008-07-29 International Business Machines Corporation Device and methodology for reducing effective dielectric constant in semiconductor devices
US9105590B2 (en) * 2011-08-10 2015-08-11 United Microelectronics Corp. Semiconductor structure having material layers which are level with each other and manufacturing method thereof
US20130320451A1 (en) 2012-06-01 2013-12-05 Taiwan Semiconductor Manufacturing Company, Ltd., ("Tsmc") Semiconductor device having non-orthogonal element
US9581899B2 (en) * 2012-11-27 2017-02-28 International Business Machines Corporation 2-dimensional patterning employing tone inverted graphoepitaxy
US9136168B2 (en) * 2013-06-28 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive line patterning
KR102395478B1 (ko) * 2014-06-13 2022-05-09 인텔 코포레이션 Ｅ 빔을 이용한 층 상의 단방향 금속
US9306164B1 (en) 2015-01-30 2016-04-05 International Business Machines Corporation Electrode pair fabrication using directed self assembly of diblock copolymers
KR102705024B1 (ko) 2016-12-14 2024-09-09 삼성전자주식회사 반도체 장치
US10361158B2 (en) 2017-08-29 2019-07-23 Micron Technology, Inc. Integrated assemblies having structures along a first pitch coupled with structures along a second pitch different from the first pitch

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US5886410A (en) * 1996-06-26 1999-03-23 Intel Corporation Interconnect structure with hard mask and low dielectric constant materials
US6262487B1 (en) 1998-06-23 2001-07-17 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method
US6194667B1 (en) 1998-08-19 2001-02-27 International Business Machines Corporation Receptor pad structure for chip carriers
US6795367B1 (en) * 2000-05-16 2004-09-21 Micron Technology, Inc. Layout technique for address signal lines in decoders including stitched blocks
JP2001352053A (ja) * 2000-06-08 2001-12-21 Nikon Corp 固体撮像装置
US6531357B2 (en) * 2000-08-17 2003-03-11 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device
JP3964608B2 (ja) * 2000-08-17 2007-08-22 株式会社東芝 半導体装置
JP2003330385A (ja) * 2002-05-17 2003-11-19 Dainippon Printing Co Ltd 電極パターンおよびその検査方法
JP2004048032A (ja) * 2002-07-12 2004-02-12 Sharp Corp 配線構造、表示装置および能動素子基板
DE10259634B4 (de) 2002-12-18 2008-02-21 Qimonda Ag Verfahren zur Herstellung von Kontakten auf einem Wafer
JP4498088B2 (ja) * 2004-10-07 2010-07-07 株式会社東芝 半導体記憶装置およびその製造方法
JP2006173186A (ja) * 2004-12-13 2006-06-29 Toshiba Corp 半導体装置、パターンレイアウト作成方法および露光マスク
JP4936659B2 (ja) * 2004-12-27 2012-05-23 株式会社東芝 半導体装置の製造方法
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US20080085600A1 (en) * 2006-10-10 2008-04-10 Toshiharu Furukawa Method of forming lithographic and sub-lithographic dimensioned structures
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Also Published As

Publication number Publication date
CN102473649B (zh) 2015-03-18
WO2011019552A1 (en) 2011-02-17
GB201200163D0 (en) 2012-02-15
TW201123351A (en) 2011-07-01
DE112010003269B4 (de) 2014-05-15
JP2013502072A (ja) 2013-01-17
GB2485493B (en) 2014-01-15
US8247904B2 (en) 2012-08-21
CN102473649A (zh) 2012-05-23
DE112010003269T5 (de) 2013-04-25
GB2485493A (en) 2012-05-16
US20110037175A1 (en) 2011-02-17
JP5559329B2 (ja) 2014-07-23

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