TWI520292B - 封裝體層疊結構 - Google Patents

封裝體層疊結構 Download PDF

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TWI520292B
TWI520292B TW102126601A TW102126601A TWI520292B TW I520292 B TWI520292 B TW I520292B TW 102126601 A TW102126601 A TW 102126601A TW 102126601 A TW102126601 A TW 102126601A TW I520292 B TWI520292 B TW I520292B
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solderless
contact pad
package
bump
contact pads
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TW102126601A
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TW201407736A (zh
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蔡再宗
林俊成
艾蒂 洪
蔡易達
鄭明達
劉重希
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台灣積體電路製造股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0367—Metallic bump or raised conductor not used as solder bump
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H05K3/4015—Surface contacts, e.g. bumps using auxiliary conductive elements, e.g. pieces of metal foil, metallic spheres

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

封裝體層疊結構
本發明係有關於半導體裝置，且特別是有關於一種半導體裝置之封裝體層疊結構。
為了因應電子產品縮小化的需求，積體電路產業之製造商及其他業者持續地尋找方法來微縮應用於電子產品之積體電路之尺寸。在此方向下，係已發展出立體(3D)型態之積體電路封裝技術並使用。
3D積體電路封裝技術之其中一種技術係為封裝體層疊(Package-on-Package，以下簡稱PoP)。如其名稱所指，PoP係為一種創新的半導體封裝，其包含將一封裝體至堆疊另一封裝體之上。PoP裝置可垂直地結合彼此分開的記憶體封裝體及邏輯封裝體。在PoP堆疊設計中，最頂端的封裝體可使用球柵陣列結構中的銲球與最底端的封裝體作內連接。但不幸的是，球柵陣列結構中的銲球具有間距及尺寸的限制。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
本揭露係提供一種封裝體層疊結構，包括：一基 材，具有一接觸墊陣列沿此基材之周圍排列；一邏輯晶片，裝設於基材之此接觸墊陣列內部；以及多個無焊料凸塊結構，裝設於部分的可供裝設的接觸墊上。
本揭露亦提供一種封裝體層疊結構，包含：一印刷電路板，具有由多個接觸墊組成之陣列，該些接觸墊係以多個同心環之方式沿一基材之周圍排列；一邏輯晶片，以覆晶方式裝設於該基材上及該接觸墊陣列內部；以及多個無焊料凸塊結構，裝設於部分的該些接觸墊上。
2‧‧‧剖面線
4‧‧‧剖面線
10‧‧‧封裝體層疊裝置
12‧‧‧基材
14‧‧‧銲球
16‧‧‧邏輯晶片
18‧‧‧銲球直徑
20‧‧‧間距
22‧‧‧封裝體層疊裝置
24‧‧‧基材
26‧‧‧無銲料凸塊結構
28‧‧‧邏輯晶片
30‧‧‧間距
32‧‧‧無銲料凸塊結構列
34‧‧‧柱形凸塊
36‧‧‧銅凸塊
38‧‧‧銅凸塊直徑
40‧‧‧標記
42‧‧‧暴露的接觸墊
44‧‧‧圖案
46‧‧‧圖案
48‧‧‧圖案
50‧‧‧接觸墊
52‧‧‧基材周圍
54‧‧‧角落
56‧‧‧內環
58‧‧‧外環
第1圖顯示具有沿邏輯晶片圍繞之球柵陣列之封裝體層疊裝置之平面圖。
第2圖顯示沿第1圖之線段2-2作剖面之封裝體層疊裝置之剖面圖。
第3圖顯示具有沿邏輯晶片圍繞之無銲料凸塊結構之封裝體層疊裝置。
第4圖顯示沿第3圖之線段4-4作剖面之封裝體層疊裝置之剖面圖。
第5a圖顯示無銲料凸塊結構為柱狀凸塊形式之實施例。
第5b圖顯示無銲料凸塊結構為銅球形式之實施例。
第6圖顯示一標記，用以辨認暴露的接觸墊及第5a及5b圖所示之無銲料凸塊結構。
第7至9圖顯示暴露的接觸墊與無銲料凸塊結構之示範例圖案。
以下將詳細討論本發明各種實施例之製造及使用方法。然而值得注意的是，本發明所提供之許多可行的發明概念可實施在各種特定範圍中。這些特定實施例僅用於舉例說明本發明之製造及使用方法，但非用於限定本發明之範圍。
本揭露將以特定內容，針對封裝體層疊(PoP)半導體裝置之較佳實施例作解釋。然需注意的是，本揭露之概念亦可應用至其他半導體結構或電路。
參見第1圖，其顯示為一封裝體層疊(PoP)裝置10。此PoP裝置10通常包含基材12(例如印刷電路板(PCB))，其可支撐沿邏輯晶片16周圍排列之球柵陣列(BGA)銲球14。如第2圖所示，每一銲球14之直徑18為約150μm至250μm。兩相鄰銲球14之間的間距20為約300μm至400μm。雖然上述尺寸可適用於現有的PoP裝置，但如欲應用至技術更先進的PoP裝置，所需的是大幅縮小的銲球直徑及/或間距。
參見第3圖，其顯示為一封裝體層疊(PoP)裝置22。此PoP裝置22通常包含基材24(例如印刷電路板(PCB))，其可支撐沿邏輯晶片28周圍排列之無銲料凸塊結構(亦即接觸裝置)26。已發現的是，使用如第3圖所示的無銲料凸塊結構24取代第2圖之球柵陣列銲球14，可容許縮減封裝體的尺寸。因此，如將第2圖之球柵陣列銲球14替換為無銲料凸塊結構將可使封裝體之整體更為縮小。
在一實施例中，第3圖所示之邏輯晶片28可為一或多種的標準邏輯積體電路，例如中央處理器(CPU)、微控制器 (MCU)、應用處理器(application processor)、系統核心邏輯晶片組(System Core Logic Chipsets)、圖像控制晶片組(Graphics & Imaging Controllers)、儲存晶片控制組(Mass Storage Controllers)及輸入/輸出控制組(I/O Controllers)。在一實施例中，邏輯晶片28可為一或多種的特定應用積體電路(ASICs)，例如可程式化元件設計(Programmable Device based Design，PDD)、閘門陣列設計(Gate Array based Design，GAD)、標準單元設計(Cell-Based IC)及全客戶設計(Full Customer Design，FCD)。
如第4圖所示，在一實施例中，相鄰的無銲料凸塊結構26之間的間距30係小於球柵陣列銲球間的間距20(間距20為約300μm)。此外，在一實施例中，第4圖之相鄰無銲料凸塊結構26之間的間距30係小於約100μm。需汪意的是，雖然第4圖僅顯示4列的無銲料凸塊結構26，但PoP裝置10亦可包含更多或更少列的無銲料凸塊結構。
參見第5a圖，其顯示無銲料凸塊結構26為柱形凸塊(stud bump)34形式之實施例。這些柱形凸塊34可透過例如打線接合製程形成。如圖所示，柱形凸塊34之高度H係小於其寬度W。柱形凸塊34之高度及寬度尺寸係取決於打線接合製程中關於線的選擇。無論如何，通常而言，柱形凸塊34在至少一或多個方向上的尺寸係小於第2圖之球柵陣列銲球14。柱形凸塊34可由各種合適的無銲料金屬材料形成，例如但不限於：金、銀、銅、鋁或前述之合金。
參見第5b圖，其顯示無銲料凸塊結構26為銅凸塊 36形式之實施例。通常而言，銅凸塊36之直徑38係小於第2圖所示之球柵陣列銲球14之直徑。在一實施例中，凸塊結構26亦可為金球、銀球或鋁球，其類似於第5b圖所示之銅球。在其他實施例中，凸塊結構26亦可由合適的無銲料金屬合金形成。
參見第6圖，其係顯示用以識別第5a-5b圖之暴露的接觸墊42及無銲料凸塊結構26的標記(legend)40。以第6圖之標記40為參考，第7-9圖係顯示暴露的接觸墊42與無銲料凸塊結構26相對的示範圖案44、46、48。儘管第7-9圖僅顯示為特定圖案，但其亦可為其他圖案。
如以下之詳述，無銲料凸塊結構26係裝設於基材24上之部分的(即少於全部的)可供安裝的接觸墊50上。亦即，某些接觸墊50係由無銲料凸塊結構26覆蓋或裝設於其上。其他未支撐無銲料凸塊結構26之接觸墊50係稱為暴露的接觸墊42(如第6圖之標記40所指)。在一實施例中，銲料膜之薄層係設置於無銲料凸塊結構26之下及暴露的接觸墊42之上。
參見第7圖，基材24具有一接觸墊50陣列，其係通常沿基材之周圍52圍繞排列。此外，邏輯晶片28係裝設於基材24之接觸墊50陣列的內部。如圖所示，某些接觸墊50為暴露的接觸墊42，而其他的接觸墊50則各自具有一個無銲料結構26裝設於其上。參見第7圖，在一實施例中，無銲料凸塊結構26係僅裝設於位在基材24之角落54之接觸墊50上。易言之，無銲料凸塊結構26係排設於PoP裝置22之角落54。
參見第8圖，在一實施例中，接觸墊陣列50包含沿同心圍繞的接觸墊50內環56及接觸墊50外環58。在一實施例 中，無銲料凸塊結構26係裝設於外環58之每一接觸墊50上，且裝設於內環56之僅位在角落54之接觸墊50上。參見第9圖，在一實施例中，外環58中裝設有無銲料凸塊結構26於其上之接觸墊50係與內環56中裝設有無銲料凸塊結構26於其上之接觸墊50相互交錯設置。此外，內環56中裝設有無銲料凸塊結構26於其上之接觸墊50相對於外環58中裝設有無銲料凸塊結構26於其上之接觸墊50係為偏置(offset)。
在一實施例中，凸塊結構26可以對稱圖案、非對稱圖案或前述之組合的方式排列。也就是說，凸塊結構26可以任何組態形式裝設於接觸墊50上。
在第7-9圖之每一圖中，接觸墊50包含沿同心圍繞的方形接觸墊內環56及方形接觸墊外環58。儘管如此，其亦可以其他型態之配置。此外，在其他實施例中，亦可具有更多或更少的接觸墊50環。
雖然本發明已以數條較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
16‧‧‧邏輯晶片
24‧‧‧基材
26‧‧‧無銲料凸塊結構
30‧‧‧間距
32‧‧‧無銲料凸塊結構列

Claims (10)

  1. 一種封裝體層疊結構，包括：一基材，具有一接觸墊陣列沿該基材之周圍排列；一邏輯晶片，裝設於基材之該接觸墊陣列內部；以及多個無焊料凸塊結構，裝設於部分的可供裝設的接觸墊。
  2. 如申請專利範圍第1項所述之封裝體層疊結構，其中該些無焊料凸塊結構包含藉由柱形凸塊及銅球之其中一者。
  3. 如申請專利範圍第1項所述之封裝體層疊結構，其中相鄰無焊料凸塊結構之間的間距小於或等於100μm。
  4. 如申請專利範圍第1項所述之封裝體層疊結構，其中該些無焊料凸塊結構僅裝設於該基材之角落。
  5. 如申請專利範圍第1項所述之封裝體層疊結構，其中該接觸墊陣列包含沿同心圍繞之一接觸墊內環及一接觸墊外環，該些無焊料凸塊結構裝設於該接觸墊外環之每一接觸墊上，且僅裝設於該接觸墊內環之用以形成角落之接觸墊上。
  6. 如申請專利範圍第1項所述之封裝體層疊結構，其中該接觸墊陣列包含沿同心圍繞的一接觸墊內環及一接觸墊外環，該內環中具有無焊料凸塊結構裝設於其上之接觸墊係與該外環中具有無焊料凸塊結構裝設於其上之接觸墊相互交錯。
  7. 如申請專利範圍第6項所述之封裝體層疊結構，其中該內環中具有無焊料凸塊結構裝設於其上之接觸墊相對於該外環中具有無焊料凸塊結構裝設於其上之接觸墊係為偏置。
  8. 如申請專利範圍第1項所述之封裝體層疊結構，其中該些無 焊料凸塊結構係以非對稱圖案裝設於部分的該些接觸墊上。
  9. 一種封裝體層疊結構，包含：一印刷電路板，具有由多個接觸墊組成之陣列，該些接觸墊係以多個同心環之方式沿一基材之周圍排列；一邏輯晶片，以覆晶方式裝設於該基材上及該接觸墊陣列內部；以及多個無焊料凸塊結構，裝設於部分的該些接觸墊上。
  10. 如申請專利範圍第9項所述之封裝體層疊結構，其中該接觸墊陣列包含沿同心圍繞之一接觸墊外環及多個接觸墊內環，其中該些無銲料凸塊結構係裝設於該外環之每一接觸墊上。
TW102126601A 2012-08-10 2013-07-25 封裝體層疊結構 TWI520292B (zh)

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