CN103579151A - 小间距堆叠封装结构 - Google Patents

小间距堆叠封装结构 Download PDF

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CN103579151A
CN103579151A CN201210576531.6A CN201210576531A CN103579151A CN 103579151 A CN103579151 A CN 103579151A CN 201210576531 A CN201210576531 A CN 201210576531A CN 103579151 A CN103579151 A CN 103579151A
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contact pad
cube structure
projection cube
solder projection
substrate
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CN103579151B (zh
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蔡再宗
林俊成
洪艾蒂
蔡易达
郑明达
刘重希
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
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    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
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    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
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    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
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Abstract

本发明公开了一种堆叠封装(PoP)器件。该堆叠封装(PoP)器件包括衬底,具有围绕该衬底的外围布置的接触焊盘阵列,安装至接触焊盘阵列内部的衬底的逻辑芯片,以及安装在数量少于所有可用的接触焊盘的接触焊盘上的非焊料凸块结构。本发明还公开了小间距堆叠封装结构。

Description

小间距堆叠封装结构
技术领域
本发明涉及堆叠封装结构,具体而言,涉及小间距堆叠封装结构。
背景技术
随着对更小电子产品的需求增长,制造商和其他从事电子产业的人们不断地寻找得以缩小用于电子产品的集成电路的尺寸的方法。在这方面,三维式集成电路封装技术已经被开发并使用。
一种被开发的封装技术是堆叠封装(PoP)。顾名思义,PoP是一种半导体封装的革新,其涉及将一个封装件堆叠在另一个封装件上方。一种PoP器件可能结合纵向离散存储器和逻辑封装件。在PoP封装设计中,上方的封装件可能使用球栅阵列(BGA)中的焊球与下方的封装件互连。不幸的是,该BGA焊球具有间距和尺寸限制。
发明内容
为了解决现有技术中存在的问题,根据本发明的一个方面,提供了一种堆叠封装(PoP)器件,包括:衬底,具有围绕所述衬底的外围布置的接触焊盘阵列;逻辑芯片,被安装至所述接触焊盘阵列内部的衬底;以及非焊料凸块结构,被安装在数量少于所有可用的接触焊盘的接触焊盘上。
在上述PoP器件中,其中,所述非焊料凸块结构包括通过引线接合工艺形成的柱形凸块。
在上述PoP器件中,其中,所述非焊料凸块结构包括铜球。
在上述PoP器件中,其中,所述非焊料凸块结构由金、银、铜和铝中的一种形成。
在上述PoP器件中,其中,相邻所述非焊料凸块结构之间的间距小于或等于100μm。
在上述PoP器件中,其中,所述非焊料凸块结构的宽度小于所述非焊料凸块结构的高度。
在上述PoP器件中,其中,所述非焊料凸块结构仅被安装在位于所述衬底的拐角上的接触焊盘上。
在上述PoP器件中,其中,所述接触焊盘阵列包括与接触焊盘的外环同轴的接触焊盘的内环,安装在所述外环中的每个接触焊盘上和仅安装在形成所述内环的拐角的接触焊盘上的所述非焊料凸块结构。
在上述PoP器件中,其中,所述接触焊盘阵列包括与接触焊盘的外环同轴的接触焊盘的内环,仅安装在每个所述内环和所述外环中的间隔接触焊盘上的所述非焊料凸块结构。
在上述PoP器件中,其中,所述接触焊盘阵列包括与接触焊盘的外环同轴的接触焊盘的内环,仅安装在每个所述内环和所述外环中的间隔接触焊盘上的所述非焊料凸块结构,其中,安装在所述内环上的非焊料凸块结构从安装在所述外环的非焊料凸块结构偏移其中一个接触焊盘。
在上述PoP器件中,其中,所述接触焊盘阵列包括与接触焊盘的方形外环同轴的接触焊盘的方形内环。
在上述PoP器件中,其中,所述非焊料凸块结构以非对称方式安装在数量少于所有的接触焊盘的接触焊盘上。
根据本发明的另一方面,还提供了一种堆叠封装(PoP)器件,包括:印刷电路板,具有以同轴环围绕衬底的外围布置的接触焊盘阵列;逻辑芯片,以倒装芯片安装结构安装至所述衬底并且位于所述接触焊盘阵列的内部;以及非焊料凸块结构,安装在数量少于所有的接触焊盘的接触焊盘上。
在上述PoP器件中,其中,所述非焊料凸块结构包括柱形凸块和铜球之一。
在上述PoP器件中,其中,所述非焊料凸块结构由金,银,铜,以及铝中的一种形成,并且相邻的所述非焊料凸块结构之间的间距小于或等于100μm。
在上述PoP器件中,其中,所述非焊料凸块结构仅安装在位于所述衬底的拐角上的接触焊盘上。
在上述PoP器件中,其中,所述接触焊盘阵列包括与接触焊盘的外环同轴的接触焊盘的内环,安装在所述外环中的每个接触焊盘上和仅安装在形成所述内环的拐角的接触焊盘上的所述非焊料凸块结构。
在上述PoP器件中,其中,所述接触焊盘阵列包括与接触焊盘的外环同轴的接触焊盘的内环,仅安装在每个所述内环和所述外环中的间隔接触焊盘上的所述非焊料凸块结构。
在上述PoP器件中,其中,所述接触焊盘阵列包括与接触焊盘的多个内环同轴的接触焊盘的外环,安装在所述外环中的每个接触焊盘上的所述非焊料凸块结构。
在上述PoP器件中,其中,所述非焊料凸块结构以非对称方式安装在数量少于所有的接触焊盘的接触焊盘上。
附图说明
为了更加全面的理解本发明及其优点,可以结合附图参考以下描述,其中:
图1示出具有围绕逻辑芯片布置的球栅阵列(BGA)焊球的堆叠封装(PoP)器件的平面图;
图2示出图1的PoP器件大致沿着线2-2得到的截面图;
图3示出具有围绕逻辑芯片布置的非焊料凸块结构的PoP器件;
图4示出了图3的PoP器件大致沿着线4-4得到的截面图;
图5a示出了柱形凸块形式的实施例非焊料凸块结构;
图5b示出了铜球形式的实施例非焊料凸块结构;
图6示出了标识图5a-图5b的暴露的接触焊盘和非焊料凸块结构(即,接触器件)的图例;
图7示出了暴露的接触焊盘相对于非焊料凸块结构的实施例图案;
图8示出了暴露的接触焊盘相对于非焊料凸块结构的实施例图案;并且
图9示出了暴露的接触焊盘相对于非焊料凸块结构的实施例图案。
除非特别说明,不同附图中相应的数字和符号通常指的是相应的部分。绘制附图以清晰地示出实施例的相关方面,但不需要按比例绘制。
具体实施方式
下文详细讨论目前优选的实施例的制造和使用。然而,应该理解,本发明提供了许多可以在具体的环境中实现的可应用的发明构思。所讨论的具体实施例仅仅是示例性的,而并不限定本发明的范围。
将关于具体环境中的优选实施例描述本发明,即,堆叠封装(PoP)半导体器件。然而,本发明中的构思也可以应用于其他半导体结构或电路。
参见图1,示出了PoP器件10。PoP器件10通常包括:支撑围绕逻辑芯片16布置的球栅阵列(BGA)焊球14的衬底12(例如,印刷电路板(PCB))。如图2所示,每个焊球14具有约150μm至250μm的直径18。相邻焊球14之间的球距20在约300μm至400μm之间。虽然这些尺寸可以适于现有PoP器件,但是对于更高级的PoP器件,将需要一个或全部这些尺寸的显著缩小。
现参考图3,示出PoP器件22。PoP器件22通常包括:支撑围绕逻辑芯片28布置的非焊料凸块结构26(即,接触器件)的衬底24(例如,印刷电路板(PCB))。研究发现,使用图3的非焊料凸块结构24替代图2的BGA焊球14允许封装尺寸减小。因此,用非焊料凸块结构24替换图2的BGA焊球14允许更小的整体封装。
在实施例中,图3的逻辑芯片28可以是一个或多个标准逻辑集成电路(IC),诸如:例如,中央处理单元(CPU),微控制器单元(MCU),应用处理器,系统核心逻辑芯片集,图形和成像控制器,大容量存储控制器以及I/O控制器。在实施例中,逻辑芯片28可以是一个或多个专用集成电路(ASIC),诸如:例如,基于可编程器件的设计(PDD),基于栅极阵列的设计(GAD),基于单元的IC(CBIC),以及全客户设计(FCD)。
如图4所示,在实施例中,当BGA焊球14被使用时,相邻非焊料凸块结构26之间的间距30小于间距20(300μm)。实际上,在实施例中,图4中相邻非焊料凸块结构26之间的间距30小于约100μm。虽然图4描述非焊料凸块结构26的4个行32,PoP器件10中可以包括更多或更少的行。
现参考图5a,示出了柱形凸块34形式的实施例非焊料凸块结构26。柱形凸块34可以通过,例如,引线接合工艺形成。如图所示,柱形凸块34具有高度H,其小于宽度W。高度和宽度的具体尺寸取决于引线接合工艺中引线的选择。不管怎样,柱形凸块34通常在至少一个尺寸或方向上小于图2的BGA焊球14。柱形凸块34可以由各种合适的金属非焊料材料形成,包括但不限于金,银,铜,铝,或它们的合金。
现参考图5b,示出了铜凸块36形式的实施例非焊料凸块结构26。铜凸块34的直径38通常小于图2所示的BGA焊球14的直径。在实施例中,凸块结构26也可以是金球,银球,或铝球,其每一个都类似于图5b所示的铜球36。凸块结构26也可以由合适的金属非焊料合金形成。
现参考图6,提供了标识暴露的接触焊盘42和图5a-5b的非焊料凸块结构26的图例40。关于图6的图例40,图7-9示出了暴露的接触焊盘42相对于非焊料凸块结构26的实施例图案44,46,48。尽管图7-9描述了特定图案44,46,48,但是可以使用其他图案。
以下将更详细地解释,非焊料凸块结构26被安装在接触焊盘50上,小于衬底24上可用的接触焊盘50的整体。实际上,一些接触焊盘50被其中一个非焊料凸块结构26覆盖,或在接触焊盘50上安装其中一个非焊料凸块结构26。那些未支撑其中一个非焊料凸块结构26的接触焊盘50被称为图6的图例40中标识的暴露的接触焊盘42。在实施例中,焊料膜的薄层被设置在非焊料凸块结构26的下方,而在暴露的接触焊盘42的上方。
如图7所示,衬底24具有大致围绕衬底24的外围52布置的接触焊盘50的阵列。此外,逻辑芯片28被安装至位于接触焊盘50的阵列内部的衬底24。如图所示,一些接触焊盘50是暴露的接触焊盘42,而其他的接触焊盘50具有安装在其上的其中一个非焊料凸块结构26。参见图7,在实施例中,非焊料凸块结构26仅被安装在位于衬底24的拐角54的接触焊盘50上。也就是说,非焊料凸块结构26被布置在PoP器件22的拐角54上。
现参考图8,在实施例中,接触焊盘50的阵列包括与接触焊盘50的外环58同轴的接触焊盘50的内环56。在实施例中,非焊料凸块结构26被安装在外环58中的每个接触焊盘50上和仅安装在形成内环56的拐角54的接触焊盘56上。现参考图9,在实施例中,非焊料凸块结构26仅被安装在每个内环56和外环58中的间隔接触焊盘50上。此外,安装在内环56上的非焊料凸块结构26从安装在外环58上的非焊料凸块结构26偏移其中一个接触焊盘50。
在实施例中,凸块结构26可以以对称方式,非对称方式,或它们的组合排列。也就是说,凸块结构26可以以任何各种不同的结构安装在接触焊盘50上。
在每个图7-9中,接触焊盘50的阵列包括与接触焊盘50的方形外环58同轴的接触焊盘50的方形内环56。即便如此,也可以使用其他结构。此外,在其他实施例中,可以使用接触焊盘50的更多或更少的环。
一种堆叠封装(PoP)器件包括:衬底,该衬底具有围绕衬底的外围布置的接触焊盘阵列;逻辑芯片,被安装至接触焊盘阵列内部的衬底;以及非焊料凸块结构,安装在数量少于所有可用的接触焊盘的接触焊盘上。
一种堆叠封装(PoP)器件包括:印刷电路板,具有以围绕衬底外围的同轴环布置的接触焊盘阵列;逻辑芯片,以倒装芯片安装结构安装至衬底并且位于接触焊盘阵列的内部;以及非焊料凸块结构,安装在数量少于所有的接触焊盘的接触焊盘上。
一种形成堆叠封装(PoP)器件的方法包括:围绕衬底的外围布置接触焊盘阵列,安装逻辑芯片至接触焊盘阵列内部的衬底,以及在数量少于所有的接触焊盘的接触焊盘上安装非焊料凸块结构。
虽然本发明按照示例性的实施例来描述,但是并不打算以限定的意思解释该描述。在参考该描述的基础上,该示例性实施例的各种修改和组合,以及本发明的其他实施例对于本领域普通技术人员将是显而易见的。因此意图使所附的权利要求涵盖任何这种修改或实施例。

Claims (10)

1.一种堆叠封装(PoP)器件,包括:
衬底,具有围绕所述衬底的外围布置的接触焊盘阵列;
逻辑芯片,被安装至所述接触焊盘阵列内部的衬底;以及
非焊料凸块结构,被安装在数量少于所有可用的接触焊盘的接触焊盘上。
2.根据权利要求1所述的PoP器件,其中,所述非焊料凸块结构包括通过引线接合工艺形成的柱形凸块。
3.根据权利要求1所述的PoP器件,其中,所述非焊料凸块结构包括铜球。
4.根据权利要求1所述的PoP器件,其中,所述非焊料凸块结构由金、银、铜和铝中的一种形成。
5.根据权利要求1所述的PoP器件,其中,相邻所述非焊料凸块结构之间的间距小于或等于100μm。
6.一种堆叠封装(PoP)器件,包括:
印刷电路板,具有以同轴环围绕衬底的外围布置的接触焊盘阵列;
逻辑芯片,以倒装芯片安装结构安装至所述衬底并且位于所述接触焊盘阵列的内部;以及
非焊料凸块结构,安装在数量少于所有的接触焊盘的接触焊盘上。
7.根据权利要求6所述的PoP器件,其中,所述非焊料凸块结构包括柱形凸块和铜球之一。
8.根据权利要求6所述的PoP器件,其中,所述非焊料凸块结构由金,银,铜,以及铝中的一种形成,并且相邻的所述非焊料凸块结构之间的间距小于或等于100μm。
9.根据权利要求6所述的PoP器件,其中,所述非焊料凸块结构仅安装在位于所述衬底的拐角上的接触焊盘上。
10.根据权利要求6所述的PoP器件,其中,所述接触焊盘阵列包括与接触焊盘的外环同轴的接触焊盘的内环,安装在所述外环中的每个接触焊盘上和仅安装在形成所述内环的拐角的接触焊盘上的所述非焊料凸块结构。
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Families Citing this family (2)

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Publication number Priority date Publication date Assignee Title
JP5590260B1 (ja) * 2014-02-04 2014-09-17 千住金属工業株式会社 Agボール、Ag核ボール、フラックスコートAgボール、フラックスコートAg核ボール、はんだ継手、フォームはんだ、はんだペースト、Agペースト及びAg核ペースト
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040023436A1 (en) * 2001-09-17 2004-02-05 Megic Corporation Structure of high performance combo chip and processing method
US20070001296A1 (en) * 2005-05-31 2007-01-04 Stats Chippac Ltd. Bump for overhang device
US20070152350A1 (en) * 2006-01-04 2007-07-05 Samsung Electronics Co., Ltd. Wiring substrate having variously sized ball pads, semiconductor package having the wiring substrate, and stack package using the semiconductor package
US20070190690A1 (en) * 2006-02-14 2007-08-16 Stats Chippac Ltd. Integrated circuit package system with exposed interconnects
US20090224401A1 (en) * 2008-03-04 2009-09-10 Elpida Memory Inc. Semiconductor device and manufacturing method thereof

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5490040A (en) * 1993-12-22 1996-02-06 International Business Machines Corporation Surface mount chip package having an array of solder ball contacts arranged in a circle and conductive pin contacts arranged outside the circular array
US5468995A (en) * 1994-07-05 1995-11-21 Motorola, Inc. Semiconductor device having compliant columnar electrical connections
SG71734A1 (en) * 1997-11-21 2000-04-18 Inst Materials Research & Eng Area array stud bump flip chip and assembly process
US6225699B1 (en) * 1998-06-26 2001-05-01 International Business Machines Corporation Chip-on-chip interconnections of varied characteristics
US5977640A (en) * 1998-06-26 1999-11-02 International Business Machines Corporation Highly integrated chip-on-chip packaging
US6495910B1 (en) * 2000-08-25 2002-12-17 Siliconware Precision Industries Co., Ltd. Package structure for accommodating thicker semiconductor unit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040023436A1 (en) * 2001-09-17 2004-02-05 Megic Corporation Structure of high performance combo chip and processing method
US20070001296A1 (en) * 2005-05-31 2007-01-04 Stats Chippac Ltd. Bump for overhang device
US20070152350A1 (en) * 2006-01-04 2007-07-05 Samsung Electronics Co., Ltd. Wiring substrate having variously sized ball pads, semiconductor package having the wiring substrate, and stack package using the semiconductor package
US20070190690A1 (en) * 2006-02-14 2007-08-16 Stats Chippac Ltd. Integrated circuit package system with exposed interconnects
US20090224401A1 (en) * 2008-03-04 2009-09-10 Elpida Memory Inc. Semiconductor device and manufacturing method thereof

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