TWI517323B - 在半導體晶粒中用於減緩應力的路由層 - Google Patents

在半導體晶粒中用於減緩應力的路由層 Download PDF

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Publication number
TWI517323B
TWI517323B TW099130609A TW99130609A TWI517323B TW I517323 B TWI517323 B TW I517323B TW 099130609 A TW099130609 A TW 099130609A TW 99130609 A TW99130609 A TW 99130609A TW I517323 B TWI517323 B TW I517323B
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Taiwan
Prior art keywords
bump
pads
semiconductor die
bump pads
conductive traces
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TW099130609A
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English (en)
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TW201133737A (en
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羅登 塔巴西歐
葛瑞爾 汪
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Ａｔｉ科技Ｕｌｃ公司
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Publication of TW201133737A publication Critical patent/TW201133737A/zh
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Description

在半導體晶粒中用於減緩應力的路由層
本發明一般而言係關於半導體晶粒，更詳而言之，係關於用於半導體晶粒之路由層設計。
現代半導體封裝件係藉由於半導體晶圓上形成一些積體電路而製造得到。該半導體晶圓典型上係切割成為個別的塊，各塊皆稱為晶粒(die)。各個晶粒皆於一個表面上包含一個或多個積體電路。此表面(經常稱作為“主動表面”)包含一些稱作輸入/輸出(I/O)墊的信號介面接點(signal interface contact)。
典型上係利用包含適於附接於外部電路板的銲錫球(solder ball)之載體基板(carrier substrate)來封裝晶粒。該載體基板通常包含核心以及形成於該核心任一側上之一個或多個累增層(buildup layer)。各個累增層具有形成於介電材料層上之金屬化物(metallization)或跡線(trace)。該載體基板包含多個接合銲墊(bond-pad)，用於與該晶粒之I/O墊電性互連。該基板上之導電跡線係用以將個別接合銲墊與其相應之銲錫球互連。
於該晶粒上之I/O墊與該基板上之接合銲墊之間，可使用各種接合技術以形成可靠的電性連接。兩種最常見的技術係導線接合(wire-bonding)以及覆晶組合(flip chip assembly)。
於導線接合中，該晶粒係置於該載體基板上，其主動表面背向該載體基板。接著導線之一端係接合至該晶粒上之I/O墊，而另一端係接合至該基板上相應之接合銲墊。
然而，於覆晶組合中，當附接該晶粒時，該晶粒之主動表面面向該載體基板。在附接之前，稱為銲錫凸塊之少量銲錫係沉積於各個I/O墊上。該等銲錫凸塊接著經熔化以將該晶粒上之各個I/O墊互連至該基板上相應之接合銲墊。
晶粒上之I/O墊可放置於該晶粒之主動表面上方任何位置。舉例而言，於一些晶粒中，I/O墊可分布於整個主動表面上方，而於其他晶粒中，該等I/O墊可能被限制於接近該晶粒之週邊邊緣。於任一種情況下，晶粒上之I/O墊典型上未與最終會附接至其上之基板上之接合銲墊對齊。該等I/O墊亦可能互相過於接近，而無法形成適當的銲錫凸塊，如同於覆晶組合期間所需者。因此，將這些原本的I/O墊重新分布至更適合形成銲錫凸塊之新的銲墊位置(稱為凸塊銲墊)通常係有利的。該等凸塊銲墊可對齊基板上之接合銲墊，並且利用銲錫凸塊而被附接。為了將原本的I/O墊重新分布至適於覆晶接合之新的凸塊銲墊位置，路由層或重新分布層(redistribution layer；RDL)典型上係形成於該矽晶圓、或個別晶粒上方並於該主動表面上。
該路由層經常形成於薄介電層上，於該路由層上形成有多個導電跡線，以將各個I/O墊互連至相應之凸塊銲墊。該等導電跡線係藉由該介電材料而與該晶粒之較下側層(lower layers)絕緣，除了它們所互連之I/O墊處以外。該路由層允許I/O驅動器放置於該晶粒中任何地方，無須考慮該基板接合銲墊之位置。由於該重新分布層會使形成於該晶粒之凸塊銲墊上之銲錫凸塊對齊該基板上之接合銲墊，故I/O驅動器可自由地放置於該晶粒中。使用路由層亦可簡化基板之形成，且經常造成累增層的減少，因而降低成本。
根據路由需求，該路由層可包含多個介電材料層以及相關的跡線。該頂部路由層上方經常形成有鈍化層，以保護金屬跡線免於曝露於空氣中。該鈍化層中的開口曝露出該等凸塊銲墊。
凸塊底層金屬(UBM)典型上形成於該等經曝露出的凸塊銲墊上，以提供低電阻電性連接至銲錫凸塊，用於附接至該基板。銲錫凸塊典型上係例如藉由沉積銲錫膏(solder paste)形成於該凸塊銲墊之UBM上。
於覆晶附接期間，形成於該等經重新分布的凸塊銲墊上的銲錫凸塊係與該基板中相應之接合銲墊對齊，並且接著經回銲或熔化以形成可靠的電性與機械接點。
在將半導體晶粒附接至基板之後，其銲錫凸塊經常於操作期間遭受到機械與熱應力。各個凸塊銲墊幫助吸收大量若未被吸收則可能影響該路由層中之下層介電層之應力。為了緩衝此類來自銲錫凸塊之應力，各個凸塊銲墊經常製作成至少大小相當於(且經常實質上大於)與其相應之UBM。
然而，如此一來不利的是，較大的凸塊銲墊會縮減該路由層中路由導電跡線可用之面積，導致可能潛在地危及信號完整性的較密集跡線與凸塊銲墊之設置。此外，必須繞過大型凸塊銲墊進行路由之跡線可能必須製作成較長的長度，如此會增加其電阻與電容。在跡線中增加的電阻與電容經常於電源跡線中導致電壓降(voltage drop)以及於信號跡線中導致較長的傳遞延遲(propagation delay)。此外，較新、較小的晶粒經常需要更小的凸塊銲墊以增加可用於路由之面積，且經常使用易損壞的介電材料。
一種習知用於縮減凸塊銲墊尺寸之方法，係於形成於小型凸塊銲墊頂部的大型UBM之間使用聚醯亞胺(Polyimide)，以助於減緩可能影響該晶粒之介電層之應力。然而，不幸地，如此一來將增加封裝成本且可能無法與易損壞的介電層一起運作良好。
因此，需要能夠增加跡線數量而不會危及信號完整性之半導體晶粒，並且保護介電層免於熱應力與機械應力。
依據本發明之一個實施例，提供一種半導體晶粒，包含：積體電路，係形成於一塊半導體晶圓之一個表面上；互連至該積體電路的複數個輸入/輸出(I/O)墊；以及路由層。該路由層包含：介電層，係形成於該一個表面上；以及複數個導電跡線，係形成於該介電層上，各該導電跡線延伸於該等I/O墊其中一者與形成於該介電層上之複數個凸塊銲墊其中一者之間。該半導體晶粒亦包含：複數個凸塊底層金屬(UBMs)，各該凸塊底層金屬具有用於附接複數個銲錫凸塊各者之頂部表面；以及底部接觸表面，係小於該頂部表面，且與個別凸塊銲墊各者實體接觸。至少一些該等導電跡線在該等UBM之該頂部表面下方通過靠近的凸塊銲墊且並未接觸該等凸塊銲墊，以機械性加強靠近該等UBM之路由層。
依據本發明另一實施例，提供一種半導體晶粒，包含：至少一個積體電路，係形成於一個表面上，以及連接至該積體電路之複數個輸入/輸出(I/O)墊；路由層，包括：介電層，係形成於該晶粒之表面上、以及複數個導電跡線，係形成於該介電層上，各該導電跡線延伸於該等I/O墊其中一者與複數個形成於該介電層上之凸塊銲墊其中一者之間；以及複數個銲錫凸塊，係形成於該等凸塊銲墊上，用於將該積體電路電性互連至基板。半徑大於或等於形成於各該凸塊銲墊上之相應之凸塊底層金屬(UBM)之頂部表面之平均半徑的圓形劃線區域中包含有至少一個該等凸塊銲墊。至少一些該等導電跡線通過該圓形劃線區域而未接觸該圓形劃線區域所包含之凸塊銲墊，以機械性加強靠近該圓形劃線區域所包含之凸塊銲墊的路由層。
熟習本領域者藉由參照以下本發明說明書中之特定實施例結合附加圖式將清楚了解本發明之其他態樣與特徵。
第1圖描繪習知半導體晶粒100之路由層之平面圖式。晶粒100包含形成其部份積體電路之原本的I/O墊114A、114B、114C(個別地與全體地為I/O墊114)，以及經重新分布而適於形成覆晶銲錫凸塊之凸塊銲墊104A、104B、104C、104D(個別地與全體地為凸塊銲墊104)。導電跡線122A、122B、122C、122D、122E、122F(個別地與全體地為導電跡線122)將I/O墊114互連至相應之凸塊銲墊104。
第2圖描繪一部分習知半導體晶粒100之垂直剖面圖式，包含導電跡線122、I/O墊114、以及於其上形成有銲錫凸塊112之凸塊銲墊104。I/O墊114係形成於晶粒100之下側金屬層(lower metal layer)116上，該晶粒包含形成於一塊半導體晶圓(例如：矽晶圓)上之積體電路。
凸塊銲墊104提供多個I/O連接點予該積體電路。形成於凸塊銲墊104上之銲錫凸塊112係用以利用覆晶附接技術將晶粒100附接至基板(如載體基板或印刷線路板)。
路由層108(形成於下側金屬層116上方)包含介電層120與形成於該介電層120上之導電跡線122。除了於該I/O墊114處以外，介電層120將下側金屬層116與導電跡線122絕緣。各個導電跡線122將I/O墊114互連至凸塊銲墊104。
形成於各個凸塊銲墊104上之凸塊底層金屬(UBM)102提供了用於各個銲錫凸塊112之低電阻附接表面。各個UBM 102皆可具有與銲錫凸塊112連通之頂部表面102A以及與凸塊銲墊104連通之底部接觸表面102B。
為了將晶粒100互連至基板，銲錫凸塊122係與該基板上之接合銲墊對齊，並且利用熱經熔化以形成與該基板之電性與機械性接合。
於操作期間，半導體晶粒100消耗電壓或電流輸入形式之電能，並且將一些能量散逸為熱能。熱能造成晶粒100與該晶粒100所附接之基板兩者以它們個別的熱膨脹係數(CTE)膨脹。晶粒100之CTE與該基板之CTE(晶粒100係經由銲錫凸塊112互連至該基板)經常是不同的。此種CTE數值不匹配會對銲錫凸塊112與其他附近結構(如UBM 102與路由層108中的介電材料120)造成熱應力。除了熱應力以外，靠近銲錫凸塊112之結構亦可能遭受到起因於該基板或晶粒100之屈曲(flexing)及/或振動之機械應力。
熱應力與機械應力可能潛在地損害路由層108(尤其是介電材料120)與下側層116中所使用的其他材料。舉例而言，極低K值(extreme low K；ELK)介電材料(具有介電常數值k<3.0)可使用於下側層116中。然而，ELK材料係易於損壞，且可能因機械或熱應力而翹曲、破裂或毀壞。非必為ELK的介電材料亦可能因曝露於熱或機械應力而損壞。
為了減緩應力對路由層108之介電材料120與下側層116之影響，凸塊銲墊104經常製作成大於UBM 102。大型凸塊銲墊有助於吸收若未被吸收則會影響下方之介電材料之應力。
第3圖係描繪UBM 102與凸塊銲墊104之表面之相對尺寸，並描繪沿著第2圖之線段III─III之一部分習知晶粒100之平面圖式。如圖所示，習知凸塊銲墊104係大於UBM 102，因而有助於吸收來自相應之銲錫凸塊(未顯示於第3圖中)的機械與熱應力，藉此避免對介電材料120與下側層116造成損壞。
不幸的是，較大型凸塊銲墊104縮減了在路由層108中可用於路由導電跡線122之面積。此外，為了繞過較大銲墊104進行路由，一些跡線的長度必須較長。如同所提及，較長的跡線會增加電阻與電容，其轉而導致沿著電源跡線之電壓降，並且增加跨越信號跡線之傳遞延遲。再者，利用45奈米或更小的製程技術所形成之積體電路典型上具有較小尺寸，且經常以ELK介電材料進行封裝。大型凸塊銲墊(如凸塊銲墊104)可能無法適於此類裝置。
因此，本發明之例示實施粒可採用適合與ELK介電材料一起使用之較小尺寸凸塊銲墊。較小的銲墊尺寸可釋放空間，容許增加給定面積中電源與接地跡線的密度。反之，重新釋放之空間，能夠增加平行跡線之間的間隔，可降低串擾(crosstalk)。可體認到，經降低的串擾、及/或經增加的電源與接地跡線有助於改善信號完整性並增進效能。
因此，第4圖描繪本發明例示實施例之半導體晶粒200之垂直剖面。第5圖描繪第4圖之例示晶粒200之一部分的平面圖式。如圖所示，例示晶粒200包含形成於一塊半導體晶圓(例如：矽晶圓或砷化鎵晶圓)上之積體電路(IC)與互連至該IC之I/O墊214，該I/O墊214可由例如鋁(Al)或銅(Cu)製成。
晶粒200亦可包含由一層或多層介電材料220所製成之路由層208，各層介電材料220具有形成於其上之導電跡線222A、222B、222C(個別地與全體地為導電跡線222)之層。晶粒200可包含如鈍化層206之保護罩蓋(protective cover)，以遮蔽導電跡線222免於曝露於空氣中，藉此防止發生氧化。導電跡線222可將I/O墊214互連至相應之凸塊銲墊204。
可形成複數個銲錫凸塊212，各個銲錫凸塊212分別位於其中一個凸塊銲墊204上。銲錫凸塊212可用以利用覆晶附接方法將晶粒200附接至基板。銲錫凸塊212可對齊該基板上相應之接合銲墊，並且經回銲以形成電性與機械性接合。覆晶附接方法係熟習本領域者所熟知之技術。
各個導電跡線222可於一端連接I/O墊214至相應之凸塊銲墊204(並因而連接至銲錫凸塊212)。凸塊銲墊204便於提供I/O互連至晶粒200上之積體電路。
可體認到，若不用考慮凸塊銲墊的配置(placement)，則有利於設計I/O墊214與相關I/O驅動器電路系統之配置，以免與其他最佳化(optimization)發生衝突。I/O墊214可為區域銲墊(area pad)、多列銲墊(multi-row pad)、邊緣銲墊(perimeter pad)等。不論I/O墊214的位置為何，路由層208皆可用以將I/O墊214重新分布至凸塊銲墊204，以將銲錫凸塊212對齊基板上的個別接合銲墊。
導電跡線222典型上係由銅或鋁製成，但是亦可由其他金屬(如金、鉛、錫、銀、鉍、銻、鋅、鎳、鋯、鎂、銦、碲、鎵等)製成。亦可使用上述一種或多種金屬的合金。
凸塊底層金屬(UBM)202可形成於各個凸塊銲墊204上，以提供低電阻安置表面(mounting surface)予銲錫凸塊212。舉例而言，於一個實施例中，銲錫膏可沉積於各個UBM 202上，以形成各個銲錫凸塊212。
各個UBM 202皆可具有與相應之銲錫凸塊212連通之頂部表面202A以及與底下之個別凸塊銲墊204連通之底部接觸表面202B。UBM 202於其頂部表面202A與其底部接觸表面202B之間可包含數個子層(sub-layer)(未顯示)，如黏著子層、擴散阻障子層(diffusion barrier sub-layer)、銲錫潤濕子層(solder-wettable sub-layer)、以及視需要選用的氧化阻障子層。底部接觸表面202B係與凸塊銲墊204實體接觸。
形成UBM 202可包含清潔、移除絕緣氧化物，並且沉積冶金層(metallurgy)，該冶金屬係良好地電性與機械性連接至銲錫凸塊212。該銲錫潤濕子層提供易於潤濕的表面予該經熔化的銲錫，用於使銲錫凸塊212良好地接合至下方的凸塊銲墊204。可利用熱能將銲錫凸塊212(類似第2圖之銲錫凸塊112)熔化，以於半導體晶粒200與基板或電路板之間形成電性與機械性互連。
如同下文中將詳述者，晶粒200之凸塊銲墊204小於晶粒100之凸塊銲墊104。如此一來，路由層208提供更多空間或增加之空間以供導電跡線222路由之用，可造成導電跡線具有較短的長度。較短的跡線有利於降低跡線的電阻與電容。經降低的電阻與電容值轉而降低橫跨電源跡線之電壓降以及沿著信號跡線之較小信號傳遞延遲。
第6圖描繪沿著第5圖之線段VI─VI之半導體晶粒200之垂直剖面圖。如同第6圖所描繪，例示之凸塊銲墊204小於其相應之UBM202。例示之凸塊銲墊204藉由金屬跡線222而與I/O墊214互連。
將第2圖與第4圖作比較(或者將第3圖與第5圖作比較)，可觀察到較小的凸塊銲墊204能夠容許在由凸塊銲墊104所佔據之大約相同面積內路由一些導電跡線222A、222B、及222C(個別地與全體地為導電跡線222)。凸塊銲墊104與凸塊銲墊204之相對尺寸係進一步描繪於第7圖與第9圖中。
現在，為了減緩因為對凸塊銲墊204縮減尺寸而可能造成的應力在路由層208中介電材料上應力的影響，可於凸塊銲墊204附近路由一個或多個導電跡線222，以助於吸收機械性及/或熱機械應力。
更具體而言，於第4至第6圖所描繪之特定實施例中，導電跡線222A、222B、222C通過靠近的凸塊銲墊204，以機械性加強靠近UBM 202之路由層208。導電跡線222A、222B之包圍或通過靠近的凸塊銲墊204的部分可位於UBM 202之頂部表面202A下方，但並非位於與凸塊銲墊204實體接觸的底部接觸表面202B下方。因此，導電跡線222A、222B加強了靠近UBM 202之路由層208。導電跡線222A、222B之通過靠近的凸塊銲墊204的部分可因而吸收來自附接至凸塊銲墊204之銲錫凸塊之機械及/或熱應力，以保護靠近銲錫凸塊212之下方的介電材料220。
如第5圖所示，各個凸塊銲墊204可包含於具有大於或等於UBM 202A之頂部表面之平均半徑RUBM之半徑Rarea的圓形劃線區域224內(亦即：Rarea RUBM，其中RUBM=D2/2)。如同稍後將詳述者，至少一些導電跡線(例如：跡線222A、222B)可通過圓形劃線區域224而未直接接觸其中所包含之凸塊銲墊，以機械性加強靠近所包含之凸塊銲墊的路由層208。
圓形劃線區域224內部的凸塊銲墊204與部分導電跡線222A、222B、222C可視為具有與習知凸塊銲墊104相同大小的有效尺寸的“虛擬銲墊”(由應力吸收的觀點來看)。劃線區域224能夠有效地緩衝來自對應之銲錫凸塊(形成於經劃線的凸塊銲墊204上之UBM表面202A上)之應力，藉此保護該下方之介電材料免於應力所導致的損害。當然於其他實施例中，圓形劃線區域224的尺寸可能與習知凸塊銲墊104相同、更大或甚至稍為較小。
為了比較銲墊、UBM、以及不同形狀的劃線區域的相對尺寸，於給定形狀內所內切的圓形之直徑可用來代表該形狀之尺寸。
於第2圖中，內切於UBM 102之頂部表面102A內的圓形之直徑可為大約80微米(亦即，d2 80微米)。換言之，UBM頂部表面102A之內切半徑(inradius)係大約80微米/2=40微米。內切於凸塊銲墊104內的圓形之直徑可為大約92微米(亦即，d3 92微米)；且內切於開口110內的圓形之直徑(或者內切於底部接觸表面102B內的圓形之直徑，並且標示為d1)可為大約60微米(亦即，d1 60微米)。
然而，於第4圖中，於一個實施例中，UBM 202之頂部表面202A(之內切於其內的圓形)之直徑(標示為D2)可為大約80微米(亦即，D2 80微米)。凸塊銲墊204(之內切於其內的圓形)之直徑可為大約50微米(亦即，第4圖中D3 50微米)且開口210(之內切於其內的圓形)之直徑(在第4圖中標註為D1)可為大約46微米(亦即，D1 46微米)。各個導電跡線222之寬度(標示為W1)可為大約12微米。如同熟習本領域者將體認到，上述數字僅為例示，且於其他實施例中可使用較大或較小的尺寸。
同樣地，UBM之表面202A、202B、凸塊銲墊204以及開口210的形狀不必是均勻的或必為八角形。相反地，UBM 202、凸塊銲墊204以及鈍化開口210能夠採用任何形狀與各種尺寸變化。上述各者的形狀可為例如其他多邊形(如六角形或矩形)。上述各者亦可採用其他形狀：可為圓形、橢圓形、不規則形狀或者適當尺寸之任何任意形狀。
導電跡線222A、222B、222C配置成圍繞或包圍例示路由層208中凸塊銲墊204係有利的。除了能夠於給定面積內增加信號路由跡線之數量以外，上述配置創造了圓形劃線區域224形式之應力緩衝區，能夠有效提供和大很多的習知凸塊銲墊104相同之保護以對抗應力。可體認到，靠近凸塊銲墊204(於區域224中)的導電跡線222A、222B、222C之部分係吸收若未被吸收則可能損害路由層208之下層介電材料的應力。
第7圖描繪例示凸塊銲墊204與習知凸塊銲墊104之相對尺寸，且例示的圓形劃線區域代表各種應力緩衝區的輪廓。區域702相當於較大習知凸塊銲墊104與位於同中心的較小例示凸塊銲墊204之間的表面積差異。於習知凸塊銲墊104中，區域702沒有空間(其形成凸塊銲墊104之一部分)可用於進行路由。採用凸塊銲墊204之例示實施例中，區域702的一部分可便於用於路由跡線。
然而，相反地，在習知銲墊(如凸塊銲墊104)中，儘管全部區域702皆幫助吸收應力，而於本發明例示實施例中，僅有由跡線所占據的部分區域702會吸收應力以加強路由層208。為了增進區域702內的應力吸收，例示實施例可增加區域702由導電跡線所覆蓋的百分比。
於例示路由層208中，該應力緩衝區(應力吸收區域)無須局限於區域702。取而代之，該應力緩衝區可小於或大於區域702。因此，應力緩衝區域可由包含凸塊銲墊204之第一圓形劃線區域224’以及其中所包含的部分跡線所定義。如第7圖所描繪，圓形劃線區域224’的尺寸可小於凸塊銲墊104。然而，可利用包圍凸塊銲墊204的越來越多個跡線來形成大於銲墊104之應力緩衝區，以加強路由層208。這一點係由第7圖所描繪之第二圓形劃線區域224”所例示。可體認到，增加給定之圓形劃線區域(例如：區域224”)中由凸塊銲墊與其中所包含之部分導電跡線所覆蓋之表面積的比例會對靠近所包含之凸塊銲墊的路由層208提供了更好的機械性加強。於一些實施例中，區域702由導電跡線所覆蓋之比例可介於大約30%至100%。
第8圖描繪例示半導體晶粒200之例示路由層208之平面圖式。路由層208包含該積體電路原本的I/O墊214A、214B、214C(個別地與全體地為I/O墊214)、以及經重新分布適於形成覆晶銲錫凸塊之例示凸塊銲墊204A、204B、204C、204D(個別地與全體地為凸塊銲墊204)。導電跡線222D、222E、222F、222G、222H、222I、222J、222K、222L(個別地與全體地為導電跡線222)係用以將I/O墊互連至相應之凸塊銲墊(未全部顯示)。
於第1圖中，凸塊銲墊104A與104D之間僅路由有五個信號跡線。然而，於第8圖中，凸塊銲墊204A與凸塊銲墊204D之間至少可容納十個信號、接地、及電源跡線(亦即，222D、222E、222F、222G、222H、222I、222J、222K、222L及222M)。可觀察到，第8圖之路由層於凸塊銲墊之間包含多很多的信號跡線，但未縮窄分隔鄰近跡線之間隔，如此一來可有助提升信號密度。
於第8圖中，針對路由層208所描繪之導電圖案(conductive pattern)包含：互連第一凸塊銲墊204A之第一導電跡線222A’，用於附接第一銲錫凸塊，以及I/O墊214A；以及互連第二凸塊銲墊204B之第二導電跡線222B’，用於附接第二銲錫凸塊，以及第二I/O墊214B。I/O墊214可為任何形狀且可放置於晶粒200上任何位置。
第9圖亦描繪例示半導體晶粒200之例示路由層208之平面圖式，並顯示出習知的假設凸塊銲墊104A’、104B’、104C’、104D’的輪廓(個別地與全體地為銲墊輪廓104’)，以描繪例示路由層208所達到的相對尺寸與路由密度。
如圖所示，部分導電跡線222B’、222C’(例如：銲墊輪廓104A’內的部分)至少局部地包圍或通過靠近的凸塊銲墊204A。接近凸塊銲墊204A的部分導電跡線222A’、222B’、222C’因而吸收來自附接至凸塊銲墊204A之銲錫凸塊之應力。所描繪之配置係有效地形成“虛擬銲墊”或劃線區域(例如：輪廓104A’或內切於其中的圓形)包圍銲墊204A，以保護靠近銲墊204A的介電層免於熱與機械應力所造成的損害。
第8圖至第9圖亦描繪分別互連至個別導電跡線之額外銲墊204C與204B。如圖所示，雖然導電跡線222B’、222C’並未直接與凸塊銲墊204A互連，但部份導電跡線222B’、222C’有助於保護靠近銲墊204A之介電層。
有利的是，製造半導體晶粒200無須昂貴的額外的步驟。舉例而言，一種用於製造半導體晶粒(如晶粒200)的方法，可包含製備具有至少一個積體電路(IC)的晶圓，該積體電路(IC)包含形成於主動表面上的一組I/O墊。於該晶圓上可形成有包含介電材料層之路由層(如路由層208)。該路由層可具有形成於其上之至少一個導電跡線，將第一銲墊(例如：凸塊銲墊204)互連至第一I/O墊。該路由層亦可包含第二凸塊銲墊、第二I/O墊、以及將該第二凸塊銲墊互連至該第二I/O墊之第二導電跡線。可形成該第二導電跡線(例如：跡線222B’)，以便通過靠近的第一凸塊銲墊(例如：第8圖所示之凸塊銲墊204A)並且亦可局部地包圍該第一凸塊銲墊。該第二導電跡線可因而緩衝來自附接至該第一凸塊銲墊之銲錫凸塊之應力，以保護靠近該銲錫凸塊之下方之介電材料免於受到應力。
亦可形成鈍化層。該製造方法可進一步涉及於該鈍化層上形成開口，以曝露出該等凸塊銲墊並且於各個凸塊銲墊上形成凸塊底層金屬(UBM)銲墊，以於該等凸塊銲墊之上接置、沉積、或附接銲錫凸塊。
該方法可進一步涉及利用覆晶附接而於載體基板之上附接晶粒200。覆晶附接係為熟習本領域者所熟知，且於例如Harper,Charles A. 2005,Electronic Packaging and Interconnection,4th ed. New York: McGraw Hill中進行討論，其中內容將併入本說明書作為參考。
有利的是，第8圖至第9圖所描繪之跡線222的路由圖案能夠增加路由密度，同時吸收來自銲錫凸塊之大部分應力(其若未被吸收則容易對於與較小晶粒共同使用的易損壞介電材料產生負面影響)。相較於較大型的凸塊銲墊，較小的凸塊銲墊204能夠容許有更多用於信號、電源/接地的路由跡線。此外，對於信號傳輸而言，較小的凸塊銲墊204將具有較小的電容。
藉由增加該路由層上之電源/接地跡線數量，可降低電源與接地跡線之有效電阻，有利於達成更有效率的電源使用。此外，本發明實施例之例示半導體晶粒容許凸塊銲墊的形狀不需與形成於其上方之UBM銲墊之形狀相同。
上述實施例可便於避免在UBM與該路由層之間增加聚醯亞胺緩衝的相關成本。
可體認到，為了清楚起見，第4圖至第5圖僅描繪有一個介電材料層220與一個相應之導電跡線層222。然而，熟習本領域者將輕易體認到在其他實施例中該路由層208內可設置有數個藉由介電材料層互相絕緣的導電跡線層。
於其他實施例中，晶粒200之路由層208中的凸塊銲墊中僅有一些被通過靠近的凸塊銲墊的導電跡線所包圍。可能有一些其他的凸塊銲墊不必具有通過接近其個別UBM之導電跡線，以機械性加強路由層208。除了小於本身相應之USM之上側表面的例示凸塊銲墊204以外，亦可能有其他凸塊銲墊大於其相應之UBM(類似凸塊銲墊104)。
本發明之實施例可用於多種應用面，包含製造DRAM、SRAM、EEPROM、快閃記憶體、圖形處理器、一般目的處理器、DSP、以及各種標準類比、數位與混合信號電路封裝件。
當然，上述實施例僅為說明之目的，而非限制本發明。所述實現本發明之實施例可以有許多種形式變更、零件設置、細節設置、以及操作順序。反之，本發明意圖涵蓋落於申請專利範圍所定義之範疇內的所有變更
III-III、VI-VI．．．線段
D1、D2、D3、d1、d2、d3．．．直徑
100、200．．．半導體晶粒
102、202．．．凸塊底層金屬
102A、202A．．．頂部表面
102B、202B．．．底部接觸表面
104、104A、104A’、104B、104B’、104C、104C’、104D、104D’．．．凸塊銲墊
108、208．．．路由層
110、210．．．開口
112、212．．．銲錫凸塊
114、114A、114B、114C、214、214A、214B、214C．．．I/O墊
116．．．下側金屬層；下側層
120．．．介電層
122、122A、122B、122C、122D、122E、122F、222A、222B、222C、222D、222E、222F、222G、222H、222I、222J、222K、222L、222A’、222B’、222C’、222M．．．導電跡線
RUBM．．．平均半徑
Rarea．．．半徑
204、204A、204B、204C、204D．．．凸塊銲墊
206．．．鈍化層
220．．．介電材料
224、224’、224”．．．圓形劃線區域
702．．．區域
W1．．．寬度
於圖式中，僅以範例的方式描繪本發明之實施例。
第1圖係用於習知半導體晶粒之習知路由層，該路由層將I/O墊重新分布至凸塊銲墊；
第2圖係習知半導體晶粒之垂直剖面圖式；
第3圖係第2圖之一部分習知半導體晶粒的垂直剖面圖式；
第4圖係本發明例示實施例之一部分半導體晶粒的垂直剖面圖式；
第5圖係第4圖中所描繪之一部分例示半導體晶粒的平面圖式；
第6圖係第4圖之例示半導體晶粒的另一剖面圖式；
第7圖係描繪第5圖之例示凸塊銲墊與第4圖之習知凸塊銲墊之相對尺寸的圖式；
第8圖係第4圖之半導體晶粒之例示路由層的平面圖式；以及
第9圖係第8圖之平面圖式，繪製有重疊的習知凸塊銲墊，以與例示凸塊銲墊作比較。
200．．．半導體晶粒
202．．．凸塊底層金屬化物
202A．．．頂部表面
202B．．．底部接觸表面
204．．．凸塊銲墊
206．．．鈍化層
208．．．路由層
210．．．開口
212．．．銲錫凸塊
220．．．下層介電材料
222A、222B、222C．．．導電跡線
D1、D2、D3．．．直徑
W1．．．寬度

Claims (27)

  1. 一種半導體晶粒，包括：i)積體電路，係形成於一塊半導體晶圓之一個表面上；ii)互連至該積體電路的複數個輸入/輸出(I/O)墊；iii)路由層，包括：介電層，係形成於該一個表面上；以及複數個導電跡線，係形成於該介電層上，各該導電跡線延伸於該等I/O墊其中一者與形成於該介電層上之複數個凸塊銲墊其中一者之間；iv)複數個凸塊底層金屬(UBMs)，個別包括：頂部表面，用於附接複數個銲錫凸塊各者；以及底部接觸表面，係小於該頂部表面，且與該複數個凸塊銲墊各者實體接觸；位於該路由層之複數個應力緩衝區、各該應力緩衝區劃線UBM及包括實體接觸至少一個之該經劃線的UBM的該凸塊銲墊；以及v)該等導電跡線通過靠近該凸塊銲墊且並未接觸該凸塊銲墊或該經劃線的UBM，以機械性加強靠近該等UBM之該路由層，其中，除了被該凸塊銲墊佔據的區域，該至少一個的該等導電跡線佔據該應力緩衝區30%至100%之間。
  2. 如申請專利範圍第1項所述之半導體晶粒，其中，如同凸塊銲墊具有與該應力緩衝區相同的區域，各該應力緩 衝區提供實質上相同的應力保護。
  3. 如申請專利範圍第1項所述之半導體晶粒，其中，該路由層包括複數個導電跡線層，至少一個介電層將各該導電跡線層與該複數個導電跡線層之另一者分隔開。
  4. 如申請專利範圍第1項所述之半導體晶粒，其中，該至少一些該等導電跡線吸收來自對應的該等銲錫凸塊且起因於該半導體晶粒與該等銲錫凸塊所附接之基板的熱膨脹係數不匹配所產生的應力。
  5. 如申請專利範圍第1項所述之半導體晶粒，其中，該至少一些該等導電跡線包括電源跡線、接地跡線、以及信號跡線之其中一者。
  6. 如申請專利範圍第1項所述之半導體晶粒，其中，各該應力緩衝區具有大於或等於該經劃線的之頂部表面之平均半徑RUBM之半徑Rarea的圓形區域。
  7. 如申請專利範圍第1項所述之半導體晶粒，其中，內切於各該凸塊銲墊之圓形的直徑係大約50微米。
  8. 如申請專利範圍第7項所述之半導體晶粒，其中，內切於各該UBM之頂部表面之圓形的直徑係介於80微米，而內切於各該UBM之底部接觸表面之圓形的直徑係大約46微米。
  9. 如申請專利範圍第8項所述之半導體晶粒，其中，各該導電跡線之寬度係大約12微米。
  10. 如申請專利範圍第4項所述之半導體晶粒，其中，該晶粒係利用覆晶附接而附接至該基板。
  11. 如申請專利範圍第1項所述之半導體晶粒，其中，該半導體晶粒係DRAM、SRAM、EEPROM、快閃記憶體、圖形處理器、一般目的處理器、以及DSP之其中一者。
  12. 一種半導體晶粒，包括：i)至少一個積體電路，係形成於一個表面上，以及連接至該至少一個積體電路之複數個輸入/輸出(I/O)墊；ii)路由層，包括：介電層，係形成於該晶粒之該一個表面上；以及複數個導電跡線，係形成於該介電層上，各該導電跡線延伸於該等I/O墊其中一者與複數個形成於該介電層上之凸塊銲墊其中一者之間；iii)複數個凸塊底層金屬(UBMs)，係個別形成於相應之該等凸塊銲墊其中一者之上；以及iv)複數個銲錫凸塊，係形成於該等UBM塊銲墊上，用於將該積體電路電性互連至基板，其中，形成於該凸塊銲墊上之劃線相應之凸塊底層金屬UBM的圓形應力緩衝區中包含有至少一個該等凸塊銲墊，至少一些該等導電跡線通過該圓形應力緩衝區而未接觸該圓形劃線區域所包含之該凸塊銲墊，以機械性加強靠近該所包含之凸塊銲墊的路由層，其中，除了被該凸塊銲墊佔據的區域，該至少一個的該等導電跡線佔據該應力緩衝區30%至100%之間。
  13. 如申請專利範圍第12項所述之半導體晶粒，其中，如同凸塊銲墊具有與該應力緩衝區相同的區域，各該應力 緩衝區提供實質上相同的應力保護。
  14. 如申請專利範圍第12項所述之半導體晶粒，其中，圓形劃線區域中所包含之該至少一個凸塊銲墊的形狀係六角形、八角形、以及多邊形之其中一者。
  15. 如申請專利範圍第12項所述之半導體晶粒，復包括形成於該UBM頂部之銲錫凸塊。
  16. 如申請專利範圍第15項所述之半導體晶粒，其中，該等銲錫凸塊之其中一者係附接至該UBM之該頂部表面，且該UBM之小於該頂部表面之底部接觸表面係與該至少一個凸塊銲墊實體連通。
  17. 一種用於半導體晶粒之路由層，該路由層包括：i)複數個凸塊銲墊，係用於利用凸塊底層金屬(UBMs)附接銲錫凸塊；ii)複數個導電跡線，係互連相應之該等凸塊銲墊以及形成於晶粒上之積體電路之複數個輸入/輸出(I/O)墊；以及應力緩衝區，劃線相應之UBM且包含有該等銲錫凸塊，各該應力緩衝區具有至少一個該等導電跡線係通過而未接觸該凸塊銲墊或該經劃線的UBM，以機械性加強靠近該經劃線的UBM的該路由層，其中，除了被該凸塊銲墊佔據的區域，該至少一個的該等導電跡線佔據該應力緩衝區30%至100%之間。
  18. 如申請專利範圍第17項所述之路由層，其中，如同凸塊銲墊具有與該應力緩衝區相同的區域，個該應力緩衝 區提供實質上相同的應力保護。
  19. 如申請專利範圍第17項所述之路由層，其中，各該凸塊銲墊的形狀係多邊形、圓形、以及矩形之其中一者。
  20. 如申請專利範圍第17項所述之路由層，其中，各該複數個導電跡線包括銅、鋁、金、鉛、錫、銀、鉍、銻、鋅、鎳、鋯、鎂、銦、碲、及鎵之至少一者。
  21. 如申請專利範圍第17項所述之路由層，復包括介電層，其中，該複數個導電跡線係形成於該介電層上。
  22. 一種半導體晶粒，包括專利範圍第17項所述之該路由層。
  23. 一種半導體晶粒之製造方法，該半導體晶粒具有互連至複數個輸入/輸出(I/O)墊之積體電路(IC)，該方法包括：i)於介電層上形成複數個導電跡線，該等導電跡線係互連多個凸塊銲墊之相應者以及該等輸入/輸出(I/O)墊，其中，各該凸塊銲墊係應力緩衝區之部分，該應力緩衝區係劃線形成於該凸塊銲墊之頂部的凸塊底層金屬(UBM)，至少一個該等導電跡線通過該等凸塊銲墊之靠近的一者之該應力緩衝區，以便加強靠近該等凸塊銲墊之該一者之該介電層，除了被該凸塊銲墊佔據的區域，該至少一個的該等導電跡線佔據該應力緩衝區30%至100%之間；以及ii)將複數個該等銲錫凸塊附接至相應之該等凸塊銲墊。
  24. 如申請專利範圍第23項所述之方法，其中，如同凸塊銲墊具有與該應力緩衝區相同的區域，各該應力緩衝區提供實質上相同的應力保護。
  25. 如申請專利範圍第23項所述之方法，其中，附接該複數個銲錫凸塊係包括於各該凸塊銲墊上形成凸塊底層金屬(UBM)，並且於相應之該等UBM上接置各該銲錫凸塊。
  26. 如申請專利範圍第25項所述之方法，復包括於該介電層上方形成鈍化層。
  27. 如申請專利範圍第26項所述之方法，復包括於該鈍化層中形成開口，以曝露出該等凸塊銲墊，以形成該等UBM。
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