CN102668069B - 用于在半导体裸片中缓解应力的布线层 - Google Patents

用于在半导体裸片中缓解应力的布线层 Download PDF

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CN102668069B
CN102668069B CN201080047812.1A CN201080047812A CN102668069B CN 102668069 B CN102668069 B CN 102668069B CN 201080047812 A CN201080047812 A CN 201080047812A CN 102668069 B CN102668069 B CN 102668069B
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pad
lower section
projection
spraying plating
metal spraying
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CN102668069A (zh
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罗登·托帕西欧
加布里埃尔·翁
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ATI Technologies ULC
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ATI Technologies ULC
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Abstract

本发明公开了用于半导体裸片的布线层。所述布线层包括用于附着焊料突起的焊盘、与具有集成电路的裸片的突起焊盘接合的接合焊盘、以及使接合焊盘与焊盘互连的轨迹。所述布线层形成于介电材料层上。所述布线层包括至少部分围绕一些焊盘的导电轨迹以便吸收来自附着于所述焊盘上的焊料突起的应力。围绕焊盘的部分所述轨迹保护紧邻所述焊料突起的放在下面的介电材料部分，避免应力的影响。

Description

用于在半导体裸片中缓解应力的布线层
技术领域
本发明总体上涉及半导体裸片，尤其是涉及用于半导体裸片(die)的布线层设计。
背景技术
现代半导体封装通过在半导体晶片上形成若干集成电路来制造。所述晶片通常被切割(dice)——切分为单独的片——每一片都被称为裸片。每一片裸片在表面上包括一或更多集成电路。该表面(往往被称为“有源表面”)包括被称为输入-输出(I/O)焊盘的许多信号接口接点。
裸片通常利用载体衬底(carriersubstrate)进行封装，载体衬底包括适用于连接到外部电路板上的焊球(solderball)。载体衬底通常包括核心和形成于所述核心的任一侧上的一或多个增强层(builduplayer)。每个增强层具有形成于介电材料层上的金属喷镀(metallization)或轨迹(trace)。载体衬底包括用于与裸片的I/O焊盘电气互连的接合焊盘(bond-pad)。所述衬底上的轨迹(trace)被用来使各接合焊盘与其对应焊球互连。
各种接合技术可用来在裸片上的I/O焊盘和衬底上的接合焊盘之间形成可靠的电气连接。最受欢迎的技术中的两种是引线接合技术和覆晶组装技术。
在引线接合技术中，裸片被放置在载体衬底上，其有源表面背向载体衬底。然后引线一端被接合到裸片上的I/O焊盘，另一端被接合到衬底上的对应接合焊盘。
然而，在覆晶组装技术中，当连接裸片时，裸片的有源表面面向载体衬底。在连接之前，被称为焊料突起(solderbump)的少量焊料被沉积于各个I/O焊盘上。然后，焊料突起被熔化以使裸片上的各个I/O焊盘与衬底上的对应接合焊盘互连。
裸片上的I/O焊盘可被设置在该裸片的有源表面上的任何地方。例如，在一些裸片中，I/O焊盘可遍布整个有源表面而在另一些裸片中，I/O焊盘可被限制在裸片的外围边界附近。在这两种情况下，裸片上的I/O焊盘通常都不与其最终要连接的衬底上的接合焊盘对齐。I/O焊盘也可能互相靠得太近而不能在覆晶组装过程中形成所需要的适当的焊料突起。因此，有利的做法通常是重新分配(redistribute)这些原I/O焊盘到更适合焊料突起的形成的新的焊盘位置(称为突起焊盘)。然后，所述突起焊盘可与衬底上的接合焊盘对齐并利用焊料突起连接。为了重新分配原I/O焊盘到适合覆晶接合的新的突起焊盘位置，通常在硅晶片上或单独的裸片上的有源表面上形成布线层或重新分配层(RDL)。
布线层(routinglayer)通常形成于薄的介电层上，在所述介电层上，导电轨迹(trace)被形成来使各个I/O焊盘与对应突起焊盘互连。除了在它们互连的I/O焊盘处外，所述轨迹通过介电材料与裸片的更下面的层绝缘。布线层允许I/O驱动器被放置在裸片中的任何地方，却不必考虑衬底接合焊盘的位置。然后，I/O驱动器可在裸片中自由放置，因为重新分配层会将形成于突起焊盘上的焊料突起与衬底上的接合焊盘对齐。布线层的使用还简化了衬底的形成，且往往导致更少的增强层，这减少了成本。
布线层可包括多层介电材料以及取决于布线需要的相关轨迹。往往在顶部布线层上形成钝化层，以保护金属轨迹避免暴露于空气。所述钝化层中的开口暴露突起焊盘。
通常在暴露的突起焊盘上形成下方突起金属喷镀(UBM)以提供与焊料突起的低电阻电气连接，用于到衬底的连接。通常在突起焊盘的UBM上例如通过焊膏的沉积形成焊料突起。
在覆晶连接过程中，形成于重新分配的突起焊盘上的焊料突起与衬底中的对应接合焊盘对齐，然后再流焊或熔化以形成可靠的电气接点或机械接点。
在将半导体裸片附着到衬底上之后，其焊料突起在操作过程中往往受到机械应力或热应力。各个突起焊盘帮助吸收许多应力，否则，应力会影响布线层中的放在下面的介电层。为了缓冲来自焊料突起的这些应力，各个突起焊盘往往做得至少与其对应的UBM一样大(且往往实质上大于其对应的UBM)。
但是，这是不利的，因为较大的突起焊盘减少了布线层中可用于布置导电轨迹的区域，导致轨迹和突起焊盘的更密集的排布，这会潜在地危及信号完整性。而且必须布置在大突起焊盘的周围的轨迹会需要被制造得更长，这增加了其电阻和电容。轨迹上的增加的电阻和电容往往导致电源轨迹中的电压下降以及信号轨迹中的更长的传播延迟。另外，更新、更小的裸片往往要求远远更小的突起焊盘以增加用于其布线需要的可用区域，且往往使用脆性介电材料。
一种用于减小突起焊盘尺寸的已知方法是在小突起焊盘顶上的大UBM之间使用聚酰亚胺以帮助缓解会影响裸片的介电层的应力。但可惜的是，这增加了封装成本且用脆性介电层可能不能很好地工作。
因此，需要半导体裸片能够增加轨迹的数量却不会危及信号完整性，并保护介电层以防被热应力和机械应力破坏。
发明内容
根据本发明的一个方面，提供了半导体裸片，包括：在半导体晶片的一个表面上形成的集成电路；与所述集成电路互连的多个输入-输出(I/O)焊盘；以及布线层。所述布线层包括：在一个表面上形成的介电层；以及在所述介电层上形成的多个导电轨迹，所述导电轨迹的每一个在所述I/O焊盘中的一个和形成于所述介电层上的多个突起焊盘中的一个之间延伸。所述半导体裸片还包括多个下方突起金属喷镀(UBM)，每一个都具有用于附着多个焊料突起中各自的一个的顶表面；以及小于所述顶表面、在物理上与所述多个突起焊盘中各自的一个接触的底部接触表面。所述导电轨迹中的至少一些在所述UBM的所述顶表面的下方经过紧邻的所述突起焊盘而不接触所述突起焊盘以机械加固紧邻所述UBM的所述布线层。
根据本发明的另一方面，提供了半导体裸片，包括：在一个表面上形成的至少一个集成电路，以及与所述至少一个集成电路连接的多个输入-输出(I/O)焊盘；布线层，其包括在所述裸片的所述表面上形成的介电层，以及在所述介电层上形成的多个导电轨迹，在所述I/O焊盘中的一个和形成于所述介电层上的多个突起焊盘中的一个之间延伸的所述导电轨迹的每一个；以及在所述突起焊盘上形成的多个焊料突起，用于使所述集成电路与衬底电气互连。所述突起焊盘中的至少一个被包含在具有大于或等于在每一个所述突起焊盘上形成的对应的下方突起金属喷镀(UBM)的顶表面的平均半径的半径的圆形限制区域内。所述导电轨迹中的至少一些穿过所述圆形限制区域而不接触所包含的突起焊盘，以机械加固紧邻所述所包含的突起焊盘的所述布线层。
对于本领域的普通技术人员而言，在阅读下面的本发明具体实施方式的描述的基础上，结合附图，本发明的其他方面和特征会变得明白。
附图说明
在只用实施例的方式说明本发明的实施方式的附图中，
图1是用于常规半导体裸片的重新分配I/O焊盘到突起焊盘的常规布线层的俯视图；
图2是常规半导体裸片的纵向剖视图；
图3是图2的常规半导体裸片的一部分的俯视图；
图4是作为本发明实施方式的示例的半导体裸片的一部分的纵向剖视图；
图5是图4中所描绘的示例半导体裸片的一部分的俯视图；
图6是图4的示例半导体裸片的另一纵向剖视图；
图7是描绘图5的示例突起焊盘和图4的常规突起焊盘的相对尺寸的图；
图8是图4的半导体裸片的示例布线层的俯视图；以及
图9是出于与示例突起焊盘比较的目的而绘制的具有与常规突起焊盘的重叠的图8的俯视图。
具体实施方式
图1描绘了常规半导体裸片100的布线层的俯视图。裸片100包括形成其集成电路的一部分的原I/O焊盘114A、114B、114C(单称和统称为I/O焊盘114)和适用于覆晶焊料突起形成的重新分配的突起焊盘104A、104B、104C、104D(单称和统称为突起焊盘104)。导电轨迹122A、122B、122C、122D、122E、122F(单称和统称为导电轨迹122)使I/O焊盘114与对应的突起焊盘104互连。
图2描绘了常规半导体裸片100的一部分的纵向剖视图，包括导电轨迹122、I/O焊盘114和上面形成有焊料突起112的突起焊盘104。I/O焊盘114形成于包括形成在半导体晶片(例如，硅片)上的集成电路的裸片100的较下面的金属层116上。
突起焊盘104提供到所述集成电路的I/O连接点。利用覆晶附着技术，形成于突起焊盘104上的焊料突起112被用来将裸片100附着诸如载体衬底或印刷线路板之类的衬底。
在较下面的金属层116上形成的布线层108包括介电层120和形成于介电层120上的导电轨迹122。介电层120使较下面的金属层116与导电轨迹122绝缘，除了在I/O焊盘114处。导电轨迹122中的每一个使I/O焊盘114与突起焊盘104互连。
在每个突起焊盘104上形成的下方突起金属喷镀(UBM)102为每个焊料突起112提供低电阻附着表面。每个UBM102可具有与焊料突起112联通的顶表面102A以及与突起焊盘104联通的底部接触表面102B。
为了使裸片100与衬底互连，焊料突起112与衬底上的接合焊盘对齐并用热熔化以形成与衬底的电气和机械接合。
在操作过程中，半导体裸片100以电压或电流输入形式消耗电能，且使一部分能量作为热消散。热导致裸片100和裸片100所附着的衬底二者以其各自的热膨胀系数(CTE)膨胀。裸片100的CTE和衬底(裸片100通过焊料突起112与其互连)的CTE通常是不同的。CTE值的失配引起焊料突起112以及诸如UBM102和布线层108中的介电材料120等其他邻近结构上的热应力。除了热应力，紧邻焊料突起112的结构还可受到由衬底或裸片100的弯曲和/或振动导致的机械应力。
热应力和/或机械应力会潜在损害布线层108(具体地，介电材料120)以及较下面的层116中所用的其他材料。例如，极端低K(ELK)介电材料(具有K＜3.0的介电常数值)可被用于较下面的层116中。但是，ELK材料往往是脆性的，在机械应力或热应力下会弯曲、破裂或破碎。不一定ELK的介电材料也会因暴露于热应力和机械应力而被损坏。
为了减轻应力对布线层108的介电材料120以及较下面的层116的影响，突起焊盘104往往做得比UBM102大。大的突起焊盘帮助吸收应力，否则，应力会影响下面的介电材料。
图3中图示了UBM102和突起焊盘104的表面的相对尺寸，图3描绘了沿着图2中的线III-III截取的常规裸片100的一部分的俯视图。如图所示，常规突起焊盘104大于UBM102从而帮助吸收来自对应焊料突起(图3中未示出)的机械应力和热应力，从而防止对介电材料120和较下面的层116的破坏。
可惜的是，更大的突起焊盘104减少了可用于布线层108中的布线导电轨迹122的可用区域。另外，为了围绕更大的焊盘104布线，一些轨迹需要很长。如前所述，长轨迹促成了增加的电阻和电容，反过来又导致沿着电源轨迹的电压下降，以及穿过信号轨迹的增加的传播延迟。此外，用45nm或更低的工艺技术形成的集成电路通常在尺寸上是小的，且往往利用ELK介电材料进行封装。诸如突起焊盘104之类的大突起焊盘会不适用于这样的设备。
因此，本发明的示范性实施方式会利用适于与ELK介电材料一并使用的较小尺寸的突起焊盘。较小的焊盘尺寸可释放空间，容许给定区域内的电源和接地轨迹的增大的密度。反之，新释放的空间允许平行轨迹之间的增大的间隔，减少串扰。可以理解，降低串扰和/或增加电源和接地轨迹有助于改善信号完整性并提高性能。
因此，图4描绘了作为本发明实施方式的示例的半导体裸片200的纵向剖视图。图5描绘了图4中的示例裸片200的一部分的俯视图。如图所示，示例裸片200包括形成于半导体晶片(例如，硅片或镓砷化物晶片)上的集成电路(IC)和与所述IC互连的例如可由铝(Al)或铜(Cu)制成的I/O焊盘214。
裸片200还可包括由一或多个介电材料层220组成的布线层208，每个介电材料层具有形成于其上的导电轨迹222A、222B、222C(单称和统称为导电轨迹222)层。裸片200可包括诸如钝化层206之类的覆盖保护层以遮蔽导电轨迹222避免暴露于空气，从而防止氧化。导电轨迹222可使I/O焊盘214与对应的单个(ones)突起焊盘204互连。
可形成多个焊料突起212，每个突起焊盘204上一个焊料突起。焊料突起212可被用于利用覆晶附着方法将裸片200附着于衬底。焊料突起212可与所述衬底上的对应接合焊盘对齐，并再流焊以形成电气和机械接合。覆晶附着方法对本领域普通技术人员来说是公知的。
每个导电轨迹222可使I/O焊盘214在一端连接到对应的突起焊盘204(从而到焊料突起212)。突起焊盘204合宜地提供与裸片200上的集成电路的I/O互连。
可以理解，有利的做法是设计I/O焊盘214及相关I/O驱动电路的布局而不考虑突起焊盘的布局，以免干扰其他优化。I/O焊盘204可以是区域焊盘(areapad)、多行焊盘(multi-rowpad)、周界焊盘(perimeterpad)，等等。不考虑I/O焊盘204的位置，布线层208可被用于重新分配I/O焊盘214到突起焊盘204以使焊料突起212与衬底上的各自的接合焊盘对齐。
导电轨迹222通常由铜或铝制成，但也可由诸如金、铅、锡、银、铋、锑、锌、镍、锆、镁、铟、碲、镓等其他金属制成。还可使用一或多种上述金属的合金。
可在每个突起焊盘204上形成下方突起金属喷镀(UBM)202以给焊料突起212提供低电阻安装面。例如，在一实施方式中，可在每个UBM202上沉积焊膏以形成各自的焊料突起212。
每个UBM202可具有与对应焊料突起212联通的顶表面202A以及在下面与各自的突起焊盘204联通的底部接触表面202B。UBM202在其顶表面202A和其底部接触表面202B之间可包括数个子层(未图示)，例如粘合子层、扩散阻挡子层、焊料可湿子层以及可选地氧化阻隔子层。底部接触表面202B物理上与突起焊盘204接触。
UBM202的形成可包括清洁、绝缘氧化物的去除以及沉积冶金，从而制造与焊料突起212的良好的电气和机械连接。焊料可湿子层为熔化的焊料提供易湿表面，用于焊料突起212与下面的突起焊盘204的良好的接合。焊料突起212(类似图2中的焊料突起112)可利用热进行熔化以在半导体裸片200和衬底或电路板之间形成电气和机械互连。
如下面将要描述的，裸片200的突起焊盘204小于裸片100的突起焊盘104。因此，布线层208为布线导电轨迹222提供了更多的空间或额外的间隔，可导致更短的长度。更短的轨迹是有利的，因为这导致降低的轨迹电阻和电容。降低的电阻和电容值转而导致穿过电源轨迹的减少的电压降，以及沿着信号轨迹的较少的信号传播迟延。
图6描绘了沿着图5中的线VI-VI截取的半导体裸片200的纵向剖视图。如图6中所描绘的，示例突起焊盘204小于其对应UBM202。示例突起焊盘204通过金属轨迹222与I/O焊盘214互连。
比较图2与图4(或者图3与图5)，可以发现，较小的突起焊盘204允许在与突起焊盘104所占用的区域大约相同的区域内布置若干导电轨迹222A、222B和222C(单称和统称为导电轨迹222)。突起焊盘104与突起焊盘204的相对尺寸进一步被描绘于图7和图9中。
现在，为了减轻可由突起焊盘204的尺寸减小导致的应力对布线层208中的介电材料的影响，轨迹222中的一或多个可以有助于吸收机械和/或热机械应力的方法被布置在突起焊盘204的附近。
具体地，在图4-6中所描绘的具体实施方式中，导电轨迹222A、222B、222C经过紧邻的突起焊盘204以机械加固紧邻UBM202的布线层208。围绕或经过紧邻的突起焊盘204的部分导电轨迹222A、222B可在UBM202的顶表面202A的下方却不在与突起焊盘204在物理上接触的底部接触表面202B的下方。从而导电轨迹222A、222B加固了紧邻UBM202的布线层208。因此经过紧邻的突起焊盘204的部分导电轨迹222A、222B可吸收来自附着到突起焊盘204的焊料突起的机械和/或热应力，以保护紧邻焊料突起212放在下面的介电材料220。
如图5中所描绘的，每个突起焊盘204可被包含在具有不小于UBM顶表面202A的平均半径RUBM的半径Rarea的圆形限制区域224(circumscribingarea)内(即，Rarea≥RUBM，其中RUBM＝D2/2)。如后面将要描述的，至少一些导电轨迹(例如，轨迹222A、222B)会穿过圆形限制区域224却不直接接触包含在其中的突起焊盘以机械加固紧邻所包含的突起焊盘的布线层208。
圆形限制区域224内的突起焊盘204及部分的导电轨迹222A、222B、222C可被视为“虚拟焊盘”，其具有与常规突起焊盘104一样大的有效尺寸(从应力吸收的立场)。限制区域224可有效地缓冲来自对应焊料突起(形成于受限的突起焊盘204上的UBM表面202A上)的应力，从而保护下面的介电材料免遭应力引起的损坏。当然在其他实施方式中，圆形限制区域224在尺寸上可以与常规突起焊盘104相同、大于甚或微小于常规突起焊盘104。
为了比较不同形状的焊盘、UBM和限制区域的相对尺寸，给定形状的内切圆的直径可被用来作为该形状的尺寸的代表。
在图2中，内切于UBM102的顶表面102A中的圆的直径可以是大约80μm(即d2≈80μm)。换句话说，UBM顶表面102A的内径是大约80μm/2＝40μm。内切于突起焊盘104中的圆的直径可以是大约92μm(即d3≈92μm)；而内切于开口110中(或底部接触表面102B中)的圆的直径(表示为d1)可以是大约60μm(即d1≈60μm)。
然而，在图4中，在一实施方式中，UBM202的顶表面202A(中的内切圆)的直径(表示为D2)可以是大约80μm(即D2≈80μm)。突起焊盘204(中的内切圆)的直径可以是大约50μm(即图4中的D3≈50μm)，而开口210(中的内切圆)的直径(图4中表示为D1)可以是大约46μm(即D1≈46μm)。每一个导电轨迹222的宽度(表示为W1)可以是大约12μm。本领域技术人员会理解的是，上述附图只是示例，在其他实施方式中可使用更大或更小的尺寸。
同样，UBM表面202A、202B、突起焊盘204和开口210的形状既不需要一致也不必定是八边形。相反地，UBM202、突起焊盘204和钝化开口210可以呈现任何形状且可以具有可变的尺寸。其可以例如具有其他多边形形状，例如六边形或矩形。其还可以呈现其他形状：其可以是圆形、椭圆形、不规则形状或合适尺寸的任何任意形状。
导电轨迹222A、222B、222C在示例布线层208中围绕或环绕突起焊盘204的排布是有利的。除了在给定区域内容许增多数量的信号布线轨迹，所述排布以圆形限制区域224的形式创建了应力缓冲区域，可有效地提供与远远较大的常规突起焊盘104一样多的对抗应力的保护。可以理解，应力被紧邻突起焊盘204的部分导电轨迹222A、222B、222C(在区域224中)吸收，否则，应力会损坏布线层208的放在下面的介电材料。
图7描绘了示例突起焊盘204和常规突起焊盘104的相对尺寸，以及代表各种应力缓冲区域的轮廓示例圆形限制区域。区域702对应于较大的常规突起焊盘104和同中心设置的较小的示例突起焊盘204之间的表面面积上的差。在常规突起焊盘104中，区域702(成为了突起焊盘104的一部分)不能用于布线。在使用突起焊盘204的示例实施方式中，区域702的一部分可合宜地用于布置轨迹。
然而，相反地，在诸如突起焊盘104之类的常规焊盘中，全部区域702帮助吸收应力，而在本发明的示例实施方式中，只有被轨迹占用的部分区域702吸收应力以加固布线层208。为了增强区域702内的应力吸收，示例实施方式可增加被导电轨迹覆盖的区域702的百分比。
在示例布线层208中，应力缓冲区域(应力吸收区域)不必局限于区域702。相反地，其可以小于或大于区域702。因此，应力缓冲区域可由包含突起焊盘204以及部分轨迹的第一圆形限制区域224′限定。如图7中所描绘的，圆形限制区域224′在尺寸上可以小于突起焊盘104。然而，可以利用围绕突起焊盘204的越来越多的轨迹来形成大于焊盘104的应力缓冲区域以加固布线层208。这通过图7中所描绘的第二圆形限制区域224″示出。可以理解的是，增加给定圆形限制区域(例如，区域224″)的被其所包含的突起焊盘和部分导电轨迹覆盖的表面面积的比例可为紧邻所包含的突起焊盘的布线层208提供更强的机械加固。在一些实施方式中，被导电轨迹覆盖的区域702的比例可在大约30％到100％之间。
图8描绘了示例半导体裸片200的示例布线层208的俯视图。布线层208包括集成电路的原I/O焊盘214A、214B、214C(单称和统称为I/O焊盘214)和适用于覆晶焊料突起形成的重新分配的示例突起焊盘204A、204B、204C、204D(单称和统称为突起焊盘204)。导电轨迹222D、222E、222F、222G、222H、222I、222J、222K、222L(单称和统称为导电轨迹222)被用来使I/O焊盘与对应的突起焊盘(未全部图示)互连。
在图1中，在突起焊盘104A和104D之间只布置了5个信号轨迹。然而在图8中，在突起焊盘204A和突起焊盘204D之间可容纳至少10个信号、接地及电源轨迹(即222D、222E、222F、222G、222H、222I、222J、222K、222L和222M)。可以注意到，图8的布线层在突起焊盘之间包括更多信号轨迹，却不会使分隔相邻轨迹的间隔变窄，这可促进改善的信号密度。
在图8中，所描绘的用于布线层208的导电图包括使用于附着第一焊料突起的第一突起焊盘204A与I/O焊盘214A互连的第一导电轨迹222A′；以及使用于附着第二焊料突起的第二突起焊盘204B与第二I/O焊盘214B互连的第二导电轨迹222B′。I/O焊盘214可具有任何形状且可被放置于裸片200上的任何地方。
图9也描绘了示例半导体裸片200的示例布线层208的俯视图，具有显示来说明相对尺寸和示例布线层208所能达到的布线密度的假定的常规突起焊盘104A′、104B′、104C′、104D′(单独地，统称为焊盘轮廓104′)的轮廓。
如所描绘的，部分的导电轨迹222B′、222C′(例如，焊盘轮廓104A′内的部分)至少部分地围绕或经过紧邻的突起焊盘204A。从而突起焊盘204A附近的部分导电轨迹222A′、222B′、222C′吸收来自附着到突起焊盘204A的焊料突起的应力。所描绘的排布实际上形成了包围焊盘204A的“虚拟焊盘”或限制区域(例如，轮廓104A′或其中的内切圆)，以保护紧邻焊盘204A的介电层避免因热应力和机械应力引起的潜在损害。
图8-9还描绘了额外的焊盘204C和204B，每一个均与各自的独立的轨迹互连。如所描绘的，虽然导电轨迹222B′、222C′不直接与突起焊盘204A互连，但是部分的导电轨迹222B′、222C′帮助保护紧邻焊盘204A的介电层。
有利地，不需要昂贵的额外步骤来制造半导体裸片200。例如，制造诸如裸片200之类的半导体裸片的一种方法可包括制备具有包括形成于有源表面上的成组I/O焊盘的至少一个集成电路(IC)的晶片。在所述晶片上可形成包括介电材料层的诸如布线层208之类的布线层。所述布线层可具有形成于其上的至少一个导电轨迹，使第一焊盘(例如突起焊盘204)与第一I/O焊盘互连。所述布线层还可包括第二突起焊盘、第二I/O焊盘和使所述第二突起焊盘与所述第二I/O焊盘互连的第二导电轨迹。所述第二导电轨迹(例如轨迹222B′)可被形成来经过紧邻的第一突起焊盘(例如，图8中的突起焊盘204A)且还可部分围绕所述第一突起焊盘。从而所述第二导电轨迹可缓冲来自附着到所述第一突起焊盘的焊料突起的应力，以保护紧邻所述焊料突起的放在下面的介电材料，避免所述应力的影响。
还可形成钝化层。所述制造方法可进一步涉及在所述钝化层上形成开口以暴露突起焊盘以及在每个突起焊盘上形成下方突起金属喷镀(UBM)焊盘以将焊料突起安装、沉积或附着到所述突起焊盘上。
所述方法可进一步涉及利用覆晶附着技术将裸片200附着到载体衬底上。覆晶附着技术对本领域普通技术人员而言是公知的且例如在由纽约的McGrawHill出版社于2005年出版的CharlesA.Harper的《ElectronicPackagingandInterconnection(电子封装与互连)》第四版中进行了讨论，因此将其内容引入作为参考。
有利地，用于如图8-9中所描绘的轨迹222的布线图容许提高布线密度同时仍然吸收来自焊料突起的大部分应力，否则，应力会消极地影响与较小的裸片一起使用的越来越多的脆性介电材料。与较大的突起焊盘相比，较小的突起焊盘204允许用于信号、电源/接地的更多布线轨迹222。另外，较小的突起焊盘204对信号传送来说是较小电容性的。
电源和接地轨迹的有效电阻可通过增加布线层上的电源/接地轨迹的数量来降低，这有利地导致了更高效的电源使用情况。而且，作为本发明实施方式的示例的半导体裸片容许突起焊盘的形状不必与形成于其上的UBM焊盘的形状共形。
所述实施方式可合宜地避免与在UBM和布线层之间增加聚酰亚胺缓冲相关的成本。
可以理解的是，为清楚起见，在图4-5中只描绘了一个介电材料层220和对应的一层导电轨迹222。但是，本领域技术人员可容易地理解，在其他实施方式中，可排布通过布线层208中的介电材料层彼此隔绝的若干层轨迹。
在其他实施方式中，在裸片200的布线层208中只有一些突起焊盘可被经过紧邻的突起焊盘的导电轨迹围绕。可以有一些其他突起焊盘不一定有导电轨迹经过其各自的UBM附近，以机械加固布线层208。除了小于其对应UBM的上表面的示例突起焊盘204之外，还可以有大于其对应UBM的其他突起焊盘(类似突起焊盘104)。
本发明的实施方式可被用于各种各样的应用，包括DRAM、SRAM、EEPROM、闪存、图形处理器、通用处理器、DSP以及各种标准的模拟、数字和混合信号电路封装的制造。
当然，上述实施方式只是旨在说明而不是限制。实施本发明的所述实施方式容许形式、部件排布、操作细节和顺序上的许多修改。更确切些，本发明旨在包括由权利要求书所限定的在其范围内的所有这样的修改方式。

Claims (28)

1.半导体裸片，包括：
i)在半导体晶片的一个表面上形成的集成电路；
ii)与所述集成电路互连的多个输入-输出焊盘；
iii)布线层，其包括：在所述一个表面上形成的介电层；以及在所述介电层上形成的多个导电轨迹，所述导电轨迹的每一个在所述输入-输出焊盘中的一个和形成于所述介电层上的多个突起焊盘中的一个之间延伸；
iv)多个下方突起金属喷镀，每一个都包括用于附着多个焊料突起中各自的一个的顶表面；以及小于所述顶表面、在物理上与所述多个突起焊盘中各自的一个物理接触的底部接触表面；
其中所述布线层包括一个或多个应力缓冲区域，每个应力缓冲区域都对下方突起金属喷镀加以限制并且包括所述导电轨迹中的至少一个，所述至少一个导电轨迹在受限制的所述下方突起金属喷镀的下方经过而不与受限制的所述下方突起金属喷镀电气接触但却与另一个所述下方突起金属喷镀电气接触，其中所述应力缓冲区域的30％到100％被不与受限制的所述下方突起金属喷镀电气接触但却与另一个所述下方突起金属喷镀电气接触的所述导电轨迹所占用。
2.如权利要求1所述的半导体裸片，其中每个所述应力缓冲区域都提供相当的应力保护，充当具有与所述应力缓冲区域相同面积的突起焊盘。
3.如权利要求1所述的半导体裸片，其中所述布线层包括多层导电轨迹，每一层所述导电轨迹与所述多层导电轨迹中的另一层被至少一个介电层分隔。
4.如权利要求1所述的半导体裸片，其中所述导电轨迹中的所述至少一些吸收来自所述焊料突起中的对应的由所述半导体裸片和连接所述焊料突起的衬底的热膨胀的系数的失配而导致的应力。
5.如权利要求1所述的半导体裸片，其中所述导电轨迹中的所述至少一些包括电源轨迹、接地轨迹和信号轨迹中的一个。
6.如权利要求1所述的半导体裸片，其中每个所述应力缓冲区域为半径Rarea大于或等于受限制的下方突起金属喷镀的顶表面的平均半径RUBM的圆形区域。
7.如权利要求1所述的半导体裸片，其中内切于所述突起焊盘的每一个中的圆的直径是50μm。
8.如权利要求7所述的半导体裸片，其中内切于所述下方突起金属喷镀中的每一个的顶表面中的圆的直径是在80μm之间，且内切于所述下方突起金属喷镀中的所述每一个的底部接触表面中的圆的直径是46μm。
9.如权利要求8所述的半导体裸片，其中所述导电轨迹中的每一个的宽度是12μm。
10.如权利要求1所述的半导体裸片，其中所述裸片利用覆晶附着技术被附着到衬底。
11.如权利要求1所述的半导体裸片，其中所述半导体裸片是下面中的一个：DRAM、SRAM、EEPROM、闪存、图形处理器、通用处理器和DSP。
12.半导体裸片，包括：
i)在一个表面上形成的至少一个集成电路，以及与所述至少一个集成电路连接的多个输入-输出焊盘；
ii)布线层，其包括在所述裸片的所述表面上形成的介电层，以及在所述介电层上形成的多个导电轨迹，所述导电轨迹的每一个在所述输入-输出焊盘中的一个和形成于所述介电层上的多个突起焊盘中的一个之间延伸；
iii)多个下方突起金属喷镀，每一个都形成在所述突起焊盘中的对应一个上；
iv)在所述突起焊盘上形成的多个焊料突起，用于使所述集成电路与衬底电气互连；
其中所述突起焊盘中的至少一个被包含在对形成在所述突起焊盘上的对应的下方突起金属喷镀加以限制的圆形应力缓冲区域内，所述导电轨迹中的至少一些穿过所述应力缓冲区域而不接触受限制的突起焊盘但却接触所述突起焊盘中的其他突起焊盘，其中所述应力缓冲区域的30％到100％被不与受限制的所述下方突起金属喷镀电气接触但却与另一个所述下方突起金属喷镀电气接触的所述导电轨迹中的至少一个所占用。
13.如权利要求12所述的半导体裸片，其中每个所述应力缓冲区域都提供相当的应力保护，充当具有与所述应力缓冲区域相同面积的突起焊盘。
14.如权利要求12所述的半导体裸片，其中包含在圆形限制区域内的所述至少一个突起焊盘的形状是多边形。
15.如权利要求12所述的半导体裸片，其中包含在圆形限制区域内的所述至少一个突起焊盘的形状是六边形和八边形中的一种。
16.如权利要求12所述的半导体裸片，进一步包括在所述下方突起金属喷镀顶上形成的焊料突起。
17.如权利要求16所述的半导体裸片，其中所述焊料突起中的一个被附着到所述下方突起金属喷镀的顶表面，且所述下方突起金属喷镀的小于所述顶表面的底部接触表面在物理上与所述至少一个突起焊盘接触。
18.用于半导体裸片的布线层，所述布线层包括：
i)用于利用下方突起金属喷镀附着焊料突起的多个突起焊盘；
ii)介电层和使对应的所述突起焊盘与形成于裸片上的集成电路的多个输入-输出焊盘互连的多个导电轨迹；
iii)一个或多个应力缓冲区域，每个应力缓冲区域都对下方突起金属喷镀加以限制并且包括所述导电轨迹中的至少一个，所述至少一个导电轨迹在受限制的所述下方突起金属喷镀的下方经过而不与受限制的所述下方突起金属喷镀电气接触但却与另一个所述下方突起金属喷镀电气接触，
其中所述应力缓冲区域的30％到100％被不与受限制的所述下方突起金属喷镀电气接触但却与另一个所述下方突起金属喷镀电气接触的所述导电轨迹所占用。
19.如权利要求18所述的布线层，其中所述突起焊盘中的每一个的形状是多边形和圆形中的一种。
20.如权利要求18所述的布线层，其中所述突起焊盘中的每一个的形状是矩形。
21.如权利要求18所述的布线层，其中所述多个导电轨迹中的每一个包括至少下面的一者：铜、铝、金、铅、锡、银、铋、锑、锌、镍、锆、镁、铟、碲和镓。
22.如权利要求18所述的布线层，进一步包括介电层，其中所述多个导电轨迹形成于所述介电层上。
23.半导体裸片，其包括如权利要求18所述的布线层。
24.制造用于具有集成电路的裸片的半导体裸片的方法，所述集成电路与多个输入-输出焊盘互连，所述方法包括：
i)在介电层上形成多个导电轨迹，所述轨迹使对应的多个突起焊盘与所述输入-输出焊盘互连，其中每个所述突起焊盘都是对形成在所述突起焊盘顶上的下方突起金属喷镀加以限制的应力缓冲区域的一部分，所述导电轨迹中的至少一个经过所述应力缓冲区域不与受限制的所述下方突起金属喷镀电气接触但却与另一个所述下方突起金属喷镀电气接触，所述导电轨迹中的至少一个占用所述应力缓冲区域的30％到100％；以及
ii)将多个焊料突起附着到对应的所述突起焊盘。
25.如权利要求24所述的方法，其中每个所述应力缓冲区域都提供相当的应力保护，充当具有与所述应力缓冲区域相同面积的突起焊盘。
26.如权利要求24所述的方法，其中所述附着所述多个焊料突起包括在所述突起焊盘中的每一个上形成下方突起金属喷镀，并将所述焊料突起中的每一个安装到对应的所述下方突起金属喷镀上。
27.如权利要求26所述的方法，进一步包括在所述介电层上方形成钝化层。
28.如权利要求27所述的方法，进一步包括在所述钝化层中形成开口以暴露所述突起焊盘，以形成所述下方突起金属喷镀。
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US8642463B2 (en) 2014-02-04
US20110095415A1 (en) 2011-04-28
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