TWI515871B - 導線架 - Google Patents

導線架 Download PDF

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Publication number
TWI515871B
TWI515871B TW101123783A TW101123783A TWI515871B TW I515871 B TWI515871 B TW I515871B TW 101123783 A TW101123783 A TW 101123783A TW 101123783 A TW101123783 A TW 101123783A TW I515871 B TWI515871 B TW I515871B
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TW
Taiwan
Prior art keywords
semiconductor
lead frame
semiconductor element
lead
thickness
Prior art date
Application number
TW101123783A
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English (en)
Other versions
TW201246512A (en
Inventor
竹本康男
佐藤哲也
渡邊勝好
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東芝股份有限公司
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Publication of TW201246512A publication Critical patent/TW201246512A/zh
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Publication of TWI515871B publication Critical patent/TWI515871B/zh

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    • H01L23/495—Lead-frames or other flat leads
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Description

導線架
本發明係關於包含複數半導體元件之半導體封裝。
本申請案依據2007年4月27日申請之日本專利申請案2007-119798號之優先權之利益。故主張其優先權之利益。前述日本專利申請案之內容全部併入本文中作為參照文獻。
為實現半導體裝置之小型化及高密度安裝化，在1個封裝內積層複數半導體元件而予以密封之半導體封裝已邁入實用化。以半導體封裝之低廉化等為優先之情形，使用廉價之導線架作為裝載半導體元件之電路基材。在使用導線架之半導體封裝(TSOP等)中，複數半導體元件依序被積層於導線架之元件裝載部。複數半導體元件之電極墊分別經由金屬線(接合金屬線)而被電性連接於導線架之導線部。
在導線架之單面裝載半導體元件之情形，為增加半導體元件之裝載數，使用施行壓低加工以便元件裝載部低於導線之導線架。壓低加工會成為導線架之製造成本，進而半導體封裝之製造成本之增加要因。施行壓低加工之導線架具有傾斜部，故可裝載之半導體元件之大小會受到限制。
也有人探討在導線架之兩面分別積層而裝載複數半導體元件(參照日本特開2007-035865號公報)。此情形，會在導 線架之兩面裝載半導體元件之狀態被樹脂模塑，故密封樹脂之填充性會因半導體元件之墊排列或其連帶之導線架之形狀而降低。由此種觀點，最好僅在導線架之單面多層地積層而裝載半導體元件。然而，以往之具有單面積層構造之半導體封裝卻具有起因於壓低加工之製造成本增加及元件大小受到限制等之問題。
在半導體元件裝載於布線基板上之半導體封裝(BGA等)，也進行積層而裝載複數半導體元件。為了對多層地積層之半導體元件施行引線接合，考慮以各元件之電極墊露出之方式將複數半導體元件積層成階梯狀。此情形，隨著半導體元件之積層數增加，對布線基板之半導體元件之佔有面積會增加。因此，可裝載於布線基板之半導體元件之大小會受到限制。
本發明之態樣之半導體封裝之特徵在於包含：導線架，其係包含元件支撐部、及具有內導線與外導線之導線部，由前述元件支撐部至前述內導線呈平坦；第1半導體元件，其係具有形成有第1電極墊之第1電極形成面，使前述第1電極形成面朝向下方，而經由第1接著層接著於前述導線架之下表面；第2半導體元件，其係具有形成有第2電極墊之第2電極形成面，使前述第2電極形成面朝向下方，而經由第2接著層接著於前述第1半導體元件之前述第1電極形成面；第1金屬線，其係電性連接前述內導線與前述第1電極墊，且與前述第1半導體元件連接之端部埋入於前述 第2接著層內；第2金屬線，其係電性連接前述內導線與前述第2電極墊；及樹脂密封部，其將前述第1及第2金屬線與前述第1及第2半導體元件一起密封。
本發明之另一態樣之半導體封裝之特徵在於包含：導線架，其係包含元件支撐部、及具有內導線與外導線之導線部，由前述元件支撐部至前述內導線呈平坦；元件群，其係包含具有形成有電極墊之電極形成面之複數半導體元件之元件群，且前述複數半導體元件係使前述電極形成面朝向下方而經由接著層依序積層於前述導線架之下表面；金屬線，其係電性連接前述內導線與前述複數半導體元件之前述電極墊；及樹脂密封部，其將前述金屬線與前述元件群一起密封；連接在前述元件群內之上層之前述半導體元件之前述金屬線端部埋入前述元件群內之下層之前述半導體元件之前述接著層內。
本發明之又另一態樣之半導體封裝之特徵在於包含：電路基材，其係具有元件裝載部與連接部；第1元件群，其係包含具有沿著外形之一邊排列之電極墊之複數半導體元件之第1元件群，且前述複數半導體元件係以前述電極墊露出之方式，在前述電路基材之前述元件裝載部上積層成階梯狀；第2元件群，其係包含具有沿著外形之一邊排列之電極墊之複數半導體元件之第2元件群，且前述複數半導體元件係以前述電極墊露出之方式，在前述第1元件群上經由間隔物層積層成階梯狀；第1金屬線，其係電性連接前述電路基材之前述連接部與構成前述第1元件群之前 述複數半導體元件之前述電極墊；第2金屬線，其係電性連接前述電路基材之前述連接部與構成前述第2元件群之前述複數半導體元件之前述電極墊；及樹脂密封部，其將前述第1及第2金屬線與前述第1及第2元件群一起密封。
以下，說明有關實施本發明用之型態。
參照圖1至圖8說明有關本發明之第1實施型態之半導體封裝。圖1及圖2係表示第1實施型態之半導體封裝之外觀。圖3及圖4係放大表示圖2之A部。圖5係表示在導線架裝載半導體元件之狀態。圖6及圖7係表示導線架之構成。圖8係表示對積層之半導體元件之金屬線(接合金屬線)之連接狀態。
此等之圖所示之半導體封裝1具備有導線架2作為元件裝載用之電路基材。導線架2如圖6所示，具備有導線部3與元件支撐部4。導線部3具有作為與裝載於導線架2之半導體元件之連接部之內導線5、與作為外部連接端子之外導線6，由複數導線所構成。在圖5及圖6中，雖局部省略外導線6之圖示，但如圖7所示，外導線6係向外方突出。
導線架2具有下表面側之第1主面2a與上面側之第2主面2b。半導體元件7如圖2、圖3及圖4所示，係裝載於導線架2之下表面(第1主面)2a側。圖5至圖7係表示導線架2之下表面2a。圖8表示使半導體封裝1反轉之狀態，即使導線架2之下表面2a朝向上側之狀態。導線架2之下表面及上面係以將外導線6連接於安裝板等之狀態為基準，以與安裝板 表面對向之面為下表面2a，以與安裝板對向之面之相反面為上面2b。
在導線架2之下表面2a，依序積層而裝載著第1半導體元件7A、第2半導體元件7B、第3半導體元件7C及第4半導體元件7D。第1至第4半導體元件7A~7D構成元件群。作為第1至第4半導體元件7A~7D之具體例，可列舉如NAND型快閃記憶體之半導體記憶元件。半導體元件7之裝載數只要複數個(至少2個)即可，並不限定於4個。收納於半導體封裝1之半導體元件7之數可為2個、3個或5個以上。
第1半導體元件7A具有形成第1電極墊8A之電極形成面9A。第1半導體元件7A如圖4所示，係使電極形成面9A朝向下方(朝向導線架2之下表面2a之方向、圖中箭號方向)，經由第1接著層10被接著於導線架2之下表面2a。如後所詳述，內導線5係由配置於半導體元件7之短邊側之外導線6向半導體元件7之墊排列邊(長邊)被引繞。因此，除了元件支撐部4以外，第1半導體元件7A也經由第1接著層10接著於內導線5之一部分。
在第1接著層10，使用一般的接合材料，例如以矽樹脂、聚醯亞胺樹脂、環氧樹脂、丙烯酸樹脂等為主成分之絕緣性接著劑。第1接著層10之厚度最好為10~30 μm之範圍。第1接著層10之厚度不足10 μm時，有不能充分確保導線架2與第1半導體元件7A之間之絕緣性之虞。第1接著層10之厚度超過30 μm時，半導體元件7之積層厚會變厚。
第2至第4半導體元件7B~7D也具有形成第2至第4電極墊 8B、8C、8D之電極形成面9B、9C、9D。第2半導體元件7B係使電極形成面9B朝向下方，經由第2接著層11被接著於第1半導體元件7A之電極形成面9A。第3及第4半導體元件7C、7D係分別使電極形成面9C、9D朝向下方，分別經由第3及第4接著層12、13，使第3半導體元件7C接著於第2半導體元件7B之電極形成面9B，使第4半導體元件7D接著於第3半導體元件7C之電極形成面9C。
第1至第4半導體元件7A~7D具有矩形狀之同一形狀，分別使長邊及短邊一致而被積層。即，以對導線架2之半導體元件7A、7B、7C、7D之佔有面積(積層後之元件佔有面積)成為最小面積(相當於1個半導體元件7之面積)之方式，第1至第4半導體元件7A~7D分別使各邊一致而被積層。藉此，可抑制收容大型之半導體元件7之情形之封裝尺寸之增大。
第1至第4半導體元件7A~7D之電極墊8A~8D係分別經由第1至第4金屬線14A~14D而被電性連接於內導線5。金屬線14使用一般的Au線或Cu線等之金屬細線。金屬線14最好適用可降低環路高度之逆接合而施行連線接合。即，預先在電極墊8上形成金屬凸塊。將金屬線14之一端球連接於內導線5，將他端連接於形成在電極墊8上之金屬凸塊。
第1至第4半導體元件7A~7D係使各邊一致而被積層。因此，連接於第1至第3半導體元件7A~7C之第1至第3金屬線14A~14C分別被配置於下方(在圖8中，為上側)之半導體元 件7所干擾，而有發生短路等缺失之虞。因此，將第1金屬線14A之與第1電極墊8A連接之端部(元件側端部)埋入第2接著層11內。同樣地，將第2及第3金屬線14B、14C之元件側端部分別埋入位於下方之第3及第4接著層12、13內。
在半導體封裝1之製造階段，如圖8所示，第1至第4半導體元件7A~7D被依序積層於導線架之第1主面2a上。因此，第1金屬線14A之元件側端部被埋入位於上側之第2接著層11內。第2及第3金屬線14B、14C之元件側端部也同。半導體封裝1係在由積層第1至第4半導體元件7A~7D之狀態被反轉使用。結果，第1至第3金屬線14A~14C之元件側端部呈現被埋入位於下方之第2~第4接著層11~13內之狀態。
如此，除了最下層之第4半導體元件7D以外，連接於元件群內之上層之半導體元件7A、7B、7C之金屬線14A、14B、14C之端部被埋入位於元件群內之下層之半導體元件7B、7C、7D之接著層11、12、13內。藉此，可防止第1金屬線14A與第2半導體元件7B之接觸、第2金屬線14B與第3半導體元件7C之接觸、第3金屬線14C與第4半導體元件7D之接觸。金屬線14藉著接著層11、12、13之厚度而與半導體元件7分離。第2~第4接著層11、12、13一併具有作為間隔物層之功能。
具有作為間隔物層之功能之第2~第4接著層11~13除了接著功能以外，係由可藉半導體元件7之接著溫度而軟化而將金屬線14取入內部之絕緣樹脂所構成。作為此種絕緣樹 脂，例如，可列舉如丙烯酸樹脂之熱可塑性樹脂、或如環氧樹脂之熱硬化性樹脂。接著層11、12、13之厚度較好為30~100 μm之範圍，更好為50~85 μm之範圍。接著層11、12、13之厚度不足30 μm之情形，有不能抑制金屬線14A與半導體元件7之接觸之虞。接著層11、12、13之厚度超過100 μm時，半導體元件7之積層厚度會變得過厚。
半導體元件7A~7D之厚度未必需要受到限定。連線接合時，位於最下層之第1半導體元件7A之厚度以厚於其他半導體元件7B、7C、7D之厚度為宜。具體上，第1半導體元件7A之厚度與第1接著層10之厚度合計以100 μm以上為宜。但，第1半導體元件7A之厚度過於厚，也僅係使積層厚度變厚而已，與第1接著層10之厚度合計以150 μm以下為宜。
第1半導體元件7A之厚度與第1接著層10之厚度合計不足100 μm時，在連線接合時，有受到傷害之虞。第1半導體元件7A之厚度以80~100 μm之範圍更為理想。其他半導體元件7B、7C、7D在連線接合時，接合傷害可藉位於下方之接著層11、12、13加以緩和，即使薄化此等之厚度，也無受到傷害之虞，反之，在抑制積層厚度之增加上以使其薄化為宜。
第2至第4半導體元件7B~7D之厚度在抑制積層厚度之增加上以不足80 μm為宜，70 μm以下更佳。第2至第4半導體元件7B~7D之厚度之下限值並無特別限定，最好在半導體元件之一般的製造步驟中可製作之範圍內(例如20 μm以 上)使其薄化。第2至第4半導體元件7B~7D之厚度在實用上以50 μm以上為宜。選擇任何厚度之情形，第1半導體元件7A之厚度也以厚於其他半導體元件7B、7C、7D之厚度為宜。
積層而裝載於導線架2之下表面2a之第1至第4半導體元件7A~7D係與內導線5及第1至第4金屬線14A~14D同時被樹脂密封部15所密封。樹脂密封部15使用如一般的環氧樹脂之熱硬化性樹脂。藉此等要素構成單面積層構造之半導體封裝1。第1實施型態之半導體封裝1適合於多層地積層半導體記憶元件以謀求高容量化之半導體記憶裝置。
如上所述，第1至第4半導體元件7A~7D係積層而裝載於導線架2之單面(下表面2a)。因此，為將半導體元件7之積層厚度收容於半導體封裝1之厚度內，使由導線架2之元件支撐部4至內導線5平坦化，而且將元件支撐部4與內導線5形成之平坦部配置於樹脂密封部15之上方側。換言之，以確保導線架2之下側之空間之方式，使導線架2之由樹脂密封部15之突出部(導線之肩部)位於通常之上側。
具體上，如圖3所示，薄化由導線架2之上面2b至樹脂密封部15之上部之厚度(上側樹脂厚度)T1，增厚由導線架2之下表面2a至樹脂密封部15之下部之厚度(下側樹脂厚度)T2。適用此種構成時，不必在導線架2施行壓低加工，而可僅在導線架2之單面(下表面2a)多層地積層而裝載半導體元件7。
例如，導線架2之厚度為125 μm，第1半導體元件7A與 第1接著層10之合計厚度為110 μm(元件厚度85 μm+接著層厚度25 μm)，第2至第4半導體元件7B~7D之各厚度為70 μm，第2至第4接著層11~13之各厚度為60 μm，樹脂密封部15之厚度為1000 μm(1 mm)時，樹脂密封部15之上側樹脂厚度T1為185 μm，下側樹脂厚度T2為690 μm。
採用此種構成時，可將多層地積層之半導體元件7(積層厚度=400 μm)僅裝載於未施行壓低加工之導線架2之單面(下表面2a)。另外，將導線架2之由樹脂密封部15之突出部(導線之肩部)之位置設定於上側時，可增高外導線6之高度。藉此，可增大半導體封裝1安裝於安裝板等之際之外導線6之彈簧性，故可提高半導體封裝1之安裝可靠性，尤其是提高對溫度循環之可靠性(壽命)。
另外，使導線架2之與半導體元件7面對之部分(元件支撐部4與內導線5)平坦化，故與樹脂密封部15之大小相同之情形作比較時，可使可裝載於導線架2之半導體元件7之大小大於對導線架2施行壓低加工之情形。使複數半導體元件7之各邊一致而積層時，也可增大可裝載於導線架2之元件大小。藉此，可施行元件大小較大之半導體元件7之裝載。
其次，說明有關半導體元件7之墊排列構造與導線架2之具體的形狀。第1至第4電極墊8A~8D係分別沿著第1至第4半導體元件7A~7D之外形之一邊，具體上，沿著一方之長邊排列。即，第1至第4半導體元件7A~7D如圖5所示，具有長邊單側墊構造。外導線6係配置成分別由半導體元件7 之短邊突出。外導線6係由半導體封裝1之短邊突出。
因此，導線架2有必要將外導線6配置於兩短邊側，將內導線5之接合部分配置於長邊側。因此，內導線5係由外導線6向與半導體元件7之連接位置(對應於半導體元件7之一方長邊之位置)被引繞。具體上，內導線5係由與位於短邊側之外導線6連接之部分改變90度方向，例如向約45度之方向撓曲2次而向長邊側被引繞。使用此種導線架2時，可將長邊單側墊構造之半導體元件7收容於使外導線6由兩短邊突出之半導體封裝1。
長邊單側墊構造之半導體元件7與短邊兩側墊構造之半導體元件及短邊單側墊構造之半導體元件相比，元件大小難以受到限制，且可增加連接電極數。短邊兩側墊構造雖可簡化導線架2之形狀，但長邊側之元件大小受到限制。短邊單側墊構造與長邊單側墊構造相比，連接電極數受到限制。如此，組合引繞內導線5之導線架2與長邊單側墊構造之半導體元件7時，可將大型而連接電極數多之半導體元件7裝載於導線架2。
內導線5由短邊側向長邊側被引繞，故與半導體元件7之連接部分容易移動。因此，以絕緣帶16固定內導線5之與半導體元件7之連接部分附近(內導線5之一部分)。藉此，提高對內導線5之接合性及導線架2之操作性。又，在2次撓曲內導線5所生之空間，配置有與導線架2之對向之二邊(在此為對向之長邊)之各邊連結之元件支撐部4。藉此，提高導線架2對半導體元件7之支撐性。元件支撐部4係藉設 置貫通孔17而提高對接著層10之濕潤性。
導線架2係由短邊側向長邊側引繞內導線5，而使內導線5之一部分與裝載於導線架2之半導體元件7相對向。在具有此種構造之導線架2之兩面裝載半導體元件時，不能將密封樹脂填充於半導體元件所夾之導線架2之間隙部分。對此，半導體元件7僅裝載於導線架2之單面，故也可將密封樹脂填充於導線架2之間隙部分。藉此，可提供密封可靠性優異之半導體封裝1。
又，圖5之金屬線18係外導線6之線數多於內導線5之線數之情形之分歧用金屬線。例如，相對於半導體元件7之電極(晶片生效電極等)有2個，作為半導體封裝1，需要4個電極之情形，只要能在內導線5使其分岐(施行對複數點之連線接合與引繞)，即無問題。不能如此時，則需要配置繞回用之內導線5，並以金屬線18連接此與增加部分之外導線6。適用此種構造時，可對應於各種之電極配置構造。
其次，參照圖9至圖15說明有關第2實施型態之半導體封裝。圖9係表示第2實施型態之半導體封裝之平面構造。圖10係表示第1元件群之連線接合構造。圖11係表示第2元件群之連線接合構造。圖12及圖13係表示半導體封裝之剖面構造。圖14係表示對半導體元件之具體的連線接合狀態，圖15係表示其變形例。圖9省略樹脂密封部之圖示。
此等圖所示之半導體封裝21具有布線基板22作為元件裝載用之電路基材。電路基材只要可裝載半導體元件，且具 有電路部即可。也可與第1實施型態同樣地適用導線架以取代布線基板22。布線基板22例如在絕緣樹脂基板之內部及表面設有布線網，具體上，適用利用玻璃環氧樹脂及BT樹脂(雙馬來酸酐縮亞胺．三胺樹脂)等之印刷布線基板。
在布線基板22之下表面側之第1主面22a，設有焊料凸塊等作為外部連接端子23。在此，揭示適用於BGA封裝之半導體封裝21，故在布線基板22之下表面，設置焊料凸塊作為外部連接端子23。半導體封裝21也可適用於LGA封裝，此情形，適用金屬溢料面作為外部連接端子23。在布線基板22之上面側之第2主面22b，設有元件裝載部與連接墊24。連接墊24係經由布線基板22之布線網而與外部連接端子23電性連接。連接墊24為連線接合時之連接部。
在布線基板22之元件裝載部上，依序積層構成第1元件群25之第1及第2半導體元件26A、26B。第1半導體元件26A經由省略圖示之接著層被接著於元件裝載部上。第2半導體元件26B經由省略圖示之接著層被接著於第1半導體元件26A上。半導體元件26A、26B具有矩形狀之同一形狀。第1及第2半導體元件26A、26B具有分別形成電極墊27A、27B之電極形成面，使此等電極形成面朝向上方被配置。
在第1元件群25上，經由間隔物層29依序積層有構成第2元件群30之第3及第4半導體元件31A、31B。間隔物層29例如係經由省略圖示之接著層被接著於第2半導體元件26B上。第3半導體元件31A經由省略圖示之接著層被接著於間隔物層29上。第4半導體元件31B經由省略圖示之接著層被 接著於第3半導體元件31A上。在間隔物層29適用具有接著性之絕緣樹脂層之情形，可省略第3半導體元件31A之接著層。
第3及第4半導體元件31A、31B具有矩形狀之同一形狀。第3及第4半導體元件31A、31B分別具有分別形成電極墊32A、32B之電極形成面，使此等電極形成面朝向上方被配置。在第4半導體元件31B上積層第5半導體元件34。第5半導體元件34係經由省略圖示之接著層被接著於第4半導體元件31B上。第5半導體元件34具有比其他半導體元件小型之形狀。第5半導體元件34也可為構成第2元件群30之一部分之半導體元件。
作為第1至第4半導體元件26A、26B、31A、31B之具體例，例如可列舉如NAND型快閃記憶體之半導體記憶元件。作為第5半導體元件34之具體例，例如可列舉如半導體記憶元件之控制元件。構成第1及第2元件群25、30之半導體元件26、31之數分別只要複數個即可，並不限定於2個或3個。第1元件群25也可由3個以上之半導體元件26構成。第2元件群30也可由2個或4個以上之半導體元件31、34構成。
第1至第4電極墊27A、27B、32A、32B分別沿著第1至第4半導體元件26A、26B、31A、31B之外形之一邊，具體上，沿著一方之長邊排列。即，第1至第4半導體元件26A、26B、31A、31B分別具有長邊單側墊構造。第5半導體元件34具有沿著鄰接之二邊排列之電極墊35。第5半導 體元件34具有L型墊構造。第5半導體元件34與其他半導體元件同樣，係使形成電極墊35之電極形成面朝向上方被配置。
具有長邊單側墊構造之第1及第2半導體元件26A、26B係以露出電極墊27A、27B之方式被積層成階梯狀。即，使第1及第2半導體元件26A、26B之短邊一致，且使長邊錯開而積層成露出第1電極墊27A。第2電極墊27B係在第1元件群25與第2元件群30之間配置間隔物層29而露出。
同樣地，第3及第4半導體元件31A、31B係以露出電極墊32A、32B之方式被積層成階梯狀。即，使第3及第4半導體元件31A、31B之短邊一致，且使長邊錯開而積層成露出第3電極墊32A。第5半導體元件34比其他半導體元件小型，故在第5半導體元件34積層於第4半導體元件31B上之狀態下，露出第4半導體元件31B之電極墊32B。
第1至第4半導體元件26A、26B、31A、31B係分別使短邊一致，且使第1半導體元件26A與第3半導體元件31A之長邊、及第2半導體元件26B與第4半導體元件31B之長邊一致而被積層。換言之，第2元件群30係以在布線基板22上之位置與第1元件群25相同之方式，被配置於第1元件群25上。第1元件群25與第2元件群30之對布線基板22之配置位置相同。
藉由適用此種積層構造，可使各電極墊27A、27B、32A、32B露出，且可抑制對布線基板22之半導體元件26、31之佔有面積之增大。即，將4個半導體元件全部積 層成階梯狀之情形，半導體元件之佔有面積為1個半導體元件之面積加上3個份之錯開面積之面積。相對地，本實施型態之半導體元件26、31之佔有面積為1個半導體元件之面積加上1個份之錯開面積之面積。
如上所述，將複數半導體元件分成第1元件群25與第2元件群30，在第1元件群25與第2元件群30之間配置間隔物層29。另外，將第1及第2元件群25、30內之半導體元件26、31積層成階梯狀，且使第1及第2元件群25、30之配置一致。藉此，可利用1個間隔物層29露出電極墊27A、27B、32A、32B，且抑制對布線基板22之半導體元件26、31之佔有面積之增大。間隔物層29之增加會直接關聯到積層厚度之增大。因此，可提供薄型且抑制面積之增大之半導體封裝21。
第1及第2半導體元件26A、26B之電極墊27A、27B係經由第1金屬線37被電性連接於布線基板22之連接墊24。第1電極墊27A與第2電極墊27B之電氣特性及信號特性相等之情形，可將連接於第2電極墊27B之金屬線37連接於第1電極墊27A，經由第1電極墊27A電性連接連接墊24與第2電極墊27B。此際之金屬線37既可個別地實施接合步驟而加以連接，也可以1條金屬線37依序連接連接墊24、第1電極墊27A與第2電極墊27B。
第3及第4半導體元件31A、31B之電極墊32A、32B係經由第2金屬線38被電性連接於布線基板22之連接墊24。第2元件群30也適用與第1元件群25同樣之連接構造。第5半導 體元件34之電極墊35係經由第3金屬線39被電性連接於布線基板22之連接墊24。金屬線37、38、39使用一般的Au線或Cu線等之金屬細線所構成。金屬線37、38、39最好適用可降低環路高度之逆接合。
在安裝半導體元件26、31、34之布線基板22之第2主面22b，例如模塑成型環氧樹脂構成之樹脂密封部40。半導體元件26、31、34係與金屬線37、38、39同時被樹脂密封部40一體密封。藉此，構成使用作為BGA及LGA等之單面積層構造之半導體封裝21。第2實施型態之半導體封裝21適合於多層地積層半導體記憶元件而謀求高容量化之半導體記憶裝置。
構成第1及第2元件群25、30之半導體元件26、31之厚度未必需要受到限定。在第1及第2元件群25、30中，下層側之半導體元件26A、31A之厚度以厚於上層側之半導體元件26B、31B之厚度為宜。在第1元件群25方面，第1半導體元件26A在連線接合時，容易受到傷害，且因布線基板22之表面凹凸而有在樹脂密封部40之模塑成型時發生破裂之虞。因此，第1半導體元件26A之厚度以80~150 μm之範圍為宜。
在第2元件群30方面，第3半導體元件31A之接合部呈現外伸狀態，該部分撓曲時，連線接合性會降低。因此，第3半導體元件31A之厚度以100~180 μm之範圍為宜。第2及第4半導體元件26B、31B之厚度在抑制積層厚度之增加上，以不足80 μm為宜。70 μm以下更佳。半導體元件 26B、31B之厚度與第1實施型態同樣，以20 μm以上為宜。第5半導體元件34之厚度可從功能及積層厚度之觀點適宜地加以選擇。
配置於第1元件群25與第2元件群30之間之間隔物層如圖15所示，也可由可取入金屬線37之元件側端部之絕緣樹脂層41所構成。構成第1元件群25之半導體元件26A、26B中，連接於上層之半導體元件26B之金屬線37之端部被埋入絕緣樹脂層41內。絕緣樹脂層41除了作為間隔物層之功能以外，一併具有作為接著層之功能。絕緣樹脂層41例如係由如丙烯酸樹脂之熱可塑性樹脂、或如環氧樹脂之熱硬化性樹脂所構成。絕緣樹脂層41之厚度較好為30~120 μm之範圍，更好為50~100 μm之範圍。
又，本發明並不限定於上述實施型態，可適用於在導線架等電路基材之單面積層而裝載複數半導體元件之各種半導體封裝。該種半導體元件也包含於本發明。又，本發明之實施型態可在本發明之技術的思想之範圍內加以擴充或變更，此擴充或變更之實施型態也包含於本發明之技術的範圍。
1、21‧‧‧半導體封裝
2‧‧‧導線架
2a‧‧‧導線架之下表面側之第1主面
2b‧‧‧導線架之上面側之第2主面
3‧‧‧導線部
4‧‧‧元件支撐部
5‧‧‧內導線
6‧‧‧外導線
7‧‧‧半導體元件
7A、26A‧‧‧第1半導體元件
7B、26B‧‧‧第2半導體元件
7C、31A‧‧‧第3半導體元件
7D、31B‧‧‧第4半導體元件
8、35‧‧‧電極墊
8A、27A‧‧‧第1電極墊
8B、27B‧‧‧第2電極墊
8C、32A‧‧‧第3電極墊
8D、32B‧‧‧第4電極墊
9、9A、9B、9C、9D‧‧‧電極形成面
10‧‧‧第1接著層
11‧‧‧第2接著層
12‧‧‧第3接著層
13‧‧‧第4接著層
14、18‧‧‧金屬線
14A、37‧‧‧第1金屬線
14B、38‧‧‧第2金屬線
14C、39‧‧‧第3金屬線
14D‧‧‧第4金屬線
15、40‧‧‧樹脂密封部
16‧‧‧絕緣帶
22‧‧‧布線基板
22a‧‧‧布線基板之下表面側之第1主面
22b‧‧‧布線基板之上面側之第2主面
23‧‧‧外部連接端子
24‧‧‧連接墊
25‧‧‧第1元件群
29‧‧‧間隔物層
30‧‧‧第2元件群
34‧‧‧第5半導體元件
41‧‧‧絕緣樹脂層
T1‧‧‧上側樹脂厚度
T2‧‧‧下側樹脂厚度
圖1係表示第1實施型態之半導體封裝之平面圖。
圖2係圖1所示之半導體封裝之平面圖。
圖3係將圖2之A部放大所示之圖。
圖4係圖3之剖面圖。
圖5係表示在第1實施型態之半導體封裝之導線架裝載半 導體元件之狀態之平面圖。
圖6係表示第1實施型態之半導體封裝之導線架之構成之平面圖。
圖7係表示第1實施型態之半導體封裝之導線架之全體構成之平面圖。
圖8係沿著圖5之X-X線之剖面圖。
圖9係表示第2實施型態之半導體封裝之平面圖。
圖10係表示在第2實施型態之半導體封裝之第1元件群施行連線接合之狀態之平面圖。
圖11係表示在第2實施型態之半導體封裝之第2元件群施行連線接合之狀態之平面圖。
圖12係沿著圖9之X-X線之剖面圖。
圖13係沿著圖9之Y-Y線之剖面圖。
圖14係表示在第2實施型態之半導體封裝之半導體元件之積層狀態與連線接合狀態之剖面圖。
圖15係表示圖14所示之半導體元件之積層狀態之變形例之剖面圖。
1‧‧‧半導體封裝
2‧‧‧導線架
2a‧‧‧導線架之下表面側之第1主面
2b‧‧‧導線架之上面側之第2主面
6‧‧‧外導線
7‧‧‧半導體元件
15‧‧‧樹脂密封部

Claims (11)

  1. 一種導線架，其包含：外導線，其係從以密封樹脂密封成具有兩個長邊及兩個短邊之矩形體形狀之情形時之前述密封樹脂之前述兩個短邊突出；內導線，其係與前述外導線電性連接，而埋入於前述密封樹脂；及元件支撐部，其係支撐半導體元件；前述元件支撐部係連接於第一懸吊接腳和第二懸吊接腳；前述第一懸吊接腳係沿著前述長邊之一側而配置；前述第二懸吊接腳係沿著前述長邊之另一側而配置；前述內導線中之第1群係從前述短邊之一側朝向前述長邊之另一側撓曲；且前述內導線中之第2群係從前述短邊之另一側朝向前述長邊之另一側撓曲。
  2. 如請求項1之導線架，其進一步包含保持前述內導線之絕緣帶。
  3. 如請求項2之導線架，其中前述絕緣帶係固定於前述內導線與前述元件支撐部之間。
  4. 如請求項1之導線架，其中前述元件支撐部包含第1部份部及第2部分。
  5. 如請求項4之導線架，其中前述第1部分係連接於複數之前述第1懸吊接腳。
  6. 如請求項4之導線架，其中前述第2部份係連接於複數之前述第2懸吊接腳。
  7. 如請求項4之導線架，其中前述第2部份係連接於前述外導線。
  8. 如請求項1之導線架，其中於前述元件支撐部設置有貫通孔。
  9. 如請求項8之導線架，其中前述貫通孔之形狀係前述長邊之方向成為長度方向。
  10. 如請求項1之導線架，其中前述內導線係至少於2處撓曲。
  11. 如請求項1之導線架，其中前述內導線係至少於2處撓曲，且其相對於前述長邊之方向之角度係至少45度。
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