TWI505424B - 電子組件、包含其之電子設備及該電子設備之製造方法 - Google Patents

電子組件、包含其之電子設備及該電子設備之製造方法 Download PDF

Info

Publication number
TWI505424B
TWI505424B TW102140135A TW102140135A TWI505424B TW I505424 B TWI505424 B TW I505424B TW 102140135 A TW102140135 A TW 102140135A TW 102140135 A TW102140135 A TW 102140135A TW I505424 B TWI505424 B TW I505424B
Authority
TW
Taiwan
Prior art keywords
solder
electrode
conductive portion
terminal
barrier metal
Prior art date
Application number
TW102140135A
Other languages
English (en)
Other versions
TW201428918A (zh
Inventor
Muneyuki Odaira
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of TW201428918A publication Critical patent/TW201428918A/zh
Application granted granted Critical
Publication of TWI505424B publication Critical patent/TWI505424B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/11472—Profile of the lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/116—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/1161—Physical or chemical etching
    • H01L2224/11614—Physical or chemical etching by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H01L2224/11902—Multiple masking steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H01L2224/11902—Multiple masking steps
    • H01L2224/11903—Multiple masking steps using different masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13007—Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13011—Shape comprising apertures or cavities, e.g. hollow bump
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13013—Shape in top view being rectangular or square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13014—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13017—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H01L2224/13019—Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/13076—Plural core members being mutually engaged together, e.g. through inserts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13084—Four-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1356—Disposition
    • H01L2224/13562—On the entire exposed surface of the core
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1356—Disposition
    • H01L2224/13563—Only on parts of the surface of the core, i.e. partial coating
    • H01L2224/13564—Only on the bonding interface of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1357—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13575—Plural coating layers
    • H01L2224/1358—Plural coating layers being stacked
    • H01L2224/13582—Two-layer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13611—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1601—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605—Shape
    • H01L2224/16057—Shape in side view
    • H01L2224/16058—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/165—Material
    • H01L2224/16501—Material at the bonding interface
    • H01L2224/16503—Material at the bonding interface comprising an intermetallic compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/165—Material
    • H01L2224/16505—Material outside the bonding interface, e.g. in the bulk of the bump connector
    • H01L2224/16507—Material outside the bonding interface, e.g. in the bulk of the bump connector comprising an intermetallic compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/8181—Soldering or alloying involving forming an intermetallic compound at the bonding interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/8182—Diffusion bonding
    • H01L2224/81825—Solid-liquid interdiffusion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

電子組件、包含其之電子設備及該電子設備之製造方法 發明領域
本文揭示係有關於電子組件、包含其之電子設備及該電子設備之製造方法。
 發明背景
已知利用稱作為柱(又稱桿)的一電極之一電子組件諸如半導體元件。已知一種技術其中該電子組件之一電極係使用形成在該電極上之焊料而連結至一對偶電子組件諸如半導體元件的一電極(例如一柱)以電氣連結兩個電極。在連結處理期間可能出現電極成分與焊料成分之擴散及反應。也已知一種在一電極上形成一位障層之技術，其具有比較該電極難以出現該焊料成分之擴散及反應的性質。
又復，習知地，從遏止該焊料成分之擴散及反應之觀點，已知在焊料凸塊與下方襯墊間形成一位障金屬之技術。例如參考日本特許申請公開案第2010-263208號及日本特許申請公開案第2013-31576號。
 發明概要
據此，於本發明之一面向中的一目的係提出一種藉使用焊料連結兩個電氣組件之可靠連結技術。依據本發明之一面向，一電子組件包括一電極部及形成於該電極部上的一焊料部。於該電子組件中，該電極部包括一第一傳導部及一第二傳導部，各自具有相對於該電極部之一頂面上的該焊料部之一成分的不同擴散係數，及該焊料部係形成於該第一傳導部及該第二傳導部上。
1A-C、300、320‧‧‧電子組件
10、210‧‧‧主體部
10a、210a‧‧‧佈線部
20A-C、20Aa、20Ab、220、310、330‧‧‧端子
21‧‧‧電極部
21a、221‧‧‧柱電極
21b、222‧‧‧位障金屬
21c、21e‧‧‧凸部
21d、31a-37a‧‧‧開口部
22、223‧‧‧焊料
23、23A-C、221a‧‧‧化合物
30‧‧‧基體
30a‧‧‧黏著層
30b‧‧‧晶種層
31-37‧‧‧光阻
41‧‧‧鍍覆層
42‧‧‧電極層
50、60‧‧‧連結部
51、62‧‧‧鎳(Ni)層
52、53、61、63‧‧‧銅(Cu)層
54、64‧‧‧連結層
64a‧‧‧孔隙部
64b‧‧‧擴散部
100‧‧‧半導體裝置
110、200‧‧‧半導體晶片
111‧‧‧連接端子
120‧‧‧電路基體
121‧‧‧傳導部
121a‧‧‧電極端子
122‧‧‧絕緣部
123‧‧‧外部連接端子
130‧‧‧底填補材料
223a‧‧‧斷裂部
223b‧‧‧溶蝕部
L、L1-3‧‧‧視線
圖1A及1B為例示一示範半導體裝置之視圖。
圖2為例示一示範端子之一視圖。
圖3A及3B為端子間之連結的一範例之說明圖。
圖4A及4B為例示依據第一實施例之一示範端子之視圖。
圖5A至5D為依據第一實施例之端子間之連結的一範例之說明圖。
圖6A及6B為依據第一實施例之端子間之連結的另一範例之說明圖。
圖7A至7C為依據第一實施例之一種端子形成方法的一範例之說明(第一)視圖。
圖8A至8D為依據第一實施例之該端子形成方法的該範例之說明(第二)視圖。
圖9A至9D為依據第一實施例之該端子形成方法的該範例之說明(第三)視圖。
圖10A至10D為一種端子形成方法的另二範例之說明圖。
圖11A至11D為該端子形成方法的另二範例之其它說明圖。
圖12A及12B為例示依據第二實施例之一示範端子之視圖。
圖13A至13D為依據第二實施例之端子間之連結的一範例之說明圖。
圖14A及14B為依據第二實施例之端子間之連結的另一範例之說明圖。
圖15A至15D為依據第二實施例之一種端子形成方法的一範例之說明(第一)視圖。
圖16A至16D為依據第二實施例之該端子形成方法的一範例之說明(第二)視圖。
圖17A及17B為例示依據第三實施例之一示範端子之視圖。
圖18A至18D為依據第三實施例之端子間之連結的一範例之說明圖。
圖19A及19B為依據第三實施例之端子間之連結的另一範例之說明圖。
圖20A至20D為依據第三實施例之一種端子形成方法的一範例之說明(第一)視圖。
圖21A至21D為依據第三實施例之該端子形成方法的一範例之說明(第二)視圖。
圖22A至22C為例示於再流處理後之另一示範端子之視圖。
圖23為一例示評估結果之一範例之一視圖。
 較佳實施例之詳細說明
當一電子組件之一電極係藉焊接法而連結另一電子組件之另一電極時，可能發生一種情況，於該處由於電極成分與形成於電極上的焊料成分間之擴散及反應，可能出現連結部體積縮小，如此於連結期間或於連結後連結部斷裂。即便當位障層形成於電極上時，仍然擔憂焊料成分可能沿位障層的一側表面而擴散至下電極，及與該電極反應而造成該連結部體積縮小及連結部斷裂，取決於例如電極及焊料材料，以及連結條件(例如電子組件的壓縮量及位障層上的焊料量)。
依據本文揭示之一面向，提出一種電子組件其包括一電極部及形成於該電極部上的一焊料部。於該電子組件中，該電極部包括一第一傳導部及一第二傳導部，相對於焊料部成分具有不同的擴散係數且係形成於該電極部之一頂面上，及該焊料部係形成於該第一傳導部及該第二傳導部上。
又，依據本文揭示之另一面向，提出一種包括該電子組件之電子設備及該電子設備之製造方法。
依據所揭示之技術，相對於焊料部成分具有不同的擴散係數的傳導部係配置於該電極部之頂面上以造成於與一對偶端子連結期間，優先擴散及反應係出現在該等傳導部中之一者。結果可能遏止焊料部從電極部的頂面擴散至側面。據此，連結部的斷裂受遏止以改良電子組件間的連接可信度。
首先將描述電子組件間的連接技術。舉例言之，作為連接半導體元件(例如半導體晶片)至電路基體之技術，已知打線接合技術，其中該半導體晶片係安裝於電路基體上以藉一導線連結該半導體 晶片之端子至該電路基體之端子。又，隨著連接端子數目的增加，已經變成運用覆晶連結技術，其中該半導體晶片之端子與該電路基體之端子彼此面對面以連結該半導體晶片與該電路基體之該等端子。
圖1為例示一示範半導體裝置之一視圖。圖1A為該半導體 裝置之一實施例的平面圖，及圖1B為沿線L-L所取半導體裝置之剖面圖。如圖1A及圖1B所例示，半導體裝置100包括一半導體晶片110及一電路基體120。如圖1B所例示，半導體晶片110包括設於該半導體晶片110之一表面上的複數個連接端子111。如圖1B所例示，該電路基體120包括一傳導部121(例如佈線、通孔、貫穿孔)及環繞該傳導部121的一絕緣部122。電極端子121a之配置位置係相對應於在該電路基體120的半導體晶片110之各個連接端子111位置。半導體晶片110係配置成與電路基體120相對，及各個連接端子111係連結至相對應電極端子121a，及因而半導體晶片110係電連接電路基體120。
如圖1B所例示，底填補材料130可填補於半導體晶片110與 電路基體120間。又，外部連接端子123諸如焊珠可設置於該電路基體120之與該半導體晶片110表面相對的一表面上，許可連同半導體晶片110安裝的電路基體120利用該外部連接端子123而連接其它電路基體(例如二次安裝)。
於一覆晶連結技術中，連結材料諸如焊料或銅(Cu)係廣用 在端子部。除了使用凸塊諸如焊珠之方法外，端子可藉連結法形成，其中例如使用銅(Cu)形成一柱電極，從增加端子數目及改良連接可信度觀點，在柱電極上形成焊料以連結一對偶端子(例如柱電極)。至於焊料，考慮環保效益已經使用不含鉛(Pb)的無鉛焊料。
同理，包括前述柱電極的端子結構可採用於電路基體端子 或除了半導體晶片端子外設有該半導體晶片的一半導體裝置(例如半導體裝置封裝體)的端子。
無鉛焊料的主成分錫(Sn)的擴散係數相對於銅為高。因 此，當端子連結期間藉加熱而熔解焊料時，錫(Sn)與銅(Cu)彼此擴散且彼此反應，因此含錫(Sn)與銅(Cu)的金屬間化合物(IMC)形成於端子間的連結部上。當藉連結製程期間產生的熱或藉連結製程後產生的熱(例如二次安裝期間產生的熱或半導體晶片操作期間產生的熱造成的加熱)進行錫(Sn)與銅(Cu)之擴散及反應時，可能出現諸如端子間的連結部體積縮小及錫(Sn)溶蝕入端子下層佈線部之現象。
考慮此種現象，可利用一種端子結構其中與錫(Sn)的反應 性比銅(Cu)更低的材料(例如對錫具低擴散係數)諸如，舉例來說，鎳(Ni)層形成於銅製成的一柱電極上作為位障金屬層以遏止錫與銅的反應。
圖2為例示一端子之一範例的一視圖。此處，將舉例說明 一半導體晶片之端子結構。一半導體晶片實施例之主部的剖面圖係圖解例示於圖2。如圖2所例示之半導體晶片200包括從設於主體部210的一佈線部210a凸起的一端子220。又，為求方便只舉例說明單一端子220，但複數個端子220也可設於主體部210上。該端子220包括設於該佈線部210a上的一柱電極221，設於該柱電極221上的一位障金屬222，及形成於該位障金屬222上的一焊料223。舉例言之，銅係用於柱電極221，鎳係用於位障金屬222，及含錫(Sn)作為主成分的材料係用於焊料223。
如前文描述，焊料223係形成於柱電極221上，透過位障金 屬222以遏止於連結期間或於半導體晶片200連結後的加熱期間焊料 223之錫(Sn)與柱電極221之銅的擴散及反應。但如圖3所例示，即便當採用其中位障金屬222係設於柱電極221上的端子220時，仍可能出現一種情況於該處焊料223之錫(Sn)與柱電極221之銅反應。
圖3為例示端子間之連結的一範例之一視圖。此處，將舉 例說明如圖2所例示設有端子之半導體晶片的連結。圖3A及圖3B分別例示進行連結的示範半導體晶片之主部的剖面圖。
例如當其上設有如圖2所例示的端子220之該半導體晶片 200係彼此連結時，於其上設有一上及下半導體晶片200的該位障金屬222之該等柱電極221係彼此連結，使得焊料223係插置於該等柱電極221間，如圖3A所例示。於此種情況下，含在焊料223內的錫(Sn)可優先地沿位障金屬222之一側表面朝向具有比由鎳(Ni)製成的位障金屬222之擴散係數更高的一擴散係數之銅製成的柱電極221之一側表面擴散。前述擴散更容易出現在一種情況於該處如圖所示材料係為錫(Sn)與銅(Cu)的組合，或一種情況於該處於連結期間焊料223係從位障金屬222頂面擴散至側面。又復，隨著於連結期間形成於位障金屬222上的焊料223量之逐漸增加，更容易出現一種情況於該處焊料223從位障金屬222頂面擴散至側面。又，於連結期間隨著半導體晶片200壓力量的遞增更容易出現該情況。
如圖3A所例示，當焊料223的錫(Sn)沿位障金屬222之一側 面擴散至銅製成的柱電極221的側面且與銅反應時，含錫(Sn)及銅(Cu)的一化合物221a可形成於柱電極221的一外側面上。如圖3B所例示，當含於該焊料223的錫(Sn)擴散量增加時，與柱電極221的銅(Cu)之反應量增加，及因而化合物221a可形成於柱電極221的外側面之較大範圍。如前文描述，當焊料223的錫(Sn)擴散至柱電極221的側面且耗用 在該側面形成化合物221a時，留在彼此相對的柱電極221間(位障金屬222間)之一空間的焊料223量減少。於此種情況下，如圖3B所例示，在柱電極221間的焊料223產生一斷裂部223a，可能出現柱電極221間之連接故障。
又復，當從位障金屬222頂面擴散至柱電極221側面的錫 (Sn)係進一步擴散到達柱電極221下方的佈線部210a時，錫(Sn)與佈線部210a的一成分反應而溶蝕佈線部佈線部210a(例如溶蝕部223b)，如此，擔憂可能發生佈線部210a的故障。
可考慮一種方法其中錫(Sn)的擴散可藉以例如聚醯亞胺 樹脂薄膜覆蓋柱電極221之側面加以遏止。但當此種薄膜不夠黏合至柱電極221之側面時，難以達成需要的擴散遏止。
如圖2所例示，含柱電極221、位障金屬222及焊料223的端 子220結構也可採用於設有半導體晶片的一半導體封裝體的端子，或除了半導體晶片之端子外採用於電路基體之端子。端子220之結構也可採用於各個電子組件間之連接，諸如，舉例來說，半導體晶片與電路基體間之一連接、半導體晶片與半導體封裝體間之一連接、半導體封裝體與電路基體間之一連接、半導體封裝體間之一連接、及除了半導體晶片間之連接外電路基體間之一連接。由如前述焊料223之錫(Sn)的擴散造成的斷裂部223a之生成及佈線部210a之溶蝕也可能出現在採用端子220之結構的各個電子組件間之連接。
綜上所述，具有如後文描述的結構之一端子係用作為電子 組件之端子，諸如半導體晶片、半導體封裝體、及電路基體。將說明一第一實施例。
圖4為例示依據第一實施例之一示範端子的一視圖。圖4A 為一平面圖例示設有依據第一實施例的端子的一電子組件之一範例的主部。圖4B為一剖面圖所例示設有依據第一實施例的端子的一電子組件之一範例的主部之剖面。圖4B為沿圖4A之線L1-L1所取截面圖。為求方便部分焊料係不示例說明於圖4A。
圖4A及圖4B所例示的一電子組件1A係設有一端子20A， 其從設於一主體部10的佈線部10a凸起。又，為了方便起見圖4A例示單一端子20A，但複數個端子20A可設於主體部10上。
端子20A包括一電極部21及形成於電極部21上的一焊料 22(或例如一焊料部)。端子20A之電極部21包括設在佈線部10a上的一柱電極21a(例如傳導部)、設在柱電極21a上的一位障金屬21b(例如傳導部)、及設在位障金屬21b上的一凸部21c(例如傳導部)。與含在焊料22的預定成分反應以形成化合物的材料係用在凸部21c。
設有位障金屬21b以覆蓋柱電極21a的頂面。凸部21c係設 在位障金屬21b頂面上的一部分，於本範例中，設在位障金屬21b頂面上的中部上。位障金屬21b及凸部21暴露於電極部21頂面上，焊料22係形成於電極部21上以覆蓋暴露於電極部21頂面上的位障金屬21b及凸部21。
具有錫(Sn)作為主成分的材料係用在焊料22。舉例來說， 諸如銅(Cu)之材料用在電極部21的柱電極21a。含在焊料22的成分於本範例中，相對於錫(Sn)具有不同擴散係數的材料係用在電極部21的位障金屬21b及凸部21c。此處，相對於錫(Sn)具有不同擴散係數，係低於凸部21c的擴散係數，的材料係用在位障金屬21b。舉例言之，鎳(Ni)係用在位障金屬21b，例如銅(Cu)係用在凸部21c。後文中將舉例說明使用前述材料的端子20A。
當銅(Cu)對錫(Sn)的擴散係數比較得自其它文件(例如http：//diffusion.nims.go.jp/)的鎳(Ni)對錫(Sn)的擴散係數時，於200℃溫度銅(Cu)之擴散係數為2.05x10-10 (平方米/秒)及鎳(Ni)之擴散係數為1.79x10-10 (平方米/秒)。於100℃溫度銅(Cu)之擴散係數為6.17x10-11 (平方米/秒)及鎳(Ni)之擴散係數為4.86x10-11 (平方米/秒)。銅(Cu)對錫(Sn)的擴散係數係高於鎳(Ni)對錫(Sn)的擴散係數。
如前文描述，位障金屬21b及具有對錫(Sn)的擴散係數高於位障金屬21b對錫(Sn)的擴散係數之凸部21c係形成於電極部21頂面上，如此，於其它電子組件及電子組件1A連結期間，含在焊料22的錫(Sn)優先擴散及與凸部21c反應。據此，可遏止焊料22的錫(Sn)朝向柱電極21a側面擴散。
圖5為例示依據第一實施例在端子間之連結之一範例。此處，將舉例說明如圖4所例示，設有端子20A的電子組件1A之連結。圖5A、5B、5C及5D例示連結期間電子組件1A之一範例的主部。
端子20A係設在事先欲連結的電子組件1A之相對應位置。如圖5A所例示，當端子20A彼此連結時，端子20A首先係配置成在設有端子20A的電子組件1A中彼此面對面。
如圖5B所例示，隨後，於其上形成位障金屬21b及凸部21c的電子組件1A的柱電極21a係彼此連結，使得當於焊料22的熔點或以上溫度加熱時，藉加壓電子組件1A而讓焊料22插置在柱電極21a間。於此種情況下，含在焊料22的錫(Sn)優先擴散至及與在與焊料22接觸的鎳(Ni)製成的位障金屬21b及銅(Cu)製成的凸部21c間有較高擴散係數的銅(Cu)製成的凸部21c反應以形成一化合物23。如圖5C所例示，隨著焊料22之錫(Sn)與凸部21c的銅(Cu)反應，化合物23持續生 長。
如圖5C所例示，當化合物23生長時，隨著化合物的生長 而出現柱電極21a間(例如位障金屬21b間)的連結部的體積收縮。類似本範例，以銅(Cu)用在凸部21c為例，當銅(Cu)與錫(Sn)彼此反應以形成化合物23時，化合物之晶體緊密排列，如此出現柱電極21a間之連結部的體積收縮。銅(Cu)之密度為8.9克/平方厘米，及錫(Sn)之密度為7.3克/平方厘米。當此種銅(Cu)與錫(Sn)彼此反應時，形成銅-錫化合物(Cu6 Sn5 )為化合物23。當從錫(Sn)及銅(Cu)的金屬二元相圖預測含在化合物23的銅(Cu)對錫(Sn)之質量比時，銅(Cu)對錫(Sn)之質量比為約40：60。化合物23之密度為8.28克/平方厘米，及在形成化合物23期間，化合物23之體積減少約5%。當凸部21c形成於位障金屬21b中部時，隨著化合物23的生長，如圖5C及又圖5D所例示，柱電極21a間之連結部的體積收縮朝向位障金屬21b之中部繼續進行。
如前文描述，銅(Cu)製成的凸部21c係形成於鎳(Ni)製成的 位障金屬21b中部上，如此焊料22之錫(Sn)優先擴散至且與凸部21c反應以形成化合物23。又復，當形成化合物23時，出現朝向位障金屬21b之中部的柱電極21a間之連結部的體積收縮。據此，焊料22的錫(Sn)沿側面擴散至電極部21側面可藉停止焊料22在相對電極部21間之空間的擴散流加以遏止。又復，焊料22與柱電極21a的過度反應可藉位障金屬21b遏止。結果，在相對電極部21間之空間的連結部的焊料22減少及因而，可遏止斷裂部的產生。
於端子20A其中銅(Cu)製成的凸部21c係形成於鎳(Ni)製 成的位障金屬21b中部上，當凸部21c的全部銅(Cu)皆耗用在與焊料22的錫(Sn)形成化合物23時，耗盡後化合物23的形成不再連續進行。 因此，焊料22的錫(Sn)之過度擴散被遏止。
如前文描述，端子20A係設在電子組件1A上以具現電子設 備，其中電子組件1A係以高度可信度連接。同時，於該電子設備中，並非全部焊料22皆須改變成化合物以形成連結態如圖5D所例示，而可改變成化合物以形成如圖5B及圖5C所例示之連結態。於具有如圖5B及圖5C所例示之連結態的電子設備中，當後來加熱時，錫(Sn)擴散至柱電極21a側面及連結部斷裂可被遏止，原因在於焊料223的錫(Sn)優先擴散至凸部21c，及原因在於化合物23形成期間的體積收縮之故。
雖然設有端子20A的電子組件1A間之連結係供舉例說 明，但當設有端子20A的電子組件1A與設有與端子20A相異的一結構之設有一端子的其它電子組件連結時可獲得前述效果。
圖6為說明依據第一實施例該等端子間之連結的一範例之 一圖。於圖6A之一實施例中，電子組件1A係連結與電子組件1A相異的一電子組件300。如前文描述，電子組件1A係設有端子20A包括柱電極21a、位障金屬21b及凸部21c。同時，電子組件300設有端子310其係包括柱電極21a及位障金屬21b但不包括凸部21c。類似前文描述，焊料22的錫(Sn)之優先擴散至凸部21c及依據化合物23形成的體積縮小也在電子組件1A之端子20A與電子組件300之端子310間之連結產生。據此，可遏止錫(Sn)之擴散至柱電極21a側面及柱電極21a間之連結部的斷裂。
於圖6B之範例中，電子組件1A係與電子組件1A相異的電 子組件320連結。電子組件1A係設有端子20A包括柱電極21a、位障金屬21b及凸部21c；而電子組件320係設有不包括位障金屬21b及凸 部21c的端子330。同時，端子330可具有多種形狀，舉例來說，諸如柱電極、襯墊電極及佈線部。焊料22的錫(Sn)之優先擴散至凸部21c及依據化合物23形成的體積縮小也在電子組件1A之端子20A與電子組件320之端子330間之連結產生。據此，可遏止錫(Sn)之擴散至柱電極21a側面或端子330及柱電極21a間之連結部的斷裂。
如前文描述之端子20A係設在電子組件1A上以具現一電 子設備，其中電子組件1A與其它電子組件係以高可信度連結。其次將說明如前述形成依據第一實施例的端子20A之方法。
圖7至圖9為解釋依據第一實施例一端子形成方法之一範 例的視圖。於一端子形成方法的各個製程中主部之剖面圖係圖解例示於圖7至圖9。首先製備如圖7A所例示之其中形成端子20A的基體30。電子組件1A的一或多個主體部10係形成於基體30上，但為求簡明在此不例示。換言之，有一種情況於該處基體30本身為單一電子組件1A(例如電路基體)的主體部10，或複數個電子組件1A的主體部10係含括於基體30(例如其中形成多個半導體晶片的一晶圓)。又復，當複數個電子組件1A的主體部10係含括於基體30時，在端子20A形成於各個主體部10上之後，複數個電子組件1A分開成一電子組件1A。
製備如圖7A所例示，黏著層30a及晶種層30b係形成於基 體30上。舉例言之，具有100奈米厚度的鈦(Ti)層係形成為黏著層30a，具有500奈米厚度的銅(Cu)層係形成為晶種層30b。該黏著層30a及晶種層30b可使用濺鍍法形成。
隨後，如圖7B所例示，塗覆光阻31，及在光阻31上執行曝光及顯影以在其中形成基體30的端子20A之一區(例如相對應於主 體部10的佈線部10a之一區)形成一開口部31a。例如形成具有10微米直徑的開口部31a。
隨後，如圖7B所例示，使用電解鍍覆法，使用晶種層30b 作為動力進給層而鍍覆銅(Cu)以在光阻31的開口部31a內部形成柱電極21a。舉例言之，具有5微米高度(厚度)的銅(Cu)製成之柱電極21a係形成於光阻31的開口部31a內部。
隨後如圖8A所例示，利用電解鍍覆法，位障金屬21b係形 成於光阻31的開口部31a內部的柱電極21a上。舉例言之，具有3微米高度(厚度)的鎳(Ni)層作為位障金屬21b係形成於柱電極21a 31上。
如圖8B所例示，在形成位障金屬21b之後剝離光阻31。隨 後如圖8C所例示，光阻32係經塗覆，曝光製程及顯影製程係在光阻32上執行以在位障金屬21b中部形成開口部32a。例如在光阻32上形成具有8微米直徑的開口部32a。
隨後如圖8D所例示，利用電解鍍覆法，凸部21c係形成於 光阻32的開口部32a內部的位障金屬21b上。舉例言之，具有2微米高度(厚度)的銅(Cu)層係形成於位障金屬21b上作為凸部21c。據此，形成該電極部21其中位障金屬21b係形成於柱電極21a上而凸部21c係形成於位障金屬21b上。
如圖9A所例示，在凸部21c形成後剝除光阻32。隨後如圖 9B所例示，塗覆光阻33，及在光阻33上執行曝光及顯影以在電極部21之一區形成一開口部33a。
隨後如圖9C所例示，使用電解鍍覆法，焊料22形成於光 阻33之開口部33a內部的凸部21c及位障金屬21b上。舉例言之，具有3.5微米厚度的錫-銀(SnAg)焊料係形成作為焊料22。又，欲形成的焊 料22體積可設定為凸部21c體積之約1.85倍或以下的體積以便讓含在焊料22中的全部錫(Sn)皆與銅反應。於此種情況下，凸部21c的銅尺寸可定義為具有2微米厚度及8微米直徑的圓柱，及焊料的期望厚度為約3.65微米或以下。
形成焊料22後，如圖9D所例示，光阻33被剝除，及在光 阻33被剝除後暴露的晶種層30b及黏著層30a藉蝕刻去除。在晶種層30b及黏著層30a被蝕刻之後執行再流處理以形成具有圓化形狀的焊料22，如圖9D所例示。同時，可刪除圖9D之再流處理。
其中形成焊料22以覆蓋形成於柱電極21a上的位障金屬 21b及形成於位障金屬21b中部上的凸部21c之端子20A係依據圖7A至圖9D之製程製造。
依據圖10及圖11所例示之方法製成的端子可用作為一端 子，其中具有比焊料組件更高的擴散係數之一凸部係形成於位障金屬上，類似依據第一實施例的端子20A，形成焊料以覆蓋位障金屬及凸部。
圖10為端子形成方法之另一範例的解說圖。於端子形成方 法之各個製程中主部之剖面圖係圖解例示於圖10。於圖10之範例中，首先執行圖7A至圖7C所例示之方法。隨後，如圖10A所例示，形成位障金屬21b，用以形成凸部21c的該鍍覆層41係形成於位障金屬21b上，及使用電解鍍覆法焊料22係形成於鍍覆層41上。舉例言之，形成具有3微米厚度的鎳(Ni)層，具有2微米厚度的銅(Cu)層係形成作為鍍覆層41，及形成具有3.5微米厚度的錫-鎳(Sn-Ag)焊料層作為焊料22。
隨後，如圖10B所例示光阻31被剝除，及光阻31被剝除後 暴露的晶種層30b及黏著層30a藉蝕刻去除，如圖10C所例示。於此種情況下，晶種層30b係藉濕蝕刻去除。於該濕蝕刻中，比較鎳(Ni)製成的位障金屬21b之蝕刻速率，銅(Cu)製成的鍍覆層41之蝕刻速率為較高。鍍覆層41之直徑變成比位障金屬21b之直徑更窄，結果具有窄化直徑的鍍覆層41亦即凸部21c因鎳(Ni)與銅(Cu)之蝕刻速率間之差異故而形成於位障金屬21b的中部上。
在藉濕蝕刻形成凸部21c期間也進行柱電極21a之蝕刻 法。又，在藉濕蝕刻形成凸部21c期間也進行焊料22之蝕刻。因此，如圖10C所例示，柱電極21a直徑及焊料22直徑也可變成比位障金屬21b之直徑更窄。
於凸部21c形成後進行再流處理以形成具有圓化形狀的焊料22，如圖10D所例示。同時，可刪除圖10D的再流處理。
其中形成焊料22以覆蓋位障金屬21b及形成於位障金屬21b中部上的凸部21c之端子20Aa係依據圖7A至圖7C及圖10A至圖10D之製程製造。
圖11為端子形成方法之另一範例的解說圖。端子形成方法之各個製程中主部的剖面圖係圖解例示於圖11。於圖11之範例中，首先執行圖7A至圖7C所例示之處理。隨後如圖11A所例示，形成電極層42，用以形成凸部21c的鍍覆層41係形成於電極層42上，及使用電解鍍覆法焊料22形成於鍍覆層41上。舉例言之，具有8微米之高度(厚度)的鎳(Ni)層係形成為電極層42，具有2微米之高度(厚度)的銅(Cu)層係形成為鍍覆層41，及具有3.5微米之高度(厚度)的錫-銀(Sn-Ag)層係形成為焊料22。鎳(Ni)製成的電極層42用作為柱電極及位障金屬。
隨後，如圖11B所例示光阻31被剝除，及光阻31被剝除後 暴露的晶種層30b及黏著層30a藉蝕刻去除，如圖11C所例示。於此種情況下，晶種層30b係藉濕蝕刻去除。於該濕蝕刻中，比較鎳製成的位障金屬21b之蝕刻速率，銅製成的鍍覆層41之蝕刻速率為較高。利用濕蝕刻中鎳(Ni)與銅(Cu)之蝕刻速率間之差異，鍍覆層41之直徑變成比位障金屬21b之直徑更窄。據此，具有窄化直徑的鍍覆層41亦即凸部21c形成於電極層42的中部上。
在藉濕蝕刻形成凸部21c期間也進行焊料22之蝕刻法。 又，在藉濕蝕刻形成凸部21c期間也進行焊料22之蝕刻。因此，如圖11C所例示，焊料22直徑可變成比電極層42之直徑更窄。
於凸部21c形成後進行再流處理以形成具有圓化形狀的焊 料22，如圖11D所例示。同時，可刪除圖10D的再流處理。
其中形成焊料22以覆蓋電極層42，其係用作為柱電極及位 障金屬，及形成於電極層42中部上的凸部21c之端子20Aa係依據圖7A至圖7C及圖11A至圖11D之製程製造。
如前述端子20A、端子20Aa、及端子20Ab可製作成當從頂 面觀看時具有圓形形狀或實質上圓形形狀。此外，端子20A、端子20Aa、及端子20Ab可製作成當從頂面觀看時具有橢圓形形狀或實質上橢圓形形狀、四邊形形狀或實質上四邊形形狀、或三角形形狀或實質上三角形形狀。
又復，於如前述端子20A、端子20Aa、及端子20Ab中，雖 然凸部21c係形成於位障金屬21b及電極層42的中部，但凸部21c可不形成於位障金屬21b及電極層42的中部。當凸部21c係形成於位障金屬21b及電極層42的側部而非中部時，於連結期間，可獲得焊料22之 錫(Sn)優先擴散至凸部21c，及連結部朝向21C的體積縮小。據此，可遏止錫(Sn)之擴散至例如柱電極21a的側面及連結部的斷裂。
又復，如前述端子20A、端子20Aa、及端子20Ab包括銅(Cu) 製的柱電極21a、鎳(Ni)製的位障金屬21b、銅(Cu)製的凸部21c、及鎳(Ni)製的電極作為柱電極作為其元件。此處，除了純銅(Cu)製的柱電極21a及純銅(Cu)製的凸部21c外，銅(Cu)製的柱電極21a及銅(Cu)製的凸部21c包括其主要成分為銅(Cu)的柱電極21a及凸部21c。除了純鎳(Ni)製的位障金屬21b及純鎳(Ni)製的電極層外，鎳(Ni)製的位障金屬21b及鎳(Ni)製的電極層包括其主要成分為鎳(Ni)的位障金屬21b及其主要成分為鎳(Ni)的電極層。
又復，用在凸部21c及位障金屬21b及電極層42的材料組合 並不限於如前文描述銅(Cu)(例如包括其主要成分為銅(Cu)的材料)及鎳(Ni)(例如包括其主要成分為鎳(Ni)的材料)的組合。用在焊料22的材料之一成分須具有一擴散係數其針對凸部21c為較大，而針對位障金屬21b及電極層42為較小。
其次將描述第二實施例。圖12例示依據第二實施例一端子 之一範例的一視圖。圖12A為例示依據第二實施例設有該端子之電子組件的一範例之主部的一平面圖。圖12B為例示依據第二實施例設有該端子之電子組件的一範例之主部的一剖面圖。圖12B為沿圖12A之線L1-L1所取的剖面圖。為求方便部分焊料未例示於圖412。
圖12A及圖12B所例示的電子組件1B設有一端子20B從設 在主體部10上的佈線部10a凸起。又復，為求方便單一端子20B例示於圖12A，但複數個端子20B可設在主體部10上。
端子20B包括一電極部21及形成於電極部21上的一焊料 22(例如焊料部)。電極部21包括設在佈線部10a上的一柱電極21a(例如傳導部)、設在柱電極21a上的一位障金屬21b(例如傳導部)。到達位障金屬21b下方的柱電極21a之一開口部21d係形成於位障金屬21b上。於本範例中，開口部21d係形成於位障金屬21b中部上。開口部21d的位障金屬21b及柱電極21a暴露於頂面上，焊料22係形成以覆蓋電極部21的電極部21頂面、及位障金屬21b及柱電極21a。
具有錫(Sn)作為主成分的材料係用於焊料22。舉例來說， 材料諸如銅(Cu)係用在柱電極21a。含在焊料22中的一成分亦即於本範例中，具有相對於錫(Sn)的擴散係數係低於柱電極21a的擴散係數之材料係用於電極部21的位障金屬21b。後文中將舉例說明使用前述材料的端子20B。
如前文描述，於端子20B中，一開口部21d係形成於鎳(Ni) 製位障金屬21b，該位障金屬21b及具有相對於錫(Sn)更高擴散係數的銅(Cu)製柱電極21a係從位障金屬21b的開口部21d而暴露於電極部21d頂面上，及位障金屬21b及柱電極21a係以焊料22覆蓋。據此，於電子組件1B與其它電子組件連結過程中，焊料22的錫(Sn)優先擴散至且與開口部21d的銅(Cu)製柱電極21a起反應，及因而可遏止錫(Sn)之擴散至柱電極21a側面。
圖13為例示依據第二實施例該等端子間之連結的一範例 之一圖。此處，將舉例說明如圖12所例示在設有端子20B的電子組件1B間之連結。圖13A至圖13D例示於連結處理期間電子組件1B之一範例的主部的剖面圖。
端子20B設有事先欲連接的電子組件1B的相對應位置上。當端子20B彼此連結時，如圖13A所例示，在設有端子20B的電 子組件1B中，端子20B首先係配置成彼此面對面。
隨後，如圖13B所例示，當於焊料22之熔點或更高溫度加 熱時，藉加壓電子組件1A，電子組件1A的於其上形成具有一開口部21d的位障金屬21b之該等柱電極21a係彼此連結成焊料22係插置於柱電極21a間。於此種情況下，含在焊料22的錫(Sn)優先擴散且與接觸焊料22的開口部21d的鎳(Ni)製位障金屬21b及銅(Cu)製柱電極21a中之具有較高擴散係數的銅(Cu)製柱電極21a起反應以形成一化合物23。隨著焊料22之錫(Sn)與開口部21d的柱電極21a之銅反應之進行，化合物23持續生長，如圖13C所例示。
如圖13C所例示，當化合物23生長時，隨著化合物的生 長，晶體緻密排列，因而出現柱電極21a(位障金屬21b間)間之連結部的體積縮小。如圖13C及進一步如圖13D所例示，隨著化合物23之生長，當開口部21d形成於位障金屬21b的中部上時，柱電極21a間連結部的體積縮小朝向位障金屬21b中部進行。
如前文描述，到達銅(Cu)製柱電極21a的開口部21d係形成 於鎳(Ni)製位障金屬21b的中部上，及因而焊料22的錫(Sn)優先擴散至且與開口部21d的柱電極21a起反應以形成化合物23。又復，當形成化合物23時，出現相對柱電極21a間連結部的體積縮小。據此，藉中止在電極部21間之一部分焊料22之擴散流，可遏止焊料22之錫(Sn)沿位障金屬21b側面擴散至柱電極21側面。又，焊料22與柱電極21a的過度反應藉位障金屬21b遏止。結果，相對柱電極21a間之連結部的焊料22減少，因而可遏止斷裂部的產生。
於端子20B中，其中到達柱電極21a的開口部21d係形成於位障金屬21b的中部上，足夠讓全部焊料22之錫(Sn)改變成化合物23 的銅(Cu)量可根據連結條件(例如連結期間之溫度或時間)而從柱電極21a供給。因此，其中全部焊料22之錫(Sn)皆改變成化合物23的連結部可連結彼此相對的柱電極21a，如此，諸如由連結部內剩餘焊料22的擴散所造成的孔隙或斷裂部生成問題也可於連結後於加熱環境中加以遏止。
前述端子20B係設於電子組件1B上以具現其中電子組件 1B係以高可信度連接的電子設備。又復，於電子設備中，全部焊料22之錫(Sn)可不必要皆改變成化合物以形成如圖13D所例示之連結態，而可改變成化合物以形成如圖13B及圖13C所例示之連結態。於具有如圖13B及圖13C所例示之連結態的電子設備中，錫(Sn)之擴散至柱電極21a側面及連結部的斷裂可被遏止，原因在於錫(Sn)優先擴散至開口部21d的柱電極21a，及於化合物23形成期間體積縮小故。
雖然設有端子20B的電子組件1B間之連結係藉舉例說 明，但當設有端子20B的電子組件1B與設有與端子20B不同結構的一端子之其它電子組件連結時也可獲得前述效果。
圖14為依據第二實施例該等端子間之連結的另一範例之解說圖。於圖14A之範例中，電子組件1B連結與電子組件1A相異的一電子組件300。該電子組件300係設有端子310包括柱電極21a及位障金屬21b(例如不包括開口部21d)。在連結電子組件1A的端子20B與電子組件300的端子310間也產生焊料22的錫(Sn)優先擴散至開口部21d的柱電極21a，及隨著化合物23之形成的體積縮小。因此，錫(Sn)之擴散至柱電極21a側面及柱電極21a間之連結部的斷裂可被遏止。
於圖14B之範例中，電子組件1B係連結與電子組件1B不同的一電子組件320。該電子組件320係設有端子330(例如柱電極、位障 金屬及佈線部)。焊料22的錫(Sn)優先擴散至開口部21d的柱電極21a，及隨著化合物23之形成的體積縮小也產生在電子組件1A的端子20B與電子組件320之端子330間。據此，錫(Sn)之優先擴散至柱電極21a的側表面或端子330，及柱電極21a間之連結部的斷裂可被遏止。
如前文描述端子20B係設於電子組件1B上以具現其中電 子組件1B與其它電子組件係以高可信度連結的電子設備。其次將說明依據如前文描述之第二實施例形成端子20B之方法。又復，第一實施例中描述圖7A至圖7C之方法可與於依據第二實施例形成端子20B之方法相同。此處，圖7C處理後之處理將參考圖15及圖16作說明。
圖15及圖16為依據第二實施例一種端子形成方法之一範 例的解說圖。於一個端子形成方法之各個製程中主部的剖面圖係圖解例示於圖15及圖16。首先，在執行圖7A至圖7C之處理後，如圖15A所例示，剝除用以形成柱電極21a的光阻31。
隨後，光阻31經塗覆，在光阻31上進行曝光製程及顯影製 程，以形成覆蓋柱電極21a之周邊部及中部的一光阻34，而形成在柱電極21a上有平面圈餅形的一開口部34a。舉例言之，在柱電極21a中部形成具有10微米直徑的開口部31a。
隨後，使用電解鍍覆法，如圖15C所例示，在柱電極21a 上在開口部34a內部形成位障金屬21b。舉例言之，具有3微米高度(厚度)的鎳(Ni)層作為位障金屬21b係形成於柱電極21a上。
如圖15D所例示，在形成位障金屬21b之後剝除光阻34。 據此，其上位障金屬21b具有形成在位中部的該開口部21d的電極部21係形成於柱電極21a上。
隨後，如圖16A所例示，光阻材料係經塗覆，在光阻材料 上執行曝光處理及顯影處理以形成在電極部21的一區上有一開口部35a的一光阻35。隨後，使用電解鍍覆法，如圖16B所例示，在光阻33的開口部33a內部之開口部21d及位障金屬21b的柱電極21a上形成焊料22。例如，形成具有3.5微米厚度之錫-銀(Sn-Ag)焊料作為焊料22。
在焊料22形成後，剝除光阻35，及如圖16C所例示，在剝 除光阻35後暴露出的晶種層30b及黏著層30a藉蝕刻去除。然後，如圖16D所例示，進行再流處理以形成具有圓化形狀的焊料22。又，可刪除圖16D之再流處理。
其中形成焊料22以覆蓋形成於柱電極21a上方的位障金屬 21b及形成於位障金屬21b上的開口部21d之柱電極21a的端子20A係根據圖7A至圖7C及圖15A至圖15D之方法製成。
位障金屬21b之開口部21d的直徑可能無需以高精度控 制。當形成到達柱電極21a的開口部21d時，錫(Sn)擴散至柱電極21a的側表面及連結期間之連結部的斷裂可被遏止。又復，當形成到達柱電極21a的開口部21d時，因化合物23形成期間銅(Cu)係從柱電極21a供給，故焊料22的全部錫(Sn)皆可改變成化合物23。
又，前述端子20B可製作成當從頂面觀看時具有圓形或實 質上圓形。此外，端子20B可製作成當從頂面觀看時具有橢圓形形狀或實質上橢圓形形狀、四邊形形狀或實質上四邊形形狀、或三角形形狀或實質上三角形形狀。
又復，如前文描述，雖然開口部21d係形成於端子20B的 位障金屬21b之中部上，開口部21d可不形成於位障金屬21b的中部上。即便當開口部21d係形成於外側而非形成於位障金屬21b的中 部，仍可獲得焊料22的錫(Sn)優先擴散至開口部21d的柱電極21a，及連結期間連結部的體積收縮。據此，錫(Sn)擴散至例如柱電極21a的側表面及連結部的斷裂可被遏止。
又，如前文描述，端子20B包括銅(Cu)製柱電極21a。此處， 除了純銅(Cu)製的柱電極21a外，銅(Cu)製的柱電極21a包括其主要成分為銅(Cu)的柱電極21a。除了純鎳(Ni)製的位障金屬21b外，鎳(Ni)製的位障金屬21b包括其主要成分為鎳(Ni)的位障金屬21b。
又復，用在柱電極21a及位障金屬21b的材料組合並不限於 如前文描述銅(Cu)(例如包括其主要成分為銅(Cu)的材料)及鎳(Ni)(例如包括其主要成分為鎳(Ni)的材料)的組合。用在焊料22的材料之一成分須具有一擴散係數其針對柱電極21a為較大，而針對位障金屬21b為較小。
其次將描述第三實施例。圖17為例示依據第三實施例的一 示範端子之一視圖。圖17A為例示依據第三實施例設有該端子之電子組件的一範例之主部的一平面圖。圖17B為例示依據第三實施例設有該端子之電子組件的一範例之主部的一剖面圖。圖17B為沿圖17A之線L3-L3所取的剖面圖。為求方便部分焊料未例示於圖17A。
圖17A及圖17B所例示的電子組件1C設有一端子20C從設 在主體部10上的佈線部10a凸起。又復，為求方便單一端子20C例示於圖17A，但複數個端子20C可設在主體部10上。
端子20C包括一電極部21及形成於電極部21上的一焊料 22(例如焊料部)。電極部21包括設在佈線部10a上的一柱電極21a(例如傳導部)、設在柱電極21a上的一位障金屬21b(例如傳導部)。到達位障金屬21b下方的柱電極21a之一開口部21d係形成於位障金屬21b 上。於本範例中，開口部21d係形成於位障金屬21b中部上。設在開口部21d的柱電極21a上及藉穿透位障金屬21b而從位障金屬21b凸起的凸部21e係形成於端子20C之電極部21上。與含在焊料22的預定成分反應以形成一化合物之材料係用在凸部21e。焊料22係形成以覆蓋位障金屬21b及凸部21e。
具有錫(Sn)作為主成分的材料係用於焊料22。舉例來說， 諸如銅(Cu)之材料係用在電極部21之柱電極21a。含在焊料22中的一成分亦即於本範例中，具有相對於錫(Sn)的擴散係數不同的擴散係數之材料係用於電極部21的位障金屬21b及凸部21e。此處，具有相對於錫(Sn)的擴散係數係低於凸部21e的擴散係數之材料係用於位障金屬21b。例如鎳(Ni)層係用在位障金屬21b及例如銅(Cu)係用在凸部21e。後文中將舉例說明使用前述材料的端子20C。
如前文描述，於端子20C中，一開口部21d係形成於鎳(Ni) 製位障金屬21b，及藉穿透位障金屬21b到達位障金屬21b下方的銅(Cu)製柱電極21a而從銅(Cu)製成的凸部21e形成凸起的該凸部21e。 如前文描述，該位障金屬21b及具有相對於錫(Sn)更高擴散係數的銅(Cu)製凸部21e係暴露於電極部21d頂面上，及位障金屬21b及凸部21e係以焊料22覆蓋。據此，當電子組件1C與其它電子組件連結時，焊料22的錫(Sn)優先擴散至且與開口部21d的凸部21e或位障金屬21b下方的柱電極21a起反應。因而可遏止錫(Sn)之擴散至柱電極21a之側面。
圖18為例示依據第三實施例該等端子間之連結的一範例 的一視圖。此處，將舉例說明如圖17所例示在設有端子20C的電子組件1C間之連結。圖18A至圖18D例示於連結處理期間電子組件1C之一 範例的主部的剖面圖。
端子20C設有事先欲連接的電子組件1C的相對應位置 上。當端子20C彼此連結時，如圖18A所例示，在設有端子20C的電子組件1C中，端子20C首先係配置成彼此面對面。
隨後，如圖18B所例示，當於焊料22之熔點或更高溫度加 熱時，藉加壓電子組件1C，電子組件1C的於其上形成位障金屬21b及凸部21e之該等柱電極21a係彼此連結成焊料22係插置於凸部21e間。於此種情況下，含在焊料22的錫(Sn)優先擴散且與接觸焊料22的開口部21d的鎳(Ni)製位障金屬21b及銅(Cu)製凸部21e中之具有較高擴散係數的銅(Cu)製凸部21c起反應以形成一化合物23。隨著焊料22之錫(Sn)與凸部21e之銅反應之進行，化合物23持續生長，如圖18C所例示。化合物23之生長也進行至開口部21d內部的凸部21e及開口部21d附近的柱電極21a。
如圖18C所例示，當化合物23生長時，隨著化合物的生 長，晶體緻密排列，因而出現柱電極21a(位障金屬21b間)間之連結部的體積縮小。如圖13C及進一步如圖13D所例示，隨著化合物23之生長，當開口部21e形成於位障金屬21b的中部上時，柱電極21a間連結部的體積縮小朝向位障金屬21b中部進行。
如前文描述，到達銅(Cu)製柱電極21a的銅(Cu)製凸部21e 係形成於鎳(Ni)製位障金屬21b之中部上，焊料22的錫(Sn)優先擴散至且與凸部21e或連結至凸部21e的柱電極21a反應以形成化合物23。又復，當形成化合物23時，在柱電極21a間之連結部出現體積收縮。據此，藉中止在相對柱電極21a間之部分之焊料22的擴散流，可遏止焊料22沿位障金屬21b之側面擴散至柱電極21a之側面。又復， 焊料22與柱電極21a的過度反應藉位障金屬21b遏止。結果，於兩相對柱電極21a間之連結部中之焊料22減少，如此，可遏止斷裂部之生成。
其中到達柱電極21a的凸部21e係形成於位障金屬21b的中 部上的該端子20C中，凸部21e的大小可調整為銅(Cu)含量係足夠讓焊料22的全部錫(Sn)皆改變成化合物23。又復，於端子20C中，即便在凸部21e的全部銅(Cu)皆消耗在與焊料22的錫(Sn)形成化合物23，仍可從柱電極21a供給足夠將焊料22的全部錫(Sn)皆改變成化合物23的銅(Cu)量。依據端子20C，柱電極21a可與連結部連結，於其中焊料22的全部錫(Sn)皆改變成化合物23。因此，於連結後在加熱環境中，諸如由焊料22擴散所造成的孔隙或斷裂部的生成問題也可被遏止。
如前文描述端子20C係設於電子組件1C上以具現其中電 子組件1C與其它電子組件係以高可信度連結的電子設備。又，於電子設備中，焊料22並非必要全部皆改變成化合物以形成如圖18D所例示之連結態，而可改變成化合物以形成如圖18B及圖18C所例示之連結態。於具有如圖18B及圖18C所例示之連結態的電子設備中，當於後來加熱時，錫(Sn)之擴散至柱電極21a之側面及連結部的斷裂可被遏止，原因在於錫(Sn)之優先擴散至凸部21e及於化合物23形成期間之體積收縮之故。
雖然以設有端子20C的電子組件1C間之連結舉例說明，但 當設有端子20C的電子組件1C與設有與端子20C不同結構的一端子之其它電子組件連結時也可獲得前述效果。
圖19為依據第三實施例該等端子間之連結的另一範例之 解說圖。於圖19A之範例中，電子組件1C連結與電子組件1C相異的一電子組件300。該電子組件300係設有端子310包括柱電極21a及位障金屬21b(例如不包括開口部21d)。類似前文描述，在連結電子組件1C的端子20C與電子組件300的端子310間也產生焊料22的錫(Sn)優先擴散至凸部21e及進一步擴散至連結至凸部21e的柱電極21a，及隨著化合物23之形成的體積縮小。因此，錫(Sn)之擴散至柱電極21a側面及柱電極21a間之連結部的斷裂可被遏止。
於圖19B之範例中，電子組件1C係連結與電子組件1C不同 的一電子組件320。該電子組件320係設有端子330(例如柱電極、位障金屬及佈線部)。焊料22的錫(Sn)優先擴散至凸部21e及進一步擴散至連結至凸部21e的柱電極21a，及隨著化合物23之形成的體積縮小也產生在電子組件1C的端子20C與電子組件320之端子330間。據此，錫(Sn)之優先擴散至柱電極21a的側表面或端子330，及柱電極21a間之連結部的斷裂可被遏止。
如前文描述端子20C係設於電子組件1C上以具現其中電子 組件1C與其它電子組件係以高可信度連結的電子設備。其次將說明依據如前文描述之第三實施例形成端子20C之方法。又復，第二實施例中描述圖7A至圖7C及圖15A至圖15D之方法可與於依據第三實施例形成端子20C之方法相同。此處，圖15D處理後之處理將參考圖20及圖21作說明。
圖20至圖21為依據第三實施例一種端子形成方法之範例 的解說圖。於端子形成方法之各個製程中的主部之剖面圖係圖解例示於圖20及圖21。首先，於執行圖7A至圖7C及圖15A至圖15D之處理後，塗覆光阻材料，在該光阻材料上進行曝光製程及顯影製程以形 成一光阻36，在位障金屬21b之該開口部21d的位置上具有一開口部36a，如圖20A所例示。圖20A例示於該處形成如一範例的光阻36之一種情況，該光阻36具有開口部36a，其直徑係大於位障金屬21b之該開口部21d的直徑。
隨後，使用電解鍍覆法，如圖20B所例示，凸部21e係形成 在位障金屬21b之該開口部21d內部的柱電極21a上。例如，形成具有距開口部21d為2微米之高度(厚度)之一銅(Cu)層作為凸部21e。
如圖20C所例示，在形成凸部21e之後剝除光阻36。據此， 具有開口部21d形成於中部上的位障金屬21b係形成於柱電極21a上，連結至柱電極21a的凸部21e係形成於開口部21d上以形成該電極部21。
隨後，如圖20D所例示，光阻材料經塗覆，及在該光阻材 料上進行曝光製程及顯影製程以形成電極部21之具有一開口部37a的一光阻37。隨後如圖21A所例示，使用電解鍍覆法，焊料22係形成於光阻37的該開口部37a內部的凸部21e及位障金屬21b上。舉例言之，形成具有3.5微米厚度之錫-銀(Sn-Ag)焊料。
形成焊料22後，光阻37被剝除如圖21B所例示，及於光阻 37被剝除後暴露出的晶種層30b及黏著層30a係藉蝕刻去除，如圖21C所例示。然後執行再流處理以形成具有圓化形狀的焊料22，如圖21D所例示。又可刪除圖21D之再流處理。
依據如前文描述之圖7A至圖7C、圖15A至圖15D及圖20A 至圖20D之處理程序，形成端子20C，其中形成焊料22以覆蓋形成於柱電極21a及凸部21e上的位障金屬21b，該凸部21e藉穿過位障金屬21b而到達柱電極21a。
於圖20A之製程中形成的光阻36之開口部36a之直徑可製 作成大於以及小於位障金屬21b之該開口部21d的直徑。即便於一種情況下，於該處開口部36a具有該直徑以在開口部36a上形成凸部21e，當該凸部21e係經由位障金屬21b之該開口部21d而連接至柱電極21a時，錫(Sn)之擴散至柱電極21a側面及連結期間連結部的斷裂可被遏止。又復，於化合物23之形成期間銅(Cu)係從柱電極21a供給，因此，焊料22的全部錫(Sn)皆改變成化合物23。
又，前述端子20C可製作成當從頂面觀看時具有圓形或實 質上圓形。此外，端子20C可製作成當從頂面觀看時具有橢圓形形狀或實質上橢圓形形狀、四邊形形狀或實質上四邊形形狀、或三角形形狀或實質上三角形形狀。
又復，如前文描述，雖然開口部21d及凸部21e係形成於端 子20C的位障金屬21b之中部上，開口部21d及凸部21e可不形成於位障金屬21b的中部上。即便當開口部21d及凸部21e係形成於外側而非形成於位障金屬21b的中部，仍可獲得焊料22的錫(Sn)優先擴散至凸部21e及凸部21e下方的柱電極21a，及連結期間連結部朝向凸部21e的體積收縮。據此，錫(Sn)擴散至例如柱電極21a的側表面及連結部的斷裂可被遏止。
又，如前文描述，端子20C包括銅(Cu)製柱電極21a、鎳(Ni) 製位障金屬21b、銅(Cu)製凸部21e作為元件。此處，除了純銅(Cu)製的柱電極21a及銅(Cu)製凸部21e外，銅(Cu)製的柱電極21a及銅(Cu)製凸部21e包括其主要成分為銅(Cu)的柱電極21a及凸部21e。除了純鎳(Ni)製的位障金屬21b外，鎳(Ni)製的位障金屬21b包括其主要成分為鎳(Ni)的位障金屬21b。
又復，用在柱電極21a、凸部21e及位障金屬21b的材料組 合並不限於如前文描述銅(Cu)(例如包括其主要成分為銅(Cu)的材料)及鎳(Ni)(例如包括其主要成分為鎳(Ni)的材料)的組合。用在焊料22的材料之一成分須具有一擴散係數其針對柱電極21a及凸部21e為較大，而針對位障金屬21b為較小。
當依據如前文描述之第一至第三實施例形成端子20A、 20B、20C時，於圖9D、圖16D、圖21D之再流處理中可在電極部21與焊料22間形成一化合物。
圖22為例示再流處理之另一範例的一視圖。該再流處理之 端子20A、20B、20C的其它範例之主部的剖面圖分別地係圖解例示於圖22A、圖22B、圖22C。
於圖9D之再流製程中例如圖22A所例示，一化合物(例如 銅-錫(Cu-Sn)化合物)23A可形成於凸部21c表面上。又，一化合物(例如鎳-錫(Ni-Sn)化合物)可連同化合物23A形成於位障金屬21b之表面上。
於圖16D之再流製程中例如圖22B所例示，一化合物(例如 銅-錫(Cu-Sn)化合物)23B可形成於形成在位障金屬21b上的開口部21d之柱電極21a表面上。又，一化合物(例如鎳-錫(Ni-Sn)化合物)可連同化合物23B形成於位障金屬21b之表面上。
於圖21D之再流製程中例如圖22C所例示，一化合物(例如 銅-錫(Cu-Sn)化合物)23C可形成於凸部21e表面上。又，一化合物(例如鎳-錫(Ni-Sn)化合物)可連同化合物23C形成於位障金屬21b之表面上。
於圖10D及圖11D之再流製程中當形成端子20Aa、20Ab 時，類似端子20A之情況，一化合物也可形成於電極部21與焊料22間。
其次將描述第四實施例。此處，將描述一連結構件(例如 一電子設備)其中設有第一實施例描述的端子之電子組件與其它電子組件連結，及該連結構件之評估結果。
為了用於評估，具有13毫米x10毫米晶片大小的一半導體 晶片及具有10微米直徑及50微米端子間距的一端子係用作為電子組件。使用一端子其中形成7微米高度之鎳(Ni)層，厚3微米之銅(Cu)層係形成於鎳(Ni)層中部上，及厚5微米之錫-銀(Sn-Ag)製成的焊料層係形成於銅(Cu)層上。前述端子係用作為連結構件之下半導體晶片的端子。其中形成高10微米之銅(Cu)層及在該銅(Cu)層上形成厚5微米之錫-銀(Sn-Ag)製成的焊料層的一端子係用作為連結構件之上半導體晶片的端子。假設一連結構件其中如前述該上及下半導體晶片的端子彼此連結者係作為一實施例。
又，為了用於比較，設有一端子其中形成7微米高度之銅 (Cu)層，厚3微米之鎳(Ni)層係形成於銅(Cu)層上，及厚5微米之錫-銀(Sn-Ag)製成的焊料層係形成於鎳(Ni)層上的一半導體晶片係用作為該連結構件的下半導體晶片。設有一端子其中形成高10微米之銅(Cu)層及在該銅(Cu)層上形成厚5微米之錫-銀(Sn-Ag)製成的焊料層的一半導體晶片係用作為該連結構件之上半導體晶片。假設一連結構件其中如前述該上及下半導體晶片的端子彼此連結者係作為一比較例。
比較例及實施例中之任一者係根據一流程製造，容後詳述。換言之，一助熔劑係塗覆在該上及下半導體晶片中之至少一者 的端子上，及然後，該上及下半導體晶片係製作成使用覆晶連結劑而彼此排齊相對。然後該上及下半導體晶片於300℃之頭溫加熱例如10秒以熔解焊料層，藉此連結該上及下半導體晶片之端子彼此。就如前述製造的連結構件進行橫切，及使用電子探頭微分析儀(EPMA)進行元素分析用於評估。
圖23為例示評估結果之一範例的一圖。又復，使用EPMA 之元素分析範例係圖解例示於圖23。圖23例示如前述製造的實施例之連結構件的該等端子間之連結部50、比較例之連結構件的該等端子間之連結部60、及該等端子間之連結部50、60之銅(Cu)、鎳(Ni)及錫(Sn)各個元素之元素分析。
實施例的該等端子間之連結部50包括形成於底部之一鎳 (Ni)層51、形成於鎳(Ni)層51上之一銅(Cu)層52、形成於頂部之一銅(Cu)層53，及含有焊料成分之一連結層54。比較例的該等端子間之連結部60包括形成於底部之一銅(Cu)層61、部分形成於銅層61上之一鎳(Ni)層62、形成於頂部之一銅(Cu)層63，及含有焊料成分之一連結層64。孔隙(例如孔隙部64a)係形成於比較例的該等端子間之連結部60內的連結層64中，而實施例的該等端子間之連結部50內的該連結層54則係具有實質上緊密結構。
從圖23之銅(Cu)及鎳(Ni)的分析結果，在比較例的該等端 子間之連結部60中，含銅(Cu)之連結層64係形成於下銅(Cu)層61上的該鎳(Ni)層62與上銅(Cu)層63間。從圖23之錫(Sn)的分析結果，連結層64含有錫(Sn)，及錫(Sn)係擴散至下鎳(Ni)層62(擴散部64b)的側面或擴散至下鎳(Ni)層62下方之該銅(Cu)層6的側面。
從圖23之銅(Cu)及鎳(Ni)的分析結果，在實施例的該等端 子間之連結部50中，含銅(Cu)之連結層54係形成於下鎳(Ni)層51上的銅(Cu)層52與上銅(Cu)層53間。從圖23之錫(Sn)的分析結果，連結層54含有錫(Sn)。在比較例的該等端子間之連結部60中所見的錫(Sn)之擴散至鎳(Ni)層51的側面未曾形成於實施例的該等端子間之連結部50。在實施例的該等端子間之連結部50中，可謂錫(Sn)之擴散至鎳(Ni)層51的側面受遏止，原因在於錫(Sn)擴散至鎳(Ni)層51上的銅(Cu)層52，及體積朝向銅層52收縮故。
如前文描述，包括一電極部及於該電極部上的一焊料部之 一端子係用作為該電子組件諸如半導體晶片的端子。於該端子中，具有相對於焊料部的一成分之擴散係數的傳導部係形成於該電極部之頂面上，及形成焊料部以覆蓋該等傳導部。使用前述端子使得當電子組件彼此連結時，該焊料部的該成分優先地擴散入針對該成分具有較高擴散係數的傳導部，及出現經由該焊料部的該成分之優先擴散所造成的化合物體積收縮之效果，藉此遏止該焊料部的該成分擴散至該電極部側面。據此，在電子組件彼此連結的連結部之斷裂的產生獲得遏止，如此，可具現電子組件以高可信度彼此連結的一種電子設備。
於前文描述中舉例說明一種結構，其中相對於焊料22之該 成分具有不同擴散係數的兩種傳導部(例如銅(Cu)及鎳(Ni))係形成於電極部21頂面上，及焊料22係形成於傳導部上。此外，當一端子係組配成具有一種結構其中三或更多種傳導部係形成於電極部21頂面上時，此等傳導部中之至少二者係製作成相對於焊料22之該成分具有不同擴散係數的傳導部，及焊料22係形成於傳導部上，可獲得前文描述的相同效果。
又，電子組件諸如半導體晶片間之連結係舉例說明於前文 描述。但前述端子結構可應用至一種情況於該處電子組件與電子組件以外的一組件係彼此連結，也可應用至一種情況於該處電子組件以外的該等組件係彼此連結。舉例言之，當該等組件係以焊料連結時，銅(Cu)之一金屬層及形成於該金屬層上的鎳(Ni)之一位障層係形成於一表面上，於其上兩個組件彼此連結。又，依據該等電子組件之該端子之該範例，位障層上銅(Cu)之一凸部、位障層中之一開口部、或形成於位障層中之一開口部內的銅(Cu)之一凸部係形成於該等電子組件中之至少一者上。前述該等組件係使用焊料彼此連結，因而遏止該等組件間之連結部中焊料的減少及連結部的斷裂。據此，該等組件可以高度可密封性彼此連結。
100‧‧‧半導體裝置
110‧‧‧半導體晶片
111‧‧‧連接端子
120‧‧‧電路基體
121‧‧‧傳導部
121a‧‧‧電極端子
122‧‧‧絕緣部
123‧‧‧外部連接端子
130‧‧‧底填補材料

Claims (14)

  1. 一種電子組件，其包含：一電極部；以及形成於該電極部上的一焊料部，其中，該電極部包括設置在一第二傳導部之外側的一第一傳導部，且該第一傳導部之相對於該焊料部之成分的擴散係數小於該第二傳導部之相對於該焊料部之該成分的擴散係數，其中，該焊料部係形成於該第一傳導部和該第二傳導部上，並且其中，該第二傳導部之體積大小足以與該焊料部之實質上全部的成分起反應。
  2. 如請求項1之電子組件，其中，該第二傳導部係部分地形成於該第一傳導部上的一傳導部。
  3. 如請求項1之電子組件，其中，該第一傳導部包括形成於該第二傳導部上以抵達該第二傳導部的一貫穿孔。
  4. 如請求項1之電子組件，其中，該電極部包括一第三傳導部，該第三傳導部所具有的相對於該焊料部之該成分的擴散係數大於該第一傳導部之相對於該焊料部之該成分的擴散係數，該第一傳導部包括形成於該第三傳導部上以抵達該第三傳導部的一貫穿孔，並且該第二傳導部係形成於該貫穿孔上。
  5. 一種電子組件製造方法，其包含下列步驟：製備一第一電子組件，該第一電子組件包括一第一電極部與 形成於該第一電極部上的一焊料部，其中，該第一電極部包括設置在一第二傳導部之外側的一第一傳導部，該第一傳導部之相對於該焊料部之成分的擴散係數小於該第二傳導部之相對於該焊料部之該成分的擴散係數，並且該焊料部係形成於該第一傳導部和該第二傳導部上；製備設有一第二電極部的一第二電子組件；以及以使得該第一電子組件與該第二電子組件相對且該等第一與第二電子組件被以該焊料部之熔點以上的溫度加熱的方式來連結該第一電極部與該第二電極部，其中，該第二傳導部之體積大小足以與該焊料部之實質上全部的成分起反應。
  6. 如請求項5之製造方法，其中，連結該第一電極部與該第二電極部之步驟包括：形成含有該焊料部之成分與該第二傳導部之成分的一化合物。
  7. 如請求項5之製造方法，其中，該第二傳導部係部分地形成於該第一傳導部上。
  8. 如請求項5之製造方法，其中，該第一傳導部包括形成於該第二傳導部上以抵達該第二傳導部的一貫穿孔。
  9. 如請求項5之製造方法，其中，該第一電極部包括一第三傳導部，該第三傳導部所具有的相對於該焊料部之該成分的擴散係數大於該第一傳導部之相對於該焊料部之該成分的擴散係數，該第一傳導部包括形成於該第三傳導部上以抵達該第三傳導部的一貫穿孔，並且該第二傳導部係形成於該貫穿孔上。
  10. 一種電子設備，其包含：設有一第一電極部的一第一電子組件；設有一第二電極部的一第二電子組件，該第二電極部被配置成與該第一電極部相對；以及連結該第一電極部與該第二電極部的一連結部，其中，該連結部含有一焊料部，該第一電極部設有設置在一第二傳導部之外側的一第一傳導部，該第一傳導部之相對於該焊料部之成分的擴散係數小於該第二傳導部之相對於該焊料部之該成分的擴散係數，該焊料部係形成於該第一傳導部和該第二傳導部上，並且該第二傳導部之體積大小足以與該焊料部之實質上全部的成分起反應。
  11. 如請求項10之電子設備，其中，該連結部包括一化合物，該化合物含有該焊料部之該成分及與該第二傳導部之成分相同的一成分。
  12. 如請求項10之電子設備，其中，該第二傳導部係部分地形成於該第一傳導部上。
  13. 如請求項10之電子設備，其中，該第一傳導部包括形成於該第二傳導部上以抵達該第二傳導部的一貫穿孔。
  14. 如請求項10之電子設備，其中，該第一電極部包括一第三傳導部，該第三傳導部所具有的相對於該焊料部之該成分的擴散係數大於該第一傳導部之相對於該焊料部之該成分的擴散係數，該第一傳導部包括形成於該第三傳導部上以抵達該第三傳 導部的一貫穿孔，並且該第二傳導部係形成於該貫穿孔上。
TW102140135A 2012-12-06 2013-11-05 電子組件、包含其之電子設備及該電子設備之製造方法 TWI505424B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012267528A JP2014116367A (ja) 2012-12-06 2012-12-06 電子部品、電子装置の製造方法及び電子装置

Publications (2)

Publication Number Publication Date
TW201428918A TW201428918A (zh) 2014-07-16
TWI505424B true TWI505424B (zh) 2015-10-21

Family

ID=50862584

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102140135A TWI505424B (zh) 2012-12-06 2013-11-05 電子組件、包含其之電子設備及該電子設備之製造方法

Country Status (5)

Country Link
US (1) US20140159235A1 (zh)
JP (1) JP2014116367A (zh)
KR (1) KR101594220B1 (zh)
CN (1) CN103855116B (zh)
TW (1) TWI505424B (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016213238A (ja) * 2015-04-30 2016-12-15 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
JP6593208B2 (ja) * 2016-02-03 2019-10-23 富士通株式会社 半導体装置及び半導体装置の製造方法
US10276539B1 (en) * 2017-10-30 2019-04-30 Micron Technology, Inc. Method for 3D ink jet TCB interconnect control
JP7117615B2 (ja) * 2017-12-08 2022-08-15 パナソニックＩｐマネジメント株式会社 半導体装置の製造方法
US11145612B2 (en) * 2017-12-28 2021-10-12 Texas Instruments Incorporated Methods for bump planarity control
US20190259722A1 (en) * 2018-02-21 2019-08-22 Rohm And Haas Electronic Materials Llc Copper pillars having improved integrity and methods of making the same
CN110690130A (zh) * 2019-09-24 2020-01-14 浙江集迈科微电子有限公司 一种三维异构堆叠方法
CN110690131B (zh) * 2019-09-24 2021-08-31 浙江集迈科微电子有限公司 一种具有大键合力的三维异构焊接方法
CN110739236A (zh) * 2019-09-27 2020-01-31 浙江大学 一种具有防溢锡结构的新三维异构堆叠方法
JP7414563B2 (ja) * 2020-02-04 2024-01-16 ラピスセミコンダクタ株式会社 半導体装置
US20230110154A1 (en) * 2020-03-26 2023-04-13 Rohm Co., Ltd. Semiconductor device
US11721656B2 (en) 2021-08-23 2023-08-08 Qualcomm Incorporated Integrated device comprising pillar interconnect with cavity

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050001313A1 (en) * 2002-11-12 2005-01-06 Siliconware Precision Industries Co., Ltd. Semiconductor device with under bump metallurgy and method for fabricating the same
US20110006415A1 (en) * 2009-07-13 2011-01-13 Lsi Corporation Solder interconnect by addition of copper
US20120009783A1 (en) * 2007-09-21 2012-01-12 Stats Chippac, Ltd. Solder Bump With Inner Core Pillar in Semiconductor Package

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09205096A (ja) * 1996-01-24 1997-08-05 Toshiba Corp 半導体素子およびその製造方法および半導体装置およびその製造方法
JP2002261111A (ja) * 2001-03-06 2002-09-13 Texas Instr Japan Ltd 半導体装置及びバンプ形成方法
TWI245402B (en) * 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
US6740577B2 (en) * 2002-05-21 2004-05-25 St Assembly Test Services Pte Ltd Method of forming a small pitch torch bump for mounting high-performance flip-flop devices
JP4718809B2 (ja) * 2004-08-11 2011-07-06 ローム株式会社 電子装置およびそれを用いた半導体装置、ならびに半導体装置の製造方法
TWI244152B (en) * 2004-10-22 2005-11-21 Advanced Semiconductor Eng Bumping process and structure thereof
TWI252546B (en) * 2004-11-03 2006-04-01 Advanced Semiconductor Eng Bumping process and structure thereof
JP5535448B2 (ja) * 2008-05-19 2014-07-02 シャープ株式会社 半導体装置、半導体装置の実装方法、および半導体装置の実装構造
US8736050B2 (en) * 2009-09-03 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Front side copper post joint structure for temporary bond in TSV application
US8592995B2 (en) * 2009-07-02 2013-11-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method and structure for adhesion of intermetallic compound (IMC) on Cu pillar bump
US8299616B2 (en) * 2010-01-29 2012-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. T-shaped post for semiconductor devices
KR101119839B1 (ko) * 2010-05-23 2012-02-28 주식회사 네패스 범프 구조물 및 그 제조 방법
US8241963B2 (en) * 2010-07-13 2012-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Recessed pillar structure
US8409979B2 (en) * 2011-05-31 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming interconnect structure with conductive pads having expanded interconnect surface area for enhanced interconnection properties
US8587120B2 (en) * 2011-06-23 2013-11-19 Stats Chippac, Ltd. Semiconductor device and method of forming interconnect structure over seed layer on contact pad of semiconductor die without undercutting seed layer beneath interconnect structure
TWI467718B (zh) * 2011-12-30 2015-01-01 Ind Tech Res Inst 凸塊結構以及電子封裝接點結構及其製造方法
US9425136B2 (en) * 2012-04-17 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Conical-shaped or tier-shaped pillar connections
US8970035B2 (en) * 2012-08-31 2015-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structures for semiconductor package

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050001313A1 (en) * 2002-11-12 2005-01-06 Siliconware Precision Industries Co., Ltd. Semiconductor device with under bump metallurgy and method for fabricating the same
US20120009783A1 (en) * 2007-09-21 2012-01-12 Stats Chippac, Ltd. Solder Bump With Inner Core Pillar in Semiconductor Package
US20110006415A1 (en) * 2009-07-13 2011-01-13 Lsi Corporation Solder interconnect by addition of copper

Also Published As

Publication number Publication date
US20140159235A1 (en) 2014-06-12
TW201428918A (zh) 2014-07-16
CN103855116B (zh) 2017-04-12
KR101594220B1 (ko) 2016-02-15
JP2014116367A (ja) 2014-06-26
CN103855116A (zh) 2014-06-11
KR20140073419A (ko) 2014-06-16

Similar Documents

Publication Publication Date Title
TWI505424B (zh) 電子組件、包含其之電子設備及該電子設備之製造方法
US11999001B2 (en) Advanced device assembly structures and methods
CN102810522B (zh) 封装结构和方法
TWI493672B (zh) 半導體裝置、電子裝置及半導體裝置之製造方法
JP7032212B2 (ja) 配線基板、半導体パッケージ及び配線基板の製造方法
TW200926379A (en) Package substrate having electrical connecting structure and method of fabricating the same
JP6524724B2 (ja) 電子装置及びその製造方法
TW201944505A (zh) 配線基板、半導體裝置及配線基板的製造方法
JP6191121B2 (ja) 電子部品、電子部品の製造方法及び電子装置の製造方法
JP6702108B2 (ja) 端子構造、半導体装置、電子装置及び端子の形成方法
US7494924B2 (en) Method for forming reinforced interconnects on a substrate
TW200409575A (en) Fine pad pitch organic circuit board with plating solder and method for fabricating the same
JP3703807B2 (ja) 半導体装置
WO2020137025A1 (ja) 電子制御装置
JP6822038B2 (ja) 半導体装置の製造方法
JP2023002217A (ja) 配線基板
JP2023152527A (ja) 配線基板及び配線基板の製造方法
JP2023064346A (ja) 配線基板、半導体装置及び配線基板の製造方法
JP2011044571A (ja) 半導体装置、外部接続端子、半導体装置の製造方法、及び外部接続端子の製造方法
JP2010010499A (ja) 半導体装置の製造方法
JP2017130616A (ja) 半導体装置、半導体装置の製造方法
JP2009295647A (ja) 回路基板の製造方法、及びその方法を適用した回路基板
JP2003168757A (ja) ピン付き配線基板およびこれを用いた電子装置
JP2016046286A (ja) 電子部品、電子部品の製造方法及び電子装置
JP2002289734A (ja) ピン付き配線基板およびこれを用いた電子装置

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees