TWI495007B - 元件形成用基板及其製造方法 - Google Patents

元件形成用基板及其製造方法 Download PDF

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Publication number
TWI495007B
TWI495007B TW101142609A TW101142609A TWI495007B TW I495007 B TWI495007 B TW I495007B TW 101142609 A TW101142609 A TW 101142609A TW 101142609 A TW101142609 A TW 101142609A TW I495007 B TWI495007 B TW I495007B
Authority
TW
Taiwan
Prior art keywords
substrate
film
oxide film
insulating film
forming
Prior art date
Application number
TW101142609A
Other languages
English (en)
Chinese (zh)
Other versions
TW201330097A (zh
Inventor
池田圭司
Original Assignee
東芝股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 東芝股份有限公司 filed Critical 東芝股份有限公司
Publication of TW201330097A publication Critical patent/TW201330097A/zh
Application granted granted Critical
Publication of TWI495007B publication Critical patent/TWI495007B/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1922—Preparing SOI wafers using silicon etch back techniques, e.g. BESOI or ELTRAN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
TW101142609A 2011-11-17 2012-11-15 元件形成用基板及其製造方法 TWI495007B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011251885A JP2013110161A (ja) 2011-11-17 2011-11-17 素子形成用基板及びその製造方法

Publications (2)

Publication Number Publication Date
TW201330097A TW201330097A (zh) 2013-07-16
TWI495007B true TWI495007B (zh) 2015-08-01

Family

ID=48429528

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101142609A TWI495007B (zh) 2011-11-17 2012-11-15 元件形成用基板及其製造方法

Country Status (4)

Country Link
US (1) US20140252555A1 (https=)
JP (1) JP2013110161A (https=)
TW (1) TWI495007B (https=)
WO (1) WO2013073468A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106463416A (zh) * 2014-06-13 2017-02-22 英特尔公司 用于晶圆键合的表面包封
CN106611740B (zh) * 2015-10-27 2020-05-12 中国科学院微电子研究所 衬底及其制造方法
US11502106B2 (en) * 2020-02-11 2022-11-15 Globalfoundries U.S. Inc. Multi-layered substrates of semiconductor devices

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200737403A (en) * 2006-01-23 2007-10-01 Soitec Silicon On Insulator A method of fabricating a composite substrate with improved electrical properties

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050252449A1 (en) * 2004-05-12 2005-11-17 Nguyen Son T Control of gas flow and delivery to suppress the formation of particles in an MOCVD/ALD system
JP4504390B2 (ja) * 2007-02-27 2010-07-14 株式会社東芝 相補型半導体装置
JP4768788B2 (ja) * 2008-09-12 2011-09-07 株式会社東芝 半導体装置およびその製造方法
JP2010232568A (ja) * 2009-03-29 2010-10-14 Univ Of Tokyo 半導体デバイス及びその製造方法
JP5235784B2 (ja) * 2009-05-25 2013-07-10 パナソニック株式会社 半導体装置
US8557679B2 (en) * 2010-06-30 2013-10-15 Corning Incorporated Oxygen plasma conversion process for preparing a surface for bonding
US8772873B2 (en) * 2011-01-24 2014-07-08 Tsinghua University Ge-on-insulator structure and method for forming the same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200737403A (en) * 2006-01-23 2007-10-01 Soitec Silicon On Insulator A method of fabricating a composite substrate with improved electrical properties

Also Published As

Publication number Publication date
JP2013110161A (ja) 2013-06-06
TW201330097A (zh) 2013-07-16
US20140252555A1 (en) 2014-09-11
WO2013073468A1 (ja) 2013-05-23

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