JP2013110161A - 素子形成用基板及びその製造方法 - Google Patents

素子形成用基板及びその製造方法 Download PDF

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Publication number
JP2013110161A
JP2013110161A JP2011251885A JP2011251885A JP2013110161A JP 2013110161 A JP2013110161 A JP 2013110161A JP 2011251885 A JP2011251885 A JP 2011251885A JP 2011251885 A JP2011251885 A JP 2011251885A JP 2013110161 A JP2013110161 A JP 2013110161A
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JP
Japan
Prior art keywords
substrate
film
insulating film
oxide film
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2011251885A
Other languages
English (en)
Japanese (ja)
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JP2013110161A5 (https=
Inventor
Keiji Ikeda
圭司 池田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
National Institute of Advanced Industrial Science and Technology AIST
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Institute of Advanced Industrial Science and Technology AIST filed Critical National Institute of Advanced Industrial Science and Technology AIST
Priority to JP2011251885A priority Critical patent/JP2013110161A/ja
Priority to PCT/JP2012/079110 priority patent/WO2013073468A1/ja
Priority to TW101142609A priority patent/TWI495007B/zh
Publication of JP2013110161A publication Critical patent/JP2013110161A/ja
Priority to US14/279,912 priority patent/US20140252555A1/en
Publication of JP2013110161A5 publication Critical patent/JP2013110161A5/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1922—Preparing SOI wafers using silicon etch back techniques, e.g. BESOI or ELTRAN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
JP2011251885A 2011-11-17 2011-11-17 素子形成用基板及びその製造方法 Pending JP2013110161A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2011251885A JP2013110161A (ja) 2011-11-17 2011-11-17 素子形成用基板及びその製造方法
PCT/JP2012/079110 WO2013073468A1 (ja) 2011-11-17 2012-11-09 素子形成用基板及びその製造方法
TW101142609A TWI495007B (zh) 2011-11-17 2012-11-15 元件形成用基板及其製造方法
US14/279,912 US20140252555A1 (en) 2011-11-17 2014-05-16 Substrate for forming elements, and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011251885A JP2013110161A (ja) 2011-11-17 2011-11-17 素子形成用基板及びその製造方法

Publications (2)

Publication Number Publication Date
JP2013110161A true JP2013110161A (ja) 2013-06-06
JP2013110161A5 JP2013110161A5 (https=) 2015-01-08

Family

ID=48429528

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011251885A Pending JP2013110161A (ja) 2011-11-17 2011-11-17 素子形成用基板及びその製造方法

Country Status (4)

Country Link
US (1) US20140252555A1 (https=)
JP (1) JP2013110161A (https=)
TW (1) TWI495007B (https=)
WO (1) WO2013073468A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170017880A (ko) * 2014-06-13 2017-02-15 인텔 코포레이션 웨이퍼 본딩을 위한 표면 캡슐화

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106611740B (zh) * 2015-10-27 2020-05-12 中国科学院微电子研究所 衬底及其制造方法
US11502106B2 (en) * 2020-02-11 2022-11-15 Globalfoundries U.S. Inc. Multi-layered substrates of semiconductor devices

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007201430A (ja) * 2006-01-23 2007-08-09 Soi Tec Silicon On Insulator Technologies Sa 電気特性を向上させた複合基板の作製方法
JP2008211052A (ja) * 2007-02-27 2008-09-11 Toshiba Corp 相補型半導体装置
JP2010067929A (ja) * 2008-09-12 2010-03-25 Toshiba Corp 半導体装置およびその製造方法
JP2010232568A (ja) * 2009-03-29 2010-10-14 Univ Of Tokyo 半導体デバイス及びその製造方法
JP2010272782A (ja) * 2009-05-25 2010-12-02 Panasonic Corp 半導体装置及びその製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050252449A1 (en) * 2004-05-12 2005-11-17 Nguyen Son T Control of gas flow and delivery to suppress the formation of particles in an MOCVD/ALD system
US8557679B2 (en) * 2010-06-30 2013-10-15 Corning Incorporated Oxygen plasma conversion process for preparing a surface for bonding
US8772873B2 (en) * 2011-01-24 2014-07-08 Tsinghua University Ge-on-insulator structure and method for forming the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007201430A (ja) * 2006-01-23 2007-08-09 Soi Tec Silicon On Insulator Technologies Sa 電気特性を向上させた複合基板の作製方法
JP2008211052A (ja) * 2007-02-27 2008-09-11 Toshiba Corp 相補型半導体装置
JP2010067929A (ja) * 2008-09-12 2010-03-25 Toshiba Corp 半導体装置およびその製造方法
JP2010232568A (ja) * 2009-03-29 2010-10-14 Univ Of Tokyo 半導体デバイス及びその製造方法
JP2010272782A (ja) * 2009-05-25 2010-12-02 Panasonic Corp 半導体装置及びその製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170017880A (ko) * 2014-06-13 2017-02-15 인텔 코포레이션 웨이퍼 본딩을 위한 표면 캡슐화
JP2017523588A (ja) * 2014-06-13 2017-08-17 インテル・コーポレーション ウェハ接合のための表面封入
KR102206378B1 (ko) * 2014-06-13 2021-01-22 인텔 코포레이션 웨이퍼 본딩을 위한 표면 캡슐화

Also Published As

Publication number Publication date
TW201330097A (zh) 2013-07-16
US20140252555A1 (en) 2014-09-11
TWI495007B (zh) 2015-08-01
WO2013073468A1 (ja) 2013-05-23

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