1279906 九、發明說明： 【發明所屬之技術領域】 本發明係關於一矽覆絕緣裝置及其製作方法。 【先前技術】 隨著微電子技術的日益發展，力求電子元件必須具備更 佳之性能（performance)，因此元件與元件之間需要電性的 隔離’而較早是使用矽局部氧化絕緣技術（L〇C〇s)來完 成，但是由於矽局部氧化絕緣技術（LOCOS)會有較長的鳥 嘴效應（Bird’s Beak)，所以有許多的專利被提出來降低鳥嘴 效應（Bird’s Beak)，如：美國專利第 6,333,243號、第 5,712，186 號及中華民國專利申請第〇88丨丨0077號。但主要目的還是用 以元件與元件間的電性隔離用。而傳統石夕覆絕緣裝置（s〇工) 的晶圓都採用氧佈植分離技術（SIM〇x)、晶片黏合技術 (Wafer Bonding)及氫優質切割技術（Smart Cut)來完成，昂 貝矛王度約為普通梦晶圓之十倍。 參考圖1所示，其顯示習知矽覆絕緣裝置1〇。該習知之矽 覆絕緣裝置10包括：一基板u、一本體12、一源極13、一 汲極14、一閘極氧化層15及一閘極16。該基板丨丨具有一基 底及一埋入氧化層（Buried Oxide) 112。利用埋入氧化層 112減少PN接面，以減少漏電流和寄生PN接面電容。然而 因為該習知之矽覆絕緣裝置10具有一完全隔離矽薄層之埋 入氧化層112,散熱不易而造成通道層之帶電載子嚴重地被 自我加熱’元件和系統之性能也因此大幅降低。 由於為了抑制超短通道效應（Ultra-Sh〇rt Channel 100436.doc 12799061279906 IX. Description of the Invention: [Technical Field to Which the Invention Is Ascribed] The present invention relates to a coating insulation device and a method of fabricating the same. [Prior Art] With the development of microelectronics technology, electronic components must have better performance, so electrical isolation between components and components is required. Earlier, local oxidation insulation technology was used (L〇 C〇s) to complete, but because the local oxidation insulation technology (LOCOS) has a longer Bird's Beak, there are many patents proposed to reduce the Bird's Beak, such as the United States. Patent Nos. 6,333,243, 5,712,186 and the Republic of China Patent Application No. 〇88丨丨0077. However, the main purpose is to use electrical isolation between components and components. The wafers of the traditional Shihua overlying insulation device (s〇) are completed by oxygen plating separation technology (SIM〇x), wafer bonding technology (wafer bonding) and hydrogen cutting technology (Smart Cut). Wang Du is about ten times that of ordinary dream wafers. Referring to Figure 1, there is shown a conventional insulating device 1 . The conventional insulating device 10 includes a substrate u, a body 12, a source 13, a drain 14, a gate oxide layer 15, and a gate 16. The substrate has a substrate and a buried oxide layer 112. The PN junction is reduced by the buried oxide layer 112 to reduce leakage current and parasitic PN junction capacitance. However, since the conventional insulating device 10 has a buried oxide layer 112 which completely separates the thin layer, heat dissipation is not easy and the charged carriers of the channel layer are severely self-heated. The performance of the elements and systems is thus greatly reduced. Due to the suppression of ultrashort channel effects (Ultra-Sh〇rt Channel 100436.doc 1279906
Effect) ’ -些製作厚度均勻性好的超薄矽薄膜之專利也被 提出’但超薄矽薄膜會造成較高之串接電阻。戶斤以同時能 夠解決漏電流、串接電阻、超短通道效應（Shcm Channel 職⑷與自我加熱效應（Self-Heating Effect)問題之方法亦 屬稀有。而且利用以上所提之三種技術（氧佈植分離技術 (SIM〇X)、晶片黏合技術⑽如Bonding)及氫優f切割技術 (S丽t Cut)製作之石夕覆絕緣裝置，必須利用該昂貴之基Effect) ─ Some patents for making ultra-thin tantalum films with uniform thickness are also proposed 'but ultra-thin films will result in higher series resistance. It is also rare to use a method that can solve the problems of leakage current, series resistance, and ultra-short channel effect (Shcm Channel (4) and Self-Heating Effect), and utilize the above three techniques (oxygen cloth). The planting separation technology (SIM〇X), the wafer bonding technology (10) such as Bonding, and the hydrogen-based f-cutting technology (Slipt Cut)
板，故所完成的⑦覆絕緣裝置其成本會相對提高。因此不 符合市場上的需求。 口此有必要提供一種創新且具進步性的矽覆絕緣裝 置’以解決上述問題。 【發明内容】 本發明之目的在於提供一種矽覆絕緣裝置，其包括：一 基板、一埋入氧化層、一場氧化隔離層、一具導電之半導 體層、一閘極氧化層、一閘極層、一第二源極部及一第二 汲極α卩省埋入氧化層形成於該基板上。該場氧化隔離層 形成於該基板上且設置於該埋人氧化層之周側。該具導電 之半導體層形成於該埋入氧化層i，該半導體層具有一本 體…第-源極部及-第-汲極部。該間極氧化層形成於 该/、‘電之半‘體層上。該閘極層形成於該閘極氧化層 上。該第二源極部及該第二汲極部分別形纽該第一源極 部及該第一汲極部上。 本發明之另一目的在於提供一種矽覆絕緣裝置之製作方 法’包括以下步驟：⑷提供_基板；（b)形成一埋入氧化層 W0436.doc 1279906 及一場氧化隔離層於該基板上，#中該場氧化隔離層係設 置於該埋入氧化層之周側’·⑷形成一具導電之半導體層於 »亥埋入氧化層上；⑷形成一閘極氧化層於該具導電之半導 體層上；⑷形成—開極層於該閘極氧化層上；⑴於該具導 電之：導體層形成一第一源極部及一第一汲極部；及⑻形 成一第二源極部H汲極部，分別設置於該第一源極 部及該第一汲極部上。 由於該第-源極部與基底間有一PN接面且第一汲極部 與基底間有-PN接面’故本發明之⑦覆絕緣裝置能克服自 我加熱2應（Self-Heating Effect)。並且，利用該第二源極 部及該第二汲極部，使得本發明之石夕覆絕緣裝置具有較低 串接電阻及能壓制短通道效應（Sh〇n Channel Effect)。另 外，本發明之矽覆絕緣裝置不需使用昂貴的矽覆絕緣基 板，故成本可大幅地降低。 【實施方式】 清參考圖2 ’其顯示本發明第一實施例之矽覆絕緣裝置之 不意圖。本發明第一實施例之矽覆絕緣裝置2〇主要包括： 一基板21、一埋入氧化層22、一場氧化隔離層23、一具導 電之半導體層24、一閘極氧化層25、一閘極層26、一第二 源極部281及一第二汲極部282。 該基板21可為矽、鍺或ΙΙΙ-ν族晶圓基板，該基板21只須 用習知的普通矽晶圓，而不須用昂貴的矽覆絕緣基板。該 埋入氧化層22形成於該基板21上。該埋入氧化層22之材質 係選自由二氧化矽（Si〇2)、氮化矽（Si3N4)、氧氮氧（〇Ν〇)、 100436.doc 1279906 氧化銘（Al2〇3)、矽化碳（SiC)、鑽石、空氣腔（Air-Gap)、具 有不同設定摻雜雜質濃度之半導體或金屬矽化物 (Silicide)、或金屬所組成之群。 5亥場氧化隔離層23與該埋入氧化層22同時形成於該基板 21上且設置於該埋入氧化層22之周側。該場氧化隔離層23 之材質係選自由二氧化矽（Si02)、氮化矽（Si3N4)、氧氮氧 (ΟΝΟ)、氧化链（a12〇3)、矽化碳（SiC)、鑽石、空氣腔（Air_ Gap)、具有不同設定摻雜雜質濃度之半導體或金屬矽化物 (SlllClde)、金屬所組成之群。該場氧化隔離層23與該埋入 氧化層22間具有一通道246及247。 遠具導電之半導體層24形成於該埋入氧化層22上。該具 ‘電之半導體層24具有一本體241、一第一源極部242及一 第一汲極部243。該第一源極部242與基底21間有一 PN接面 246(亦即該場氧化隔離層23與該埋入氧化層22間之該通道） 且第一汲極部243與基底21有一 PN接面247(亦即該場氧化 隔離層23與該埋入氧化層22間之該通道）。該接面246及該 接面247能夠克服自我加熱效應（Self_Heating以化⑷的問 題而5亥本體241能夠用適當高掺雜濃度以使門檻電壓 (Threshold Voltage)達到最佳化。該具導電之半導體層之厚 度較佳地係為〇·5 11111至10〇 nm之間。該具導電之半導體層 24係遠自由第四族或Ιπ_ν族材料所組成單層或多層之群。 该閘極氧化層25係形成於該具導電之半導體層24上，該 =極氧化層25可為約〇.5至2奈米之二氧化石夕層或其他等效 厚度之高Κ值介電材料。該閘極層26形成於該閘極氧化層25 100436.doc 1279906 上。5亥閘極層26可為一閘極多晶石夕層或可為中能隙 (Mid-Gap)過渡金屬之群，係形成相對於該本體241位置之 該具導電之半導體層24上。 本發明之矽覆絕緣裝置20另包括一氧化物保護層27，係 形成於該閘極層26之周邊。該氧化物保護層27可為二氧化 矽層。該第二源極部281位於該第一源極部242上，且該第 二汲極部282位於該第一汲極部243上。該第二源極部281 及該第二汲極部282係選自由第四族或Ιπ_ν族材料所組成 之群，如矽（Si)，鍺（Ge)、碳化矽（SiC)、鍺化矽（SiGe)、… 石申化鎵（GaAs)等以增加矽覆絕緣裝置之移動率，亦可形成 擴張或壓縮力的拉力（Strain)來加強矽覆絕緣裝置通道層之 載子移動率，使得本發明之矽覆絕緣裝置具有較低串接電 阻及能壓制短通道效應（Short Channel Effect)。本發明之石夕 覆絕緣裝置20另包括一源極接觸層291及一汲極接觸層 292,分別形成於該第二源極部281及該第二汲極部282上。 參考圖3A至圖3D，其顯示本發明第一實施例之石夕覆絕緣 衣置20之製作方法示意圖。參考圖3A，首先提供一基板21。 再利用矽局部氧化絕緣（LOCOS)、多晶矽緩衝局部氧化絕 緣（Poly Buffer LOCOS)、密封介面式局部氧化絕緣（SIL〇) 或夂溝槽絕緣（sτι)專絕緣隔離技術同時熱成長氧化出該埋 入氧化層22及該場氧化隔離層23於該基板21上。該場氧化 隔離層23設置於該埋入氧化層22之周側。 值得注意的是，若以矽局部氧化絕緣（L〇c〇s)或其相關 技術形成者，該埋入氧化層22與該場氧化隔離層23之材質 100436.doc 1279906 係為一氧化矽（Si〇2)。若以淺溝槽絕緣（sti)技術形成，則 可填入其他材質，使該埋入氧化層22與該場氧化隔離層23 之材質為氮化矽（Si3N4)、氧氮氧（ΟΝΟ)、氧化鋁（Ai2〇3), 矽化碳（SiC)、鑽石、具有不同摻雜雜質濃度之半導體或金 屬矽化物（Silicide)、或製程許可下之金屬所組成之群。因 此，可造成不同的裝置性能，也可造成該具導電之半導體 層24之形成擴張或壓縮力的拉力（Strain)來加強矽覆絕緣裝 置通道層之載子移動率，增強該裝置之電流驅動力。 參考圖3B，形成一具導電之半導體層24於該埋入氧化層 22上’该具導電之半導體層24可利用如低溫低壓之化學氣 相沉積（CVD)、濺鍍（Sputtering)、或電漿加強化學氣相沈 積（PECVD)等方法形成於該埋入氧化層22上。而該具導電 之半導體層24與基底21聯結具有通道246、247，有助於碰 撞游離之電洞與熱能之排除以克服自我加熱效應 (Self-Heating Effect)的問題。 另外’當本發明之裝置形成該導電之導體層24後，可以 齊方向（H〇m〇geneous)之濕蝕刻技術從定義好的主動區（係 含該裝置之本體241與源/汲極242與243)側邊挖除而暴露的 孩埋入氧化層22與該場氧化隔離層23之材質，使形成空氣 腔（Alr_Gap)，形成所謂的矽覆無物 SON(Silicon On Nothing) 裝置。當然，被挖除的區域，可重新被填入其他如上所述 之不同材貝（例如·二氧化石夕、氮化石夕、氧氮氧、氧化铭、 石反化矽（SiC)、鑽石、空氣腔（Air_Gap)、具有不同摻雜雜質 /辰度之半導體或金屬矽化物（SiHcide)、金屬等），以增進本 100436.doc -10- 1279906 27形成於該閘極層26周彡，且在適當之乾式㈣後暴露出 該具導電之半導體層24之第一源極部242及該第一汲極部 243。由於超薄之該具導電之半導體層24有較大之串接電 阻，故再形成該第二源極部281於該第一源極部242上，且 形成該第二汲極部282於該第一汲極部243上。該第二源極 部28丨及該第二汲極部282係選自由第四族或m_v族材料所 組成之群，如矽（Si)、鍺（Ge)、碳化矽（Sic)、鍺化矽（SiGe)、… 砷化鎵（GaAs)等以增加矽覆絕緣裝置之移動率，亦可形成 擴張或壓縮力的拉力（Strain)來加強矽覆絕緣裝置通道層之 載子移動率，使得本發明之矽覆絕緣裝置具有較低串接電 阻及能壓制短通道效應。該第二源極部281及該第二汲極部 282可利用選擇性磊晶成長（SEG)技術達成，再利用高濃度 離子佈植（HDD)佈植該第二源極部281及該第二汲極部The board, so the cost of the 7-span insulation device completed will be relatively increased. Therefore, it does not meet the needs of the market. It is necessary to provide an innovative and progressive insulation device to solve the above problems. SUMMARY OF THE INVENTION An object of the present invention is to provide a coating insulation device comprising: a substrate, a buried oxide layer, an oxide isolation layer, a conductive semiconductor layer, a gate oxide layer, and a gate layer A second source portion and a second drain electrode are formed on the substrate. The field oxide isolation layer is formed on the substrate and disposed on a peripheral side of the buried oxide layer. The conductive semiconductor layer is formed on the buried oxide layer i, and the semiconductor layer has a body ... a first source portion and a - a first drain portion. The inter-electrode oxide layer is formed on the /, "electric half" bulk layer. The gate layer is formed on the gate oxide layer. The second source portion and the second drain portion are respectively formed on the first source portion and the first drain portion. Another object of the present invention is to provide a method for fabricating a thermal insulation device comprising the steps of: (4) providing a substrate; (b) forming a buried oxide layer W0436.doc 1279906 and an oxide isolation layer on the substrate, # The field oxide isolation layer is disposed on the peripheral side of the buried oxide layer. (4) forming a conductive semiconductor layer on the buried oxide layer; (4) forming a gate oxide layer on the conductive semiconductor layer (4) forming an open layer on the gate oxide layer; (1) the conductive layer: the conductor layer forming a first source portion and a first drain portion; and (8) forming a second source portion H The drain portions are respectively disposed on the first source portion and the first drain portion. Since the PN junction between the first source portion and the substrate and the -PN junction between the first drain portion and the substrate, the 7-insulation device of the present invention can overcome the Self-Heating Effect. Further, by using the second source portion and the second drain portion, the device of the present invention has a low series resistance and can suppress a short channel effect. Further, the overlying insulating device of the present invention does not require the use of an expensive overlying insulating substrate, so the cost can be greatly reduced. [Embodiment] Referring to Fig. 2', there is no intention of showing a covering insulating device according to a first embodiment of the present invention. The insulating device 2 of the first embodiment of the present invention mainly comprises: a substrate 21, a buried oxide layer 22, a field oxide isolation layer 23, a conductive semiconductor layer 24, a gate oxide layer 25, and a gate. The pole layer 26, a second source portion 281 and a second drain portion 282. The substrate 21 can be a germanium, germanium or germanium-ν family wafer substrate, which requires only conventional conventional germanium wafers, without the need for expensive germanium insulating substrates. The buried oxide layer 22 is formed on the substrate 21. The material of the buried oxide layer 22 is selected from the group consisting of cerium oxide (Si〇2), cerium nitride (Si3N4), oxynitride (〇Ν〇), 100436.doc 1279906 oxidized (Al2〇3), deuterated carbon (SiC), diamond, air-to-air (Air-Gap), semiconductors with different doping impurity concentrations, or silicide, or a group of metals. The five-field oxide isolation layer 23 and the buried oxide layer 22 are simultaneously formed on the substrate 21 and provided on the peripheral side of the buried oxide layer 22. The material of the field oxide isolation layer 23 is selected from the group consisting of cerium oxide (SiO 2 ), cerium nitride (Si 3 N 4 ), oxynitride (ΟΝΟ), oxidized chain (a12〇3), carbonized carbon (SiC), diamond, air cavity. (Air_Gap), a group of semiconductors or metal tellurides (SlClCl) having different doping impurity concentrations, and a group of metals. The field oxide isolation layer 23 and the buried oxide layer 22 have a channel 246 and 247 therebetween. A highly conductive semiconductor layer 24 is formed on the buried oxide layer 22. The semiconductor layer 24 has a body 241, a first source portion 242 and a first drain portion 243. The first source portion 242 and the substrate 21 have a PN junction 246 (that is, the channel between the field oxide isolation layer 23 and the buried oxide layer 22) and the first drain portion 243 and the substrate 21 have a PN connection. Face 247 (i.e., the channel between the field oxide isolation layer 23 and the buried oxide layer 22). The junction 246 and the junction 247 can overcome the self-heating effect (Self_Heating to solve the problem of (4) and the 5H body 241 can use a suitable high doping concentration to optimize the Threshold Voltage. The thickness of the semiconductor layer is preferably between 11·5 11111 and 10 〇 nm. The conductive semiconductor layer 24 is a group of single or multiple layers which are far from the fourth group or Ιπ_ν material. A layer 25 is formed on the conductive semiconductor layer 24, and the =oxide layer 25 may be a layer of about 2. 5 to 2 nm of a dioxide or other equivalent thickness of a high-value dielectric material. A gate layer 26 is formed on the gate oxide layer 25 100436.doc 1279906. The 5th gate layer 26 may be a gate polysilicon layer or a group of medium-gap transition metals. The conductive insulating layer 20 is formed on the conductive semiconductor layer 24 relative to the body 241. The insulating insulating device 20 of the present invention further includes an oxide protective layer 27 formed around the gate layer 26. The oxide protection The layer 27 may be a ruthenium dioxide layer. The second source portion 281 is located at the first source portion 2 42. The second drain portion 282 is located on the first drain portion 243. The second source portion 281 and the second drain portion 282 are selected from the group consisting of a fourth family or a group of Ιπ_ν materials. Such as germanium (Si), germanium (Ge), tantalum carbide (SiC), germanium telluride (SiGe), ... GaAs, etc. to increase the mobility of the insulating device, can also form expansion or compression The force of the strain (Strain) is used to enhance the carrier mobility of the channel layer of the insulating device, so that the insulating device of the present invention has a low series resistance and can suppress the short channel effect. The insulating device 20 further includes a source contact layer 291 and a drain contact layer 292 formed on the second source portion 281 and the second drain portion 282. Referring to FIG. 3A to FIG. A schematic diagram of a method for fabricating a stone-covered insulating garment 20 according to a first embodiment of the present invention. Referring to Figure 3A, a substrate 21 is first provided. A partial oxidation insulating (LOCOS), polycrystalline buffer (Poly Buffer LOCOS), Sealed interface type local oxidation insulation (SIL〇) or trench insulation (sτι) a special insulating isolation technique simultaneously thermally grows the buried oxide layer 22 and the field oxide isolation layer 23 on the substrate 21. The field oxide isolation layer 23 is disposed on the peripheral side of the buried oxide layer 22. Note that if the oxidized insulating layer (L〇c〇s) or its related art is formed, the buried oxide layer 22 and the material of the field oxide isolating layer 23 are 100436.doc 1279906 as cerium oxide (Si). 〇 2). If formed by a shallow trench insulation (sti) technique, other materials may be filled, such that the buried oxide layer 22 and the field oxide isolation layer 23 are made of tantalum nitride (Si3N4), oxygen, nitrogen oxides (ΟΝΟ), Alumina (Ai2〇3), a group of deuterated carbon (SiC), diamonds, semiconductors or metal tellurides with different doping impurity concentrations, or metals under process permits. Therefore, different device performance may be caused, and the strain of the conductive semiconductor layer 24 forming expansion or compressive force may be caused to enhance the carrier mobility of the channel layer of the insulating device and enhance the current driving of the device. force. Referring to FIG. 3B, a conductive semiconductor layer 24 is formed on the buried oxide layer 22. The conductive semiconductor layer 24 can utilize, for example, low temperature and low pressure chemical vapor deposition (CVD), sputtering, or electricity. A method such as slurry enhanced chemical vapor deposition (PECVD) is formed on the buried oxide layer 22. The electrically conductive semiconductor layer 24 is coupled to the substrate 21 with channels 246, 247 to assist in the collision of free holes and thermal energy to overcome the self-heating effect. In addition, when the conductive device layer 24 is formed by the device of the present invention, the active region (which includes the body 241 and the source/drain 242 of the device) can be obtained by a wet etching technique in a uniform direction (H〇m〇geneous). And the material of the oxide oxide layer 22 and the field oxide isolation layer 23 exposed by the 243) side excavation is formed to form an air cavity (Alr_Gap) to form a so-called SON (Silicon On Nothing) device. Of course, the excavated area can be refilled with other different shells as described above (eg, sulphur dioxide, nitrite, oxynitride, oxidized, stone SiC, diamonds, An air cavity (Air_Gap), a semiconductor or a metal halide (SiHcide) having a different doping impurity/density, a metal, etc., to enhance the formation of the gate layer 26 by the present invention, and The first source portion 242 and the first drain portion 243 of the conductive semiconductor layer 24 are exposed after a suitable dry type (4). Because the ultra-thin conductive semiconductor layer 24 has a large series resistance, the second source portion 281 is further formed on the first source portion 242, and the second drain portion 282 is formed thereon. The first drain portion 243 is on. The second source portion 28 and the second drain portion 282 are selected from the group consisting of Group 4 or m_v materials, such as germanium (Si), germanium (Ge), tantalum carbide (Sic), and germanium. Si(SiGe), GaAs (GaAs), etc. to increase the mobility of the insulating device, or to form a tensile or compressive force (Strain) to enhance the carrier mobility of the channel layer of the insulating device. The overlying insulation device of the present invention has a low series resistance and is capable of suppressing short channel effects. The second source portion 281 and the second drain portion 282 can be achieved by a selective epitaxial growth (SEG) technique, and the second source portion 281 and the first portion are implanted by high concentration ion implantation (HDD). Second bungee
282。另外，該第二源極部281及該第二汲極部^以可利用邊 襯方法形成D 參考圖3D，利用金屬矽化物（Silicide)製程同時完成金屬 矽化物的該源極接觸層291及該汲極接觸層292，與該閘極 層26之上層（圖未示出）。 因此，利用本發明之製作方法製作之第一實施例矽覆絕 緣裝置20具有較低串接電阻、能夠壓制短通道效應(Short Channel Effect)及克服自我加熱效應（Self-Heating Effect)， 且不需使用昂貴的矽覆絕緣基板，故成本可大幅地降低。 參考圖4，其顯示本發明第二實施例之矽覆絕緣裝置4〇 之不忍圖。本發明第二實施例之矽覆絕緣裝置4〇與本發明 100436.doc -12- 1279906 第-實施例之石夕覆絕緣裝置2〇之製作方法大致相同，复不 :之處在於該場氧化_層43是採用淺溝槽絕緣技術（印) 元成。 參考圖5 ’其顯示本發明第三實施例之矽覆絕緣裝置刈 之不思圖。本發明第三實施例之々覆絕緣裝置辦利用淺 溝槽絕緣技術（STI)完成該埋人氧化層52及該場氧化隔離層 53 ’其他部份與本發明第—實施例之Μ絕縣置20之製 作方法大致相同。 淮上述貫施例僅為說明本發明之原理及其功效，而非用 以限制本發明。因此，習於此技術之人士可在不違背本發 明之精神對上述實施例進行修改及變化。本發明之權利範 圍應如後述之申請專利範圍所列。 【圖式簡單說明】 圖1為習知石夕覆絕緣裝置之示意圖； 圖2為本發明第一實施例矽覆絕緣裝置之示意圖； 圖3Α至圖3D為本發明第一實施例之矽覆絕緣裝置之製 作方法示意圖； 圖4為本發明第二實施例之矽覆絕緣裝置之示意圖； 圖5為本發明第三實施例之矽覆絕緣裝置之示意圖。 【主要元件符號說明】 10 習知之矽覆絕緣裝置 11 基板 111 基底 112 埋入氧化層 -13- 100436.doc 1279906 12 本體 13 源極部 14 汲極部 15 閘極氧化層 16 閘極層 20 本發明第一實施例之矽覆絕緣裝 21 基板 22 埋入氧化層 23 場氧化隔離層 24 具導電之半導體層 241 本體 242 第一源極部 243 第一沒極部 244 第一源極部與本體間之PN接面 245 第一汲極部與本體間之PN接面 246 第一源極部與基底間之PN接面 247 第一沒極部與基底間之P N接面 25 閘極氧化層 26 閘極層 27 氧化物保護層 281 第二源極部 282 第二汲極部 291 源極接觸層 292 沒極接觸層 100436.doc -14- 1279906 40 本發明第二實施例之矽覆絕緣裝置 43 場氧化隔離層 50 本發明第三實施例之矽覆絕緣裝置 52 埋入氧化層 53 場氧化隔離層 100436.doc -15-282. In addition, the second source portion 281 and the second drain portion can be formed by using a side liner method. Referring to FIG. 3D, the source contact layer 291 of the metal germanide is simultaneously completed by a metal telluride process. The drain contact layer 292 is above the gate layer 26 (not shown). Therefore, the first embodiment of the insulating device 20 fabricated by the manufacturing method of the present invention has a low series resistance, can suppress a short channel effect and overcome a self-heating effect, and does not The expensive overlying insulating substrate is required, so the cost can be greatly reduced. Referring to Fig. 4, there is shown an unbearable view of the insulating device 4 of the second embodiment of the present invention. The underlying insulating device 4 of the second embodiment of the present invention is substantially the same as the method for fabricating the insulating device of the present invention 100436.doc -12- 1279906, which is in the form of oxidation of the field. _ layer 43 is formed by shallow trench insulation technology (printing). Referring to Fig. 5', there is shown a plan view of the insulating device of the third embodiment of the present invention. The underlying insulating device according to the third embodiment of the present invention performs the buried oxide layer 52 and the field oxide isolating layer 53' by using shallow trench insulating technology (STI), and the annihilation county of the first embodiment of the present invention. The method of making 20 is roughly the same. The above examples are merely illustrative of the principles and effects of the invention and are not intended to limit the invention. Therefore, those skilled in the art can make modifications and changes to the above embodiments without departing from the spirit of the invention. The scope of the invention should be as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view of a conventional insulating device; FIG. 2 is a schematic view of a first insulating device according to a first embodiment of the present invention; FIG. 3A to FIG. FIG. 4 is a schematic view of a smashing insulation device according to a second embodiment of the present invention; and FIG. 5 is a schematic view of a smashing insulation device according to a third embodiment of the present invention. [Main component symbol description] 10 Conventional overlying insulation device 11 substrate 111 substrate 112 buried oxide layer-13- 100436.doc 1279906 12 body 13 source portion 14 drain portion 15 gate oxide layer 16 gate layer 20 Inventive insulating device 21 of the first embodiment of the invention, substrate 22, buried oxide layer 23, field oxide isolation layer 24, conductive semiconductor layer 241, body 242, first source portion 243, first source portion 244, first source portion and body PN junction 245 PN junction 246 between the first drain portion and the body PN junction 247 between the first source portion and the substrate PN junction 25 between the first pole portion and the substrate Gate oxide layer 26 Gate layer 27 oxide protective layer 281 second source portion 282 second drain portion 291 source contact layer 292 gate contact layer 100436.doc -14- 1279906 40 the insulating device 43 of the second embodiment of the present invention Field Oxide Isolation Layer 50 The ruthenium insulation device 52 of the third embodiment of the present invention is buried with an oxide layer 53. Field Oxide Isolation Layer 100436.doc -15-