TWI492433B - 可逆性可編程電阻式記憶體及提供方法、相變記憶體、電子系統 - Google Patents
可逆性可編程電阻式記憶體及提供方法、相變記憶體、電子系統 Download PDFInfo
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- TWI492433B TWI492433B TW100129686A TW100129686A TWI492433B TW I492433 B TWI492433 B TW I492433B TW 100129686 A TW100129686 A TW 100129686A TW 100129686 A TW100129686 A TW 100129686A TW I492433 B TWI492433 B TW I492433B
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- 230000015654 memory Effects 0.000 title claims description 139
- 230000002441 reversible effect Effects 0.000 title claims description 82
- 238000000034 method Methods 0.000 title claims description 18
- 230000008859 change Effects 0.000 claims description 53
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 53
- 229920005591 polysilicon Polymers 0.000 claims description 52
- 239000007943 implant Substances 0.000 claims description 31
- 229910052732 germanium Inorganic materials 0.000 claims description 29
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 29
- 229910052751 metal Inorganic materials 0.000 claims description 25
- 239000002184 metal Substances 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 13
- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910044991 metal oxide Inorganic materials 0.000 claims description 10
- 150000004706 metal oxides Chemical class 0.000 claims description 10
- 230000004888 barrier function Effects 0.000 claims description 9
- 230000000295 complement effect Effects 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 8
- 238000003860 storage Methods 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 239000002019 doping agent Substances 0.000 claims description 5
- 229910001092 metal group alloy Inorganic materials 0.000 claims description 4
- 238000013500 data storage Methods 0.000 claims description 2
- SCCCLDWUZODEKG-UHFFFAOYSA-N germanide Chemical compound [GeH3-] SCCCLDWUZODEKG-UHFFFAOYSA-N 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 239000007784 solid electrolyte Substances 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 229910052715 tantalum Inorganic materials 0.000 claims description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 2
- 239000011159 matrix material Substances 0.000 claims 2
- 230000000903 blocking effect Effects 0.000 claims 1
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- 239000012782 phase change material Substances 0.000 description 18
- 238000010586 diagram Methods 0.000 description 17
- 230000005055 memory storage Effects 0.000 description 9
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- 239000000463 material Substances 0.000 description 4
- 230000008018 melting Effects 0.000 description 4
- 238000002844 melting Methods 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 239000011669 selenium Substances 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
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- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000008030 elimination Effects 0.000 description 2
- 238000003379 elimination reaction Methods 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052707 ruthenium Inorganic materials 0.000 description 2
- 229910052711 selenium Inorganic materials 0.000 description 2
- ALKWEXBKAHPJAQ-NAKRPEOUSA-N Asn-Leu-Asp-Asp Chemical compound NC(=O)C[C@H](N)C(=O)N[C@@H](CC(C)C)C(=O)N[C@@H](CC(O)=O)C(=O)N[C@@H](CC(O)=O)C(O)=O ALKWEXBKAHPJAQ-NAKRPEOUSA-N 0.000 description 1
- 229910000618 GeSbTe Inorganic materials 0.000 description 1
- 229910005866 GeSe Inorganic materials 0.000 description 1
- 229910003087 TiOx Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 239000005387 chalcogenide glass Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
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- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 230000005415 magnetization Effects 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910000480 nickel oxide Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910003446 platinum oxide Inorganic materials 0.000 description 1
- VIDTVPHHDGRGAF-UHFFFAOYSA-N selenium sulfide Chemical compound [Se]=S VIDTVPHHDGRGAF-UHFFFAOYSA-N 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- BCTHFFLRHBNYHU-UHFFFAOYSA-N strontium;selenium(2-) Chemical compound [Se-2].[Sr+2] BCTHFFLRHBNYHU-UHFFFAOYSA-N 0.000 description 1
- 229910052714 tellurium Inorganic materials 0.000 description 1
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 description 1
- HLLICFJUWSZHRJ-UHFFFAOYSA-N tioxidazole Chemical compound CCCOC1=CC=C2N=C(NC(=O)OC)SC2=C1 HLLICFJUWSZHRJ-UHFFFAOYSA-N 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
- 150000003624 transition metals Chemical class 0.000 description 1
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
Classifications
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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Description
本發明涉及到可編程記憶體元件,如使用在記憶體陣列之可編程電阻元件。
可編程電阻元件通常是指元件之電阻狀態可在編程後改變。電阻狀態可以由電阻值來決定。例如,電阻性元件可以是單次性可編程OTP(One-Time Programmable)元件(如電性熔絲),而編程方法可以施用高電壓,來產生高電流通過OTP元件。當這大電流經由打開的編程選擇器流過OTP元件,OTP元件將被燒成高或低電阻狀態(取決於是熔絲或反熔絲)而加以編程。
電性熔絲是一種常見的OTP,而這種可編程電阻元件,可以是多晶矽,矽化多晶矽,矽化物,熱隔離的主動區,金屬,金屬合金或它們的組合。金屬可以是鋁,銅或其他過渡金屬。其中最常用的電性熔絲是矽化的多晶矽,用互補式金氧半導體晶體管(CMOS)的閘極製成,用來作為內連接(interconnect)。電性熔絲也可以是一個或多個接點(contact)或層間接點(via),而不是小片段的內連接。高電流可把接點或層間接點燒成高電阻狀態。電性熔絲
可以是反熔絲,其中高電壓使電阻降低,而不是提高電阻。反熔絲可由一個或多個接點或層間接點組成,並含有絕緣體於其間。反熔絲也可由CMOS閘極耦合於CMOS本體,其含有閘極氧化層當做為絕緣體。
一種傳統的可編程電阻式記憶存儲單元如第一圖所示。存儲單元10包含電阻元件11和N型金氧半導體晶體管(NMOS)編程選擇器12。電阻元件11一端耦合到NMOS的汲極,另一端耦合到正電壓V+。NMOS12的閘極耦合到選擇信號(SEL),源極耦合到負電壓V-。當高電壓加在V+而低電壓加在V-時,電阻元件10則可被編程,經由提高編程選擇信號(SEL)來打開NMOS12。一種最常見的電阻元件是矽化多晶矽,乃是在同時製作MOS閘極時用的同樣材料。NMOS編程選擇器12的面積,需要足夠大,以提供所需的編程電流持續幾微秒。矽化多晶矽的編程電流通常是從幾毫安(對寬度約40奈米的熔絲)至20毫安(對寬度約0.6微米熔絲)。因此使用矽化多晶矽的電性熔絲存儲單元面積往往是非常大的。
可編程電阻元件可以是可逆的電阻元件,可以重複編程且可逆編程成數位邏輯值“0”或“1”。可編程電阻元件可從相變材料來製造,如鍺(Ge),銻(Sb),碲(Te)的組成Ge2Sb2Te5(GST-225)或包括成分銦(In),錫(Sn)或硒(Se)的GeSbTe類材料。經由高電壓短脈衝或低電壓長脈衝,相變材料可被編程成非晶體態高電阻狀態或結晶態低電阻狀態。可逆電阻元件可以是電阻式隨機存取記憶體(電阻式記憶體RRAM),存儲單元由在金屬或金屬合金電極之間的金屬氧化物,如鉑/氧化鎳/鉑(Pt/NiO/Pt),氮化鈦/氧化鋅/氧化鉿/氮化鈦
(TiN/TiOx/HfO2/TiN)製成。該電阻狀態可逆性的改變是經由電壓或電流脈衝的極性,強度,持續時間,產生或消滅導電細絲。另一種類似電阻式隨機存取記憶體(RRAM)的可編程電阻元件,就是導電橋隨機存取記憶體(CBRAM)。此記憶體是基於電化學沉積和移除在金屬或金屬合金電極之間的固態電解質薄膜裏的金屬離子。電極可以是一個可氧化陽極和惰性陰極,而且電解質可以是摻銀或銅的硫系玻璃如硒化鍺(GeSe)或硒化硫(GeS)等。該電阻狀態可逆性的改變是經由電壓或電流脈衝的極性,強度,持續時間,產生或消滅導電橋。
如第二圖a所示,相變記憶體(PCM)是另一種傳統的可編程電阻元件20。PCM存儲單元包含相變薄膜(Phase Change Material)21和當作編程選擇器的雙極性電晶體22,其具有P+射極23、N型基極27和集極25(為P型基體)。相變薄膜21一端耦合到雙極性電晶體22的射極23,另一端耦合到正電壓V+。雙極性電晶體22的N型基極27耦合到負電壓V-,而集極25耦合到接地。在V+和V-間施加適當的電壓持續適當的時間,相變薄膜21可被編程成高或低電阻狀態,根據電壓和持續時間而定。按照慣例,編程相變記憶體成高電阻狀態(或重設狀態)大約需要持續50ns的3V電壓,消耗大約300uA的電流。編程相變記憶體成低電阻狀態(或設置狀態)需要持續300ns左右的2V電壓,消耗大約100uA的電流。
另一種相變記憶體(PCM)的可編程電阻元件如第二圖b所示。相變記憶體材料有相變薄膜21'和一二極體22'。相變薄膜21'被耦合在二極體陽極22'和正電壓V+之間。二極體的陰極22'被耦合到負電壓V-。施加適當的電壓在V+和V-之間持續一段適當的時
間,相變薄膜21'可以被編程為高或低電阻狀態,根據電壓和持續時間而定。請見“Kwang-Jin Lee et al.,“A90nm 1.8V 512Mb Diode-Switch PRAM with 266MB/s Read Throughput,”International Solid-State Circuit Conference,2007,pp.472-273。第二圖b所示為使用一個二極體作為每一個相變記憶體(PCM)存儲單元的編程選擇器的例子。雖然這項技術可以減少PCM存儲單元尺寸到只有6.8F2(F代表特徵大小),二極體需要非常複雜的製造過程,如選擇性磊晶成長(SEG)。如此一來對嵌入式PCM的應用,將變的非常昂貴。
第二圖c顯示了一種傳統雙極性電晶體22的截面圖。雙極性電晶體22包括P+主動區(active region)23、N淺井24、N+主動區27、P型基體25和用來隔離元件的淺溝槽隔離(STI)26。P+主動區23和N+主動區27耦合到N井24,且為雙極性電晶體22裏射極和基極二極體的P和N端,而P型基體25是雙極性電晶體22的集極。這種存儲單元需要N淺井24比淺溝槽隔離26淺,來妥善隔離每個存儲單元,因而需要比標準CMOS邏輯制程多3-4道光罩,而使得它的製作比較昂貴。
二極體也可以從多晶矽製造。第三圖顯示一多晶矽二極體的橫截面。要形成多晶矽二極體,多晶矽是由N+植入一端而P+植入另一端,二端之間的間距Lc含有固有(intrinsic)的摻雜劑。固有的摻雜劑是由外擴散或污染所造成之些微N型或P型摻雜劑,而非刻意的摻雜。矽化物阻擋層應用於多晶矽上以防止矽化物在多晶矽的表面上形成,從而防止短路。多晶矽的P+和N+兩端由接點帶出以形成二極體的PN兩端。作為一例子,多晶矽二極體可見
Ming-Dou Ker et al.,“Ultra High-Voltage Charge Pump Circuit in Low-Voltage Bulk CMOS Processes with Polysilicon Diodes,”IEEE Transaction of Circuit and System-II,Vol.54,No.1,January 2007,pp.47-51。
第四圖顯示第三圖的多晶矽二極體的電流電壓特性。目前的電流電壓曲線顯示有用的二極體行為,如二極體的閾值電壓約為0.6V而漏電流低於1nA。經由改變間距Lc,多晶矽二極體的擊穿電壓和漏電流可以相應調整。
這項專利是關於使用二極體作為編程選擇器的可編程電阻元件存儲單元之實施例。可編程的電阻元件可以使用標準CM0S邏輯製程,以減少存儲單元的大小和成本。
因此本發明提供一種可逆性可編程電阻式記憶體,包括:多個可逆性可編程電阻式存儲單元,至少有一可逆性可編程電阻式存儲單元包括:一可逆性可編程電阻式元件耦合到第一電源電壓線;及一二極體建構於多晶矽上,包括至少一第一端和一第二端,其中該第一端具有一第一型摻雜,該第二端具有一第二型的摻雜,該第一端提供了該二極體的一第一端,該第二端提供二極體的一第二端,該第一端和第二端皆存在一共同的多晶矽上,該第一端被耦合到該可逆性可編程電阻式元件,而該第二端被耦合到第二電源電壓線;其中第一和第二端的摻雜劑是從互補式金氧半導體(CMOS)元件的源極或汲極的摻雜植入製造,其中,經由施加電壓到該第一和第二電源電壓線,該可逆性可編程電阻式元件被配置為可編程,從而改變電阻為不同的邏輯狀態。
本發明提供一種相變記憶體,包括:多個相變存儲單元,至少有一相變存儲單元包括:一相變薄膜耦合到第一電源電壓線;及一二極體包括至少一第一端和一第二端,其中該第一端具有一第一型摻雜,該第二端具有一第二型摻雜,該第一端提供了該二極體的一第一端而該第二端提供該二極體的一第二端,該第一端和第二端皆存在一個共同的多晶矽上,該第一端耦合到相變薄膜,而該第二端耦合到第二電源電壓線;其中該第一和第二端的摻雜是從互補式金氧半導體(CMOS)元件的源極或汲極的摻雜植入製造,其中,經由施加電壓到第一和第二電源電壓線,相變薄膜被配置為可編程,從而可逆的改變電阻為不同的邏輯狀態。
本發明提供一種電子系統,包括:一種處理器;及一可逆性可編程電阻式記憶體可操作地連接到處理器,該可逆性可編程電阻式記憶體包括至少數個可逆性可編程電阻存儲單元來提供數據存儲,每個可逆性可編程電阻存儲單元包括:一可逆性可編程電阻元件被耦合到第一電源電壓線;及一二極體包含至少一第一端和一第二端,其中該第一端具有第一型摻雜,而該第二端具有第二型摻雜,該第一端提供了二極體的一第一端,該第二端提供二極體的一第二端,該第一和第二端皆存在一個共同的多晶矽上,該第一端耦合到該可逆性可編程電阻元件而該第二端耦合到一第二電源電壓線;其中該第一和第二端的摻雜是從互補式金氧半導體(CMOS)元件的源極或汲極的摻雜植入製造;其中,經由施加電壓到第一和第二電源電壓線,可逆性可編程電阻元件被配置為可編程,從而可逆的改變電阻到不同的邏輯狀態。
本發明提供一種方法來提供一個可逆性電阻式記憶體,包括:提
供多個可逆性可編程電阻存儲單元,至少有一可逆性可編程電阻存儲單元包括至少(i)一可逆性可編程電阻元件被耦合到第一電源電壓線;及(ii)一二極體包含至少一第一端和一第二端,該第一端具有第一型摻雜,而該第二端具有第二型摻雜,該第一端提供了該二極體的一第一端,該第二端提供該二極體的一第二端,該第一和第二端皆存在一個共同的多晶矽上,而其摻雜是從互補式金氧半導體(CMOS)元件的源極或汲極的摻雜植入製造,該第一端耦合到電阻元件而該第二端耦合到一第二電源電壓線;及經由施加電壓到第一和第二電壓線,來編程至少一可逆性可編程電阻存儲單元到一邏輯狀態。
10‧‧‧存儲單元
11‧‧‧電阻元件
12‧‧‧NMOS編程選擇器
21‧‧‧相變薄膜
20,20’‧‧‧可編程電阻元件
22‧‧‧雙極性電晶體
23‧‧‧P+射極
27‧‧‧N型基極
25‧‧‧集極
22'‧‧‧二極體
23‧‧‧P+主動區
24‧‧‧N淺井
27‧‧‧N+主動區
25‧‧‧P型基體
26‧‧‧淺溝槽隔離
30‧‧‧存儲單元
31‧‧‧可逆性可編程電阻元件
32‧‧‧多晶矽二極體
34‧‧‧多晶矽
33‧‧‧P+植入層
37‧‧‧N+植入層
d‧‧‧距離
36‧‧‧矽化物阻擋層
39‧‧‧選項層
50‧‧‧可逆性可編程電阻元件存儲單元
42‧‧‧電阻元件
41,43‧‧‧緩衝金屬
30‧‧‧多晶矽二極體
42‧‧‧薄膜
40-1,40-2,40-3‧‧‧接點填塞物
32‧‧‧陽極接點
39‧‧‧陰極接點
35‧‧‧矽化物阻擋層
49‧‧‧介電質
44‧‧‧金屬
70‧‧‧邊界為
71‧‧‧多晶矽二極體
75‧‧‧相變材料元件
73‧‧‧P+植入層
77‧‧‧N+植入層
72‧‧‧陽極
79‧‧‧陰極
80‧‧‧矽化物阻擋層
78‧‧‧位元線
77‧‧‧字元線
76‧‧‧第一層金屬(metal1)
100‧‧‧可編程電阻記憶體
101‧‧‧陣列
110‧‧‧記憶體存儲單元
111‧‧‧電阻元件
112‧‧‧二極體
150-i‧‧‧字元線驅動器
BLR0175-0‧‧‧參考位元線
WLBi152-i‧‧‧字元線
172-i‧‧‧後解碼器
LWLBi‧‧‧局部字元線
vddi‧‧‧電源電壓
120-j,125‧‧‧Y-write通道閘
130-j,135‧‧‧Y-read通道閘
S700-S760,S800-S870‧‧‧步驟
700‧‧‧處理器系統
740‧‧‧記憶體
744‧‧‧可編程電阻元件
742‧‧‧存儲單元陣列
710‧‧‧中央處理單元
715‧‧‧共同匯流排
720‧‧‧輸入輸出單元
730‧‧‧硬盤驅動器
750‧‧‧光碟
740‧‧‧記憶體
760‧‧‧其他記憶體
第一圖顯示一種傳統的可編程電阻式記憶存儲單元示意圖。
第二圖a顯示相變記憶體(PCM)用的另一種傳統可編程電阻式元件示意圖,其採用雙極型晶體管作為編程選擇器。
第二圖b顯示一種傳統相變記憶體(PCM)截面圖,其採用二極體作為編程選擇器。
第二圖c顯示另一種傳統相變記憶體(PCM)存儲單元的橫截面,其採用雙極型晶體管作為編程選擇器。
第三圖顯示一多晶矽二極體的橫截面。
第四圖顯示如第三圖所示的多晶矽二極體的電流電壓特性圖。
第五圖顯示使用一根據本發明的多晶矽二極體於可逆性可編程電阻式存儲單元的方塊圖。
第六圖顯示一可逆性可編程電阻式存儲單元的頂視圖。此存儲單元實施例使用多晶矽二極體為編程選擇器。
第七圖顯示一可逆性可編程電阻元件的截面圖。此電阻元件使用相變材料作為電阻元件。此外根據此實施例,具有緩衝金屬層耦合相變材料層和其他金屬及多晶矽二極體。
第八圖顯示一相變記憶體存儲單元的頂視圖。根據此實施例,其使用多晶矽二極體當編程選擇器。
第九圖顯示一可逆性可編程電阻式記憶體的一部分示意圖。根據此一實施例,由n行和(m+1)列的單二極體存儲單元與n個字元線驅動器一起構成。
第十圖a描繪一種可編程電阻式記憶體編程方法流程圖。
第十圖b描繪一種可編程電阻式記憶體方讀取法流程圖。
第十一圖顯示一種處理器(Processor)的系統的實施例示意圖。
在此揭露實施例,使用至少一多晶矽二極體當編程選擇器的可編程電阻式元件。此二極體可以包括植入層於一多晶矽基板內之P+和N。由於P+和N+植入層都是以現成的標準CMOS邏輯製程,這些元件可用一個有效率及符合成本效益的方法做成。沒有額外的光罩或製程步驟,以節省成本。這可編程電阻式元件可以包括在電子系統裏。
第五圖所示為使用一多晶矽二極體的可逆性可編程電阻式記憶體存儲單元30的實施例方塊圖。特別是,存儲單元30包括一可逆性可編程電阻元件31和一多晶矽二極體32。電阻元件31可耦合在多晶矽二極體32的陽極和高電壓V+之間。多晶矽二極體32的陰極可耦合到低電壓V-。在一實施例裏,記憶體存儲單元30可以是相變記憶體存儲單元,其含有相變材料的電阻元件31。多晶矽二極體
32可作為編程選擇器。可逆性可編程電阻元件31和多晶矽二極體32於電源電壓V+和V-之間是可互換的。經由一適當的時間裏施加適當的電壓在V+和V-之間,可逆性可編程電阻元件31可根據電壓和持續時間被編程為高或低電阻狀態,因此編程記憶體存儲單元30可存儲數據值(例如,數據的位元)。多晶矽二極體的P+和N+植入層可以使用矽化物阻擋層(SBL)來隔離。
第六圖顯示用多晶矽二極體32作為編程選擇器的可逆性可編程電阻存儲單元30實施例頂視圖。可逆性可編程電阻單元30包括一可逆性可編程元件31耦合到第一電源電壓V+和一二極體32。二極體32作為可逆性可編程電阻單元30的編程選擇器。該二極體32是建立在一塊多晶矽34,即多晶矽基板。構建PMOS或NMOS元件源極或汲極的P+和N+植入層33和37用來形成多晶矽二極體32的P,N兩端於多晶矽34上。矽化物阻擋層36阻擋矽化物形成於多晶矽的表面,以防止多晶矽二極體32的P和N端短路。P+植入層33和N+植入層37的距離d可用於調整擊穿電壓和漏電流。一選項層39可以引進N型淺源汲極(NLDD)、P型淺源汲極(PLDD)植入層、或NMOS和PMOS門檻電壓的摻雜植入技術於N+植入層37和P+植入層33之間,以進一步控制二極體的導通電阻。該選項層39所植入區可於標準CMOS上產生各種類的植入層,且不會增加額外費用。
第七圖顯示了一可逆性可編程電阻元件存儲單元50的截面圖。根據此一實施例,其使用相變材料(Phase Change Material)作為電阻元件42,具緩衝金屬41和43,和多晶矽二極體30(位在矽基體上的介電質49上)。多晶矽二極體30在多晶矽基板31上有P+植入區33和N+植入區37,且此兩個植入區通過陽極接點32和陰極接
點39為二極體的P,N兩端。矽化物阻擋層(STI)35隔離P+植入區33和N+植入區37。二極體31的P+植入區33經由接點填塞物40-1被耦合到作為緩衝層的下層金屬41。這下層金屬41,經由接點填塞物40-2被耦合到相變材料的一層薄膜42(如GST薄膜)。上層金屬43也被耦合到相變材料的薄膜42。上層金屬43經過接點填塞物40-3被耦合到位元線(Bitline)的另一種金屬44。相變薄膜42可以有化學成分鍺(Ge)、銻(Sb)和碲(Te),如GexSbyTez(x,y和z是任意數字),或如Ge2Sb2Te5(GST-225)。GST可以摻至少有一或更多種的銦(In),錫(Sn)或硒(Se),以提高性能。相變的存儲單元結構,可顯著平面化。這意味著相變薄膜42的面積大於被耦合到編程選擇器薄膜的接觸面積;或從矽基體表面到相變薄膜42的高度,遠小於平行於矽基體薄膜的尺寸。在此實施例裏,相變薄膜42的有效區遠遠大於接觸面積,使編程特性可以更均勻,和具可重複性。相變薄膜42不是垂直結構,不坐落在高大的接點上面,能更適合嵌入式相變記憶體的應用,尤其是當多晶矽二極體30作為編程選擇器時,可使存儲單元的面積非常小。對此技藝知悉者可知結構和製造過程可能會有所不同,而且上述相變薄膜(如GST film)的結構和緩衝金屬只作說明用途。
第八圖顯示了一種相變材料(Phase Change Material)存儲單元的頂視圖。按照此實例,存儲單元擁有一多晶矽二極體作為編程選擇器,其邊界為70。相變材料的存儲單元有多晶矽二極體71和相變材料元件75。多晶矽二極體71具有陽極72和陰極79,分別被P+植入層73和N+植入層77所覆蓋。矽化物阻擋層(STI)80阻擋矽化物形成於多晶矽二極體71的表面,防止多晶矽二極體71的陽極
72和陰極79短路。陽極72經由第一層金屬(metal1)76耦合到相變材料薄膜75。相變材料薄膜75耦合到垂直方向的第三層金屬(metal3)78位元線(BL)。多晶矽二極體71的陰極79耦合到水平方向的第二層金屬(metal2)77字元線(WL)。施加適當的電壓於位元線78和字元線77之間一段適當的時間,相變材料75可被編程為相應的0或1狀態。由於編程相變材料存儲單元是依據溫度升高,而不是如對電性熔絲的電遷移,相變薄膜(如GST薄膜)的陽極和陰極可以有對稱的面積。對此技藝知悉者可知相變薄膜,結構和佈線風格,和金屬的結構可在其他實施例裏有所不同。
編程相變記憶體(PCM),如相變薄膜,取決於相變薄膜的物理特性,如玻璃化轉變溫度和熔化溫度。要重設(寫1),需要被加熱超出熔化溫度,然後驟降溫。要設置(寫0),相變薄膜需要被加熱到熔化和玻璃化轉變之間的溫度,然後退火處理。典型的相變材料薄膜的玻璃化轉變溫度約200℃,熔融溫度約攝氏600度。這些溫度決定相變記憶體(PCM)的操作溫度,因為在特定溫度下一段長時間後電阻狀態可能會發生變化。但是,大多數應用需要保留數據10年,從工作溫度0到85℃或-40到125℃。為了在元件的壽命期限和在如此寬的溫度範圍內維持存儲單元的穩定性,相變記憶體可以被定期讀取出,然後將數據寫回相同的存儲單元,此為更新機制。更新週期可能會相當長,如超過一秒鐘(例如,分鐘,小時,天,星期,甚至幾個月)。更新機制可由記憶體內部產生或從記憶體外部觸發。長時間的更新週期以維持存儲單元的穩定性,也可以應用於其他新興的記憶體,如電阻式隨機存取記憶體(RRAM),導電橋隨機存取記憶體(CBRAM),和磁化隨
機存取記憶體(MRAM)等。
根據另一實施例,可編程電阻元件可用於建立一記憶體。根據此實施例,第九圖顯示了可編程電阻記憶體100的一部分,由n行x(m+1)列的單二極體存儲單元110的一陣列101和n個字元線驅動器150-i(i=0,1,...,n-1)所構建。記憶體陣列101有m個正常列和一參考列,共用一感應放大器做差動感應。於同一列的每個記憶體存儲單元110有一電阻元件111被耦合到當編程選擇器的一二極體112的P端和到一位元線BL j170-j(j=0,1,..m-1)或參考位元線BLR01-0。在同一行的記憶體存儲單元110的二極體112的N端經由局部字元線LWLBi154-i,(i=0,1,…,n-1)被耦合到一字元線WLBi152-i,。每個字元線WLBi被耦合到至少一局部字元線LWLBi,此處i=0,1,…,n-1。該LWLBi154-i通常由高電阻材料,如N井或多晶矽構建,來連接存儲單元,然後經由接點或層間接點、緩衝器或後解碼器172-i(i=0,1,...,n-1)耦合到WLBi(例如,低電阻金屬WLBi)。當使用二極體作為編程選擇器,可能需要緩衝器或後解碼器172-i,因為有電流流過WLBi,特別是當WLBi驅動多個存儲單元來同時編程和讀取。該字元線WLBi是由字元線驅動器150-i所驅動,為了編程和讀取,其電源電壓vddi可以在不同的電壓之間被切換。每個BLj170-j或BLR0175-0都經由一Y-寫(Y-write)通道閘120-j或125被耦合到一電源電壓VDDP來編程,其中BLj170-j及BLR0175-0分別由被YSWBj(j=0,1,..,m-1)及YSWRB0選取。Y-write通道閘120-j(j=0,1,…,m-1)或125可以由PMOS所建構,然而NMOS,二極體,或雙極型元件可以在一些實施例裏使用。每BL或BLR0經由一Y-read通道閘130-j或135被耦合
到一數據線DLj或參考數據線DLR0,且BL及BLR0分別由YSRj(j=0,1,..,m-1)及YSRR0所選定。在記憶體陣列101這一部分,m正常的數據線DLj(j=0,1,…,m-1)被連接到一感應放大器140的一輸入端160。該參考數據線DLR0提供了感應放大器140的另一輸入端161(一般在參考部分裏不需要多工器)。感應放大器140的輸出端是Q0。
要編程一存儲單元,特定的WLBi和YSWBj被開啟而高電壓被提供到VDDP,其中i=0,1,..,n-1而j=0,1,...,m-1。在一些實例裏,經由打開WLRBi(i=0,1,...,n-1)和YSWRB0,參考存儲單元可以被編程為0或1。要讀取一存儲單元,一數據列線160可以由啟用特定的WLBi和YSRj,(其中i=0,1,...,n-1,和j=0,1,...,m-1)來選到,而一參考數據線DLR0161可以由啟用特定的一參考存儲單元來選到,其皆被耦合到感應放大器140。此感應放大器140可以被用來感應和比較DLj和DLR0與接地之間的電阻差異,同時關閉所有YSWBj和YSWRB0,其中j=0,1,..,m-1。
第十圖a和第十圖b顯示一流程圖實施例,分別描繪一可編程電阻式記憶體的編程方法S700和讀取方法S800。方法S700和S800描述了可編程電阻式記憶體(如第九圖的可編程電阻記憶體100)的編程和讀取。此外,雖然說是一個步驟流程,對此技藝知悉者可知至少一些步驟可能會以不同的順序進行,包括同時或跳過。
第十圖a描繪可編程電阻記憶體編程方法S700的流程。根據此實施例,在第一步驟S710,選擇適當的電源選擇器以施加高電壓電源到字元線和位元線驅動器。在第二步驟S720,在控制邏輯(第九圖裏沒有顯示)裏進行分析要被編程的數據,根據什麼類型的
可編程電阻元件。對於相變記憶體(PCM),編程到一個0(設定)和編程到一個1(重設)需要不同的電壓和持續時間,所以一個控制邏輯決定了輸入數據,並選擇適當的電源選擇器和啟動適當的時序控制信號。在第三步驟S730,選擇一個存儲單元的一行(群),所以相對的局部字元線可被開啟。在第四步驟S740,停用感應放大器,以節省電源和防止干擾到編程的運作。在第五步驟S750,一存儲單元的一列(群),可以被選定並且相對應的Y-write通道閘可以被打開來耦合所選的位元線(群)到一電源電壓。在最後一步驟S760,在一已建立的傳導路徑來驅動所需的電流一段所需要的時間來完成編程的運作。對於大多數可編程電阻記憶體,這個傳導路徑是由一個高壓電源,通過被選的一位元線(群),電阻元件,作為編程選擇器的二極體,以及一局部字元線(群)驅動器的NMOS下拉元件到接地。
第十圖b描繪可編程電阻記憶體讀取方法S800流程圖。在第一步驟S810,提供合適的電源選擇器來選電源電壓給局部字元線驅動器,感應放大器和其他電路。在第二步驟S820,所有Y-write通道閘,例如位元線編程選擇器,可以被關閉。在第三步驟S830,所需的局部字元線驅動器(群)可以被選,使作為編程選擇器(群)的二極體(群)具有傳導路徑到接地。在第四步驟S840,啟動感應放大器和準備感應的輸入信號。在第五步驟S850,數據線和參考數據線被預先充電到可編程電阻元件存儲單元的V-電壓。在第六步驟S860,選所需的Y-read通道閘,使所需的位元線被耦合到感應放大器的一輸入端。一傳導路徑於是被建立,從位元線到所要的存儲單元的電阻元件,作為編程選擇器(群)的二極體
(群)和局部字元線驅動器的下拉元件到接地。這同樣適用於參考分支。在最後一步驟S870,感應放大器可以比較讀取電流與參考電流的差異來決定邏輯輸出是0或1以完成讀取操作。
第十一圖顯示了一種處理器系統700的一實施例。根據此實施例,處理器系統700可以包括在記憶體740中的可編程電阻元件744(例如在存儲單元陣列742裏)。處理器系統700可以,例如屬於一電腦系統。電腦系統可以包括中央處理單元(CPU)710,它經由共同匯流排715來和多種記憶體和周邊裝置溝通,如輸入輸出單元720,硬盤驅動器730,光碟750,記憶體740,和其他記憶體760。其他記憶體760是一種傳統的記憶體如靜態記憶體(SRAM),動態記憶體(DRAM),或閃存記憶體(flash),通常經由記憶體控制器來和與中央處理單元710溝通。中央處理單元710一般是一種微處理器,一種數位信號處理器,或其他可編程數位邏輯元件。記憶體740最好是以積體電路來構造,其中包括具有至少有一可編程電阻元件744的存儲單陣列742。通常,記憶體740經由記憶體控制器來接觸中央處理單元710。如果需要,可合併記憶體740與處理器(例如中央處理單元710)在單片積體電路。
本發明可以部分或全部實現於積體電路上,在印刷電路板(PCB)上,或在系統上。該可編程電阻元件可以是熔絲,反熔絲,或新出現的非揮發行性記憶體。熔絲可以是矽化或非矽化多晶矽熔絲,熱隔離的主動區熔絲,金屬熔絲,接點熔絲,或層間接點熔絲。反熔絲可以是一個閘極氧化層崩潰反熔絲,介電質於其間的接點或層間接點反熔絲。新出現的非揮發行性記憶體可以是磁性記憶體(MRAM),相變記憶體(PCM),導電橋隨機存取記憶
體(CBRAM),或電阻隨機存取記憶體(RRAM)。雖然編程機制不同,其邏輯狀態可以由不同的電阻值來區分。
然以上所述者,僅為本發明之較佳實施例,當不能限定本發明實施之範圍,即凡依本發明申請專利範圍所作之均等變化與修飾等,皆應仍屬本發明之專利涵蓋範圍意圖保護之範疇。
30‧‧‧存儲單元
31‧‧‧可逆性可編程電阻元件
32‧‧‧多晶矽二極體
Claims (14)
- 一種可逆性可編程電阻式記憶體,包括:多個可逆性可編程電阻式存儲單元,至少有一可逆性可編程電阻式存儲單元包括:一可逆性可編程電阻式元件耦合到第一電源電壓線;及一二極體建構於多晶矽上,包括至少一第一端和一第二端,其中該第一端具有一第一型摻雜,該第二端具有一第二型的摻雜,該第一端提供了該二極體的一第一端,該第二端提供二極體的一第二端,該第一端和第二端皆存在一共同的多晶矽上,該第一端被耦合到該可逆性可編程電阻式元件,而該第二端被耦合到第二電源電壓線;該多晶矽係位於一矽基體上;其中第一和第二端的摻雜劑是從互補式金氧半導體(CMOS)元件的源極或汲極的摻雜植入製造,其中,經由施加電壓到該第一和第二電源電壓線,該可逆性可編程電阻式元件被配置為可編程,從而改變電阻為不同的邏輯狀態;其中該可逆性可編程電阻式元件在平行於該矽基體的兩個維度上,至少沿一個維度上該可逆性可編程電阻式元件之長度大於從可逆性可編程電阻式元件到多晶矽表面的高度。
- 如申請專利範圍第1項之可逆性可編程電阻式記憶體,其中可逆性電阻元件是相變薄膜可以有化學成分鍺(Ge),銻(Sb)和碲(Te)。
- 如申請專利範圍第1項之可逆性可編程電阻式記憶體,其中可逆性電阻元件是金屬或金屬合金電極和電極之間的金屬氧化物。
- 如申請專利範圍第1項之可逆性可編程電阻式記憶體,其中可逆性電阻元件是電極和電極之間的固態電解質薄膜。
- 如申請專利範圍第1項之可逆性可編程電阻式記憶體,其中可逆性電阻元件在不同的存儲單元裏彼此分離。
- 如申請專利範圍第1項之可逆性可編程電阻式記憶體,其中可逆性電阻元件實質是平面的。
- 如申請專利範圍第1項之可逆性可編程電阻式記憶體,其中該可逆性可編程電阻式元件具有一薄膜,該薄膜面積為A,該薄膜經由一接點而耦合到多晶矽表面,該接點面積為B,且其中A和B滿足關係:A/B>2。
- 如申請專利範圍第1項之可逆性可編程電阻式記憶體,其中兩摻雜植入端為二極體的兩端,被一矽化物阻擋層分開,其矽化物阻擋層至少重疊第一和第二端的一部分。
- 如申請專利範圍第1項之可逆性可編程電阻式記憶體,其中該可逆性可編程電阻式元件被構建成可編程,由一高電壓和/或短持續時間到一狀態,而一低電壓和/或長持續時間到另一狀態。
- 如申請專利範圍第1項之可逆性可編程電阻式記憶體,其中該可逆性可編程電阻式元件被構建成由使用的電流限制或電壓限制來編程。
- 一種相變記憶體,包括:多個相變存儲單元,至少有一相變存儲單元包括:一相變薄膜耦合到第一電源電壓線;及一二極體包括至少一第一端和一第二端,其中該第一端具有一第 一型摻雜,該第二端具有一第二型摻雜,該第一端提供了該二極體的一第一端而該第二端提供該二極體的一第二端,該第一端和第二端皆存在一個共同的多晶矽上,該第一端耦合到相變薄膜,而該第二端耦合到第二電源電壓線;該多晶矽係位於一矽基體上;其中該第一和第二端的摻雜是從互補式金氧半導體(CMOS)元件的源極或汲極的摻雜植入製造,其中,經由施加電壓到第一和第二電源電壓線,相變薄膜被配置為可編程,從而可逆的改變電阻為不同的邏輯狀態;其中該相變存儲單元在平行於該矽基體的兩個維度上,至少沿一個維度上該相變存儲單元之長度大於從該相變存儲單元到多晶矽表面的高度。
- 一種電子系統,包括:一種處理器;及一可逆性可編程電阻式記憶體可操作地連接到處理器,該可逆性可編程電阻式記憶體包括至少數個可逆性可編程電阻存儲單元來提供數據存儲,每個可逆性可編程電阻存儲單元包括:一可逆性可編程電阻元件被耦合到第一電源電壓線;及一二極體包含至少一第一端和一第二端,其中該第一端具有第一型摻雜,而該第二端具有第二型摻雜,該第一端提供了二極體的一第一端,該第二端提供二極體的一第二端,該第一和第二端皆存在一個共同的多晶矽上,該第一端耦合到該可逆性可編程電阻元件而該第二端耦合到一第二電源電壓線;其中該第一和第二端的摻雜是從互補式金氧半導體(CMOS)元件的源極或汲極的摻雜植入製造; 其中,經由施加電壓到第一和第二電源電壓線,可逆性可編程電阻元件被配置為可編程,從而可逆的改變電阻到不同的邏輯狀態;其中該可逆性可編程電阻式元件在平行於該矽基體的兩個維度上,至少沿一個維度上該可逆性可編程電阻式元件之長度大於從可逆性可編程電阻式元件到多晶矽表面的高度。
- 如申請專利範圍第12項之電子系統,其中該電子系統被構建成定期讀取每個存儲單元的內容,並寫回內容。
- 一種方法來提供一個可逆性電阻式記憶體,包括:提供多個可逆性可編程電阻存儲單元,至少有一可逆性可編程電阻存儲單元包括至少(i)一可逆性可編程電阻元件被耦合到第一電源電壓線;及(ii)一二極體包含至少一第一端和一第二端,該第一端具有第一型摻雜,而該第二端具有第二型摻雜,該第一端提供了該二極體的一第一端,該第二端提供該二極體的一第二端,該第一和第二端皆存在一個共同的多晶矽上,該多晶矽係位於一矽基體上,而其摻雜是從互補式金氧半導體(CMOS)元件的源極或汲極的摻雜植入製造,該第一端耦合到電阻元件而該第二端耦合到一第二電源電壓線;及經由施加電壓到第一和第二電壓線,來編程至少一可逆性可編程電阻存儲單元到一邏輯狀態;其中該可逆性可編程電阻式元件在平行於該矽基體的兩個維度上,至少沿一個維度上該可逆性可編程電阻式元件之長度大於從可逆性可編程電阻式元件到多晶矽表面的高度。
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US20120044747A1 (en) | 2012-02-23 |
US8804398B2 (en) | 2014-08-12 |
TWI479487B (zh) | 2015-04-01 |
CN102522499B (zh) | 2014-09-24 |
CN102522499A (zh) | 2012-06-27 |
TWI445137B (zh) | 2014-07-11 |
CN102376360B (zh) | 2015-03-04 |
CN102376359A (zh) | 2012-03-14 |
CN102376359B (zh) | 2014-10-01 |
TW201225219A (en) | 2012-06-16 |
TW201214430A (en) | 2012-04-01 |
TW201220566A (en) | 2012-05-16 |
CN102376360A (zh) | 2012-03-14 |
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