TWI487082B - 積體電路結構及背面受光型影像感測裝置 - Google Patents

積體電路結構及背面受光型影像感測裝置 Download PDF

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Publication number
TWI487082B
TWI487082B TW100136015A TW100136015A TWI487082B TW I487082 B TWI487082 B TW I487082B TW 100136015 A TW100136015 A TW 100136015A TW 100136015 A TW100136015 A TW 100136015A TW I487082 B TWI487082 B TW I487082B
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Taiwan
Prior art keywords
layer
semiconductor substrate
opening
dielectric
metal
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TW100136015A
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English (en)
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TW201308555A (zh
Inventor
Jeng Shyan Lin
Dun Nian Yaung
Jen Cheng Liu
Wen De Wang
Shuang Ji Tsai
Yueh Chiou Lin
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Taiwan Semiconductor Mfg Co Ltd
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Publication of TW201308555A publication Critical patent/TW201308555A/zh
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Description

積體電路結構及背面受光型影像感測裝置
本發明係有關於一種積體電路結構，特別是有關於一種背面受光型(backside illumination,BSI)影像感測裝置中的接墊結構。
由於背面受光型(BSI)影像感測晶片具有較高的光子捕獲效率而取代了正面光型影像感測晶片。在BSI影像感測晶片的製造中，影像感測器及邏輯電路形成於晶圓的矽基底上，接著在矽晶片的正面形成內連結構。內連結構包括覆數個金屬層，其包括底層金屬層M1至頂層金屬層Mtop。
接著，翻轉晶圓，從矽基底的背面對矽基底進行背側研磨。一緩衝氧化層可形成於剩餘的矽基底的背表面，並形成一第一開口，其自緩衝氧化層延伸並終止於矽基底內的淺溝槽隔離(shallow trench isolation,STI)襯墊。接著在第一開口內形成一第二開口，以進一步蝕刻STI襯墊以及位於被蝕刻的STI襯墊下方的內層介電(interlayer dielectric,ILD)層，而露出底層金屬層M1中的金屬接墊。第二開口小於第一開口。接著在第一開口及第二開口內形成一鋁銅接墊，且電性耦接至底層金屬層M1中的金屬接墊。鋁銅接墊可用於接合至BSI晶片。
可以發現在傳統的接合結構會在接合球剪力測試期間遭遇到膜層剝離問題。底層金屬層M1中的金屬接墊，其接合至鋁銅接墊，可能會從下方的蝕刻終止層剝離。金屬接墊與蝕刻終止層(其通常由碳化矽所構成)之間不佳的黏著力會造成剝離。
在本發明一實施例中，一種積體電路結構，包括：一半導體基底，包括一前側及一背側；一低介電常數介電層，位於半導體基底的前側上；一非低介電常數介電層，位於低介電常數介電層上；一金屬接墊，位於非低介電常數介電層上；一開口，自半導體基底的背側延伸穿過半導體基底、非低介電常數介電層及低介電常數介電層，其中開口露出金屬接墊的一表面；以及一鈍化保護層，形成於開口的側壁及底部，其中位於開口的底部的鈍化保護層局部覆蓋金屬接墊的露出表面。
在本發明另一實施例中，一種積體電路結構，包括：一半導體基底；一淺溝槽隔離襯墊，自半導體基底的一前表面延伸於半導體基底內；一影像感測器，設置於半導體基底的前表面上；複數個介電層，位於影像感測器及半導體基底的前表面上；一金屬接墊，位於介電層上；一開口，自半導體基底的一背表面延伸至半導體基底的前表面，穿過淺溝槽隔離襯墊及介電層，且露出一部分的金屬接墊；以及一鈍化保護層，形成於開口的側壁及底部，其中位於開口的底部的鈍化保護層局部覆蓋金屬接墊的露出部分。
在本發明又一實施例中，一種背面受光型影像感測裝置，包括：一半導體基底，其具有一前側及一背側；複數個介電層，位於半導體基底的該前側上；一金屬接墊，位於介電層上；一開口，自半導體基底的背側延伸穿過半導體基底及介電層，以露出一部分的金屬接墊；以及一凸塊，形成於開口內，以電性連接金屬接墊。
以下說明本發明實施例之製作與使用。然而，可輕易了解本發明實施例提供許多合適的發明概念而可實施於廣泛的各種特定背景。所揭示的特定實施例僅僅用於說明以特定方法製作及使用本發明，並非用以侷限本發明的範圍。
以下根據不同實施例提供用於背面受光型(BSI)影像感測裝置的接墊結構及其製造方法。以下以圖式說明BSI接墊結構的中間製造階段並詳細說明各個實施例。全文中各個圖式及實施例說明中，相同的部件係以相同的標號表示之。
第1至6圖係繪示出根據一些實施例之接墊結構的中間製造階段剖面示意圖。第1圖係繪示出一影像感測晶片20，其為晶圓22的一部分。影像感測晶片20包括半導體基底26，其為單晶矽基底或由其他半導體材料所構成的半導體基底。在以下的內文中，表面26A表示為半導體基底26的前表面，而表面26B表示為半導體基底26的背表面。影像感測器24可為光敏金氧半(MOS)電晶體或光敏二極體，其形成於半導體基底26的表面。因此，晶圓22可為一影像感測晶圓。在以下內文中，影像感測器24所處的一側表示為半導體基底26的前側，而其相對側則為半導體基底26的背側。介電襯墊36可為淺溝槽隔離(shallow trench isolation,STI)襯墊，其自半導體基底26的上表面(其為前表面26A)延伸於半導體基底26內。
內連結構28形成於半導體基底26上方，且用於電性內連接影像感測晶片20內的裝置。內連結構28包括內層介電(interlayer dielectric,ILD)層25，其形成於半導體基底26上方，其中接觸插塞(未繪示)可形成於ILD層25內。金屬層包括位於介電層30內的金屬線/接墊32及介層窗(via)34。影像感測器24可電性耦接至位於金屬層M1至Mtop內的金屬線/接墊32及介層窗34。
金屬層係標示為M1、M2...至Mtop，其中金屬層M1為內連結構28的底層金屬層，而金屬層Mtop則為內連結構28的頂層金屬層。在圖示實施例中，具有四層金屬層且金屬層Mtop為M4。然而，晶圓22可包括更多或更少層的金屬層。在一實施例中，介電層30(其內形成了金屬層M1至Mtop內的金屬線/接墊32及介層窗34)為低介電常數(low-k)介電層，例如，其介電常數值低於3.0或低於2.5。
介電層38形成於金屬層Mtop的上方。介電層38可由非低介電常數(low-k)介電材料所構成，其介電常數(k值)大於3.9。在一實施例中，介電層38由氧化物所構成，例如未摻雜矽玻璃(undoped silicate glass,USG)、硼摻雜矽玻璃(boron-doped silicate glass,BSG)、磷摻雜矽玻璃(phosphorous-doped silicate glass,PSG)或硼摻雜磷矽玻璃(boron-doped phosphor-silicate glass,BPSG)等等。介電層38也可由氧化矽層及位於其上的氮化矽層所構成。
黏合層40形成於介電層38的上方，且延伸於介電層38的一開口內，以電性耦接金屬線32(其位於金屬層Mtop內)。在一實施例中，黏合層40由鉭、氮化鉭、鈦或氮化鈦等等所構成。形成於黏合層40上方為金屬特徵部件(feature)44，其包括金屬接墊44A及金屬線44B。金屬特徵部件44可包括鋁或鋁銅合金等等。黏著層40可謂於介電層38與金屬特徵部件44之間，並與其接觸。黏合層46可形成於金屬特徵部件44上方，其中黏合層46可由鉭、氮化鉭、鈦或氮化鈦等等所構成。黏合層40及46與金屬特徵部件44的製做可包括形成第一黏合層、在第一黏合層上方形成一金屬層、在金屬層上方形成一第二黏合層以及使用相同的罩幕層來圖案化第一黏合層、金屬層及第二黏合層。因此，黏合層40及46與金屬特徵部件44為共邊界(co-terminus)，其各自的邊緣彼此垂直對準。
鈍化保護層47係形成於黏合層46及介電層38。類似於介電層38，鈍化保護層47由非低介電常數(low-k)介電材料所構成，其k值大於3.9。在一實施例中，鈍化保護層47由一氧化物所構成，例如USG、BSG或BPSG等等。鈍化保護層47也可由氧化矽層及位於其上的氮化矽層所構成。鈍化保護層47完全封住黏合層40及46與金屬特徵部件44。
請參照第2圖，翻轉晶圓22，且貼合至一載板(未繪示)，其位於晶圓22下方。因此，第1圖中每一特徵部件的上表面變為下表面，反之亦然。半導體基底26面向上，如第2圖所示。進行背側研磨以薄化半導體基底26，直至晶圓22的厚度小於約20微米(μm)或小於10微米。最終半導體基底26的背表面標示為26B。在此厚度下，光能夠自半導體基底26的背側(其與前側相對)穿透剩餘的半導體基底26而抵達影像感測器24。在進行薄化之後，緩衝氧化層48可形成於半導體基底26的背表面。在一實施例中，緩衝氧化層48包括一氧化矽層、位於氧化矽層上的一底層抗反射(bottom anti-reflective coating,BARC)層以及位於BARC層上的另一氧化矽層，然而緩衝氧化層48也可具有不同的結構且由不同材料所構成。罩幕層50可為一光阻層，其形成於晶圓22上，接著進行圖案化。
請參照第3圖，蝕刻緩衝氧化層48及半導體基底26以形成開口52。接著去除罩幕層50。在此蝕刻步驟中，STI襯墊36係作為蝕刻終止層，且蝕刻步驟係終止於STI襯墊36上。因而開口52露出STI襯墊36的上表面。
第4圖係繪示出金屬遮蔽層55與緩衝氧化層56的製做。在一實施例中，金屬遮蔽層55的製做包括形成一金屬層，接著圖案化金屬層以留下金屬遮蔽層55位於局部的半導體基底26上，使金屬遮蔽層55阻擋光抵達部分的裝置(例如電晶體(未繪示))，其位於金屬遮蔽層55正下方。金屬遮蔽層55可包括鋁及/或銅。在形成金屬遮蔽層55之後，形成緩衝氧化層56。緩衝氧化層56可由相似於緩衝氧化層48的材料所構成。緩衝氧化層56包括位於半導體基底26上的一第一部以及延伸於開口52內的一第二部。第二部更包括一部分位於半導體基底26側壁上以及一部分位於STI襯墊36上。
接著，請參照第5圖，形成光阻層58並圖案化，再以光阻層58作為蝕刻罩幕來蝕刻STI襯墊36，因而形成開口60。需注意的是為了繪示出金屬層細節部分，圖示中開口60的深寬比(aspect ratio)大於形成於實體晶圓上的實際開口的深寬比。實際開口的水平尺寸明顯大於開口60的高度(有時大於數十倍)。在進行蝕刻期間，也蝕刻低介電常數介電層30及非低介電常數介電層38，且終止於金屬接墊44A。在進行蝕刻期間，可去除因開口60而露出的黏合層40的部分。如此一來，開口60露出金屬接墊44A。接著去除光阻層58。在所產生的結構中，開口52及60構成一連續開口。
第6圖係繪示出鈍化保護層62的製做，其可由氧化層(例如，氧化矽層)及一氮化層(例如，氮化矽層)所構成。鈍化保護層62延伸於緩衝氧化層56的上表面上，且延伸於開口52及60內。鈍化保護層62包括位於開口60側壁的部分，以便於防止水氣進入介電層30。進行一圖案化步驟，以去除鈍化保護層62位於開口60底部的部分而露出金屬接墊44A。另外，可去除位於影像感測器24正上方的鈍化保護層62。因此，光(標示為曲線箭號70)可穿透緩衝氧化層48/56及半導體基底26以抵達影像感測器24(其將光轉換成電子信號)。
在一實施例中，進行打線接合以形成打線接合凸塊68，其與金屬接墊44A接合。打線接合凸塊68可包括金或鋁等等。可在切割晶圓22成影像感測晶片之後進行打線接合。在所產生的結構中，打線接合凸塊68可與金屬接墊44A直接接觸。
在本實施例中，打線接合凸塊68與金屬接墊44A(位於黏合層46上)接合。黏合層46對於鈍化保護層47及金屬接墊44A兩者具有良好的黏著性。因此，上述接合的機械強度優於傳統接合。在傳統接合製程中，打線接合凸塊形成於底層金屬層M1內的金屬特徵部件上，而金屬特徵部件因較差的黏著性或是因脆弱的低介電常數介電材料而可能自下方的蝕刻終止層剝離。
根據上述實施例，一種積體電路結構包括：一半導體基底及自半導體基底的下表面向上延伸於半導體基底內的一介電襯墊。一低介電常數介電層設置於半導體基底的下方。一第一非低介電常數介電層設置於低介電常數介電層下方。一金屬接墊位於第一非低介電常數介電層下方。一第二低介電常數介電層位於金屬接墊下方。一開口自半導體基底的上表面向下穿過半導體基底、介電襯墊以及低介電常數介電層，其中開口位於金屬接墊的上表面上。一鈍化保護層包括位於開口側壁的一部分，其中去除位於開口底部的一部分的鈍化保護層。
根據其他實施例，一種積體電路結構包括一半導體基底。一淺溝槽隔離襯墊自半導體基底的一背表面延伸於半導體基底內。一影像感測器設置於半導體基底的背表面上。複數個低介電常數介電層設置於半導體基底的下方。一第一非低介電常數介電層設置於低介電常數介電層下方。一金屬接墊位於第一非低介電常數介電層下方。一第一開口自半導體基底的一前表面延伸至淺溝槽隔離襯墊的上表面。一第二開口自淺溝槽隔離襯墊的上延伸至金屬接墊的上表面，其中第一開口與第二開口連接而構成依連續開口。一鈍化保護層具有一第一部位於半導體基底正上方以及一第二部位於第一開口側壁及第二開口側壁。鈍化保護層具有一開口位於第二開口的底部。
又根據其他實施例中，一方法包括從一半導體基底的背側蝕刻半導體基底，以形成一第一開口。第一開口終止於半導體基底內淺溝槽隔離襯墊的上表面。接著蝕刻淺溝槽隔離襯墊、位於淺溝槽隔離襯墊下方的低介電常數介電層以及位於低介電常數介電層下方的非低介電常數介電層，以形成一第二開口，其中位於非低介電常數介電層下方的金屬接墊的上表面經由第二開口而露出。第一及第二開口構成一連續開口。一鈍化保護層形成於半導體基底上方，其中鈍化保護層延伸於第一開口的側壁及底部以及第二開口的底部。自第二開口的底部去除鈍化保護層的底部部份，以露出金屬接墊，其中並未去除鈍化保護層的側壁部分。
雖然本發明實施例及其優點已詳細揭露如上，然而可以理解的是其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。再者，本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此，本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外，每一申請專利範圍構成個別的實施例，且本發明之保護範圍也包括各個申請專利範圍及實施例的組合。
20．．．影像感測晶片
22．．．晶圓
24．．．影像感測器
25．．．內層介電層
26．．．半導體基底
26A、26B．．．表面
28．．．內連結構
30、38．．．介電層
32．．．金屬線/接墊
34．．．介層窗
36．．．介電襯墊/淺溝槽隔離襯墊
40、46．．．黏合層
44．．．金屬特徵部件
44A．．．金屬接墊
44B．．．金屬線
47、62．．．鈍化保護層
48、56．．．緩衝氧化層
50．．．罩幕層
52、60．．．開口
55．．．金屬遮蔽層
58．．．光阻層
68．．．打線接合凸塊
70．．．光
M1、M2、M3、M4、Mtop．．．金屬層
第1至6圖係繪示出根據不同實施例之背面受光型影像感測晶圓中接墊結構於中間製造階段的剖面示意圖。
22．．．晶圓
24．．．影像感測器
25．．．內層介電層
26．．．半導體基底
28．．．內連結構
30、38．．．介電層
32．．．金屬線/接墊
34．．．介層窗
36．．．介電襯墊/淺溝槽隔離襯墊
40、46．．．黏合層
44．．．金屬特徵部件
44A．．．金屬接墊
47、62．．．鈍化保護層
48、56．．．緩衝氧化層
52、60．．．開口
55．．．金屬遮蔽層
68．．．打線接合凸塊
70．．．光

Claims (8)

  1. 一種積體電路結構，包括：一半導體基底，包括一前側及一背側；一金屬遮蔽層，位於該半導體基底的該背側上；一低介電常數介電層，位於該半導體基底的該前側上；一第一非低介電常數介電層，位於該低介電常數介電層上；一金屬接墊，位於該第一非低介電常數介電層上；一第二非低介電常數介電層，位於該金屬接墊上；一第二黏合層，位於該金屬接墊及該第二非低介電常數介電層之間；一開口，自該半導體基底的該背側延伸穿過該半導體基底、該第一非低介電常數介電層及該低介電常數介電層，其中該開口露出該金屬接墊的一表面；一緩衝氧化層，直接鄰接於該半導體基底的側壁並且延伸覆蓋於該金屬遮蔽層之上；以及一鈍化保護層，形成於該開口的側壁及底部，其中位於該開口的底部的該鈍化保護層局部覆蓋該金屬接墊的該露出表面，其中該鈍化保護層延伸覆蓋於該金屬遮蔽層及一部分的該緩衝氧化層之上。
  2. 如申請專利範圍第1項所述之積體電路結構，更包括：一介電襯墊，自該半導體基底的該前側延伸於該半導體基底內，其中該開口穿過該介電襯墊；以及 一影像感測器，設置於該半導體基底的該前側上。
  3. 如申請專利範圍第1項所述之積體電路結構，更包括一凸塊，位於該開口內且電性耦接至該金屬接墊，其中該凸塊與該金屬接墊直接接觸。
  4. 如申請專利範圍第1項所述之積體電路結構，更包括一第一黏合層，位於該金屬接墊與該第一非低介電常數介電層之間，其中該開口延伸於該第一黏合層內。
  5. 一種積體電路結構，包括：一半導體基底；一淺溝槽隔離襯墊，自該半導體基底的一前表面延伸於該半導體基底內；一影像感測器，設置於該半導體基底的該前表面上；複數個介電層，位於該影像感測器及該半導體基底的該前表面上；一金屬接墊，位於該等介電層上；一第一黏合層，位於該金屬接墊與該等介電層之間；一第二非低介電常數介電層，位於該金屬接墊上；一第二黏合層位於該金屬接墊與該第二非低介電常數介電層之間；一開口，自該半導體基底的一背表面延伸至該半導體基底的該前表面，穿過該淺溝槽隔離襯墊、該等介電層及該第一黏合層，且露出一部分的該金屬接墊；以及一鈍化保護層，形成於該開口的側壁及底部，其中位於該開口的底部的該鈍化保護層局部覆蓋該金屬接墊的該露出部分，其中在該開口的側壁處該鈍化保護層直 接鄰接於該等介電層。
  6. 如申請專利範圍第5項所述之積體電路結構，其中該等介電層包括位於該半導體基底的該前表面上的至少一低介電常數介電層以及位於該低介電常數介電層上的一第一非低介電常數介電層。
  7. 一種背面受光型影像感測裝置，包括：一半導體基底，其具有一前側及一背側；一金屬遮蔽層，位於該半導體基底的該背側上；複數個介電層，位於該半導體基底的該前側上；一金屬接墊，位於該等介電層上；一非低介電常數介電層，位於該金屬接墊上；一黏合層位於該金屬接墊與該非低介電常數介電層之間；一開口，自該半導體基底的該背側延伸穿過該半導體基底及該等介電層，以露出一部分的該金屬接墊；一凸塊，形成於該開口內，以電性連接該金屬接墊；以及一鈍化保護層，直接鄰接於該凸塊及該等介電層，其中該鈍化保護層延伸覆蓋於該金屬遮蔽層之一頂部表面。
  8. 如申請專利範圍第7項所述之背面受光型影像感測裝置，更包括：一影像感測器，形成於該半導體基底的該前側上，且被該等介電層所覆蓋；以及一淺溝槽隔離結構，形成於該半導體基底的該前側 上，其中該開口穿過該淺溝槽隔離結構。
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Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9013022B2 (en) 2011-08-04 2015-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. Pad structure including glue layer and non-low-k dielectric layer in BSI image sensor chips
US8987855B2 (en) * 2011-08-04 2015-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. Pad structures formed in double openings in dielectric layers
US9006900B2 (en) * 2013-03-11 2015-04-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with advanced pad structure resistant to plasma damage and method for forming the same
CN104103511B (zh) * 2013-04-03 2017-03-08 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法
JP6200188B2 (ja) * 2013-04-08 2017-09-20 キヤノン株式会社 固体撮像装置、その製造方法及びカメラ
KR20140141400A (ko) * 2013-05-29 2014-12-10 삼성전자주식회사 디스플레이 장치
US9337225B2 (en) * 2013-09-13 2016-05-10 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
CN104637961B (zh) * 2013-11-13 2018-09-11 联华电子股份有限公司 半导体结构及其制造方法
US9117879B2 (en) * 2013-12-30 2015-08-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
JP6200835B2 (ja) 2014-02-28 2017-09-20 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
EP3032583B1 (en) 2014-12-08 2020-03-04 ams AG Integrated optical sensor and method of producing an integrated optical sensor
US9748301B2 (en) 2015-01-09 2017-08-29 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
KR102437163B1 (ko) 2015-08-07 2022-08-29 삼성전자주식회사 반도체 소자
US10038025B2 (en) 2015-12-29 2018-07-31 Taiwan Semiconductor Manufacturing Co., Ltd. Via support structure under pad areas for BSI bondability improvement
FR3059143B1 (fr) * 2016-11-24 2019-05-31 Stmicroelectronics (Crolles 2) Sas Puce de capteur d'image
CN107204349A (zh) * 2017-07-19 2017-09-26 武汉新芯集成电路制造有限公司 一种铝垫放置方法以及铝垫结构
US20190027531A1 (en) * 2017-07-19 2019-01-24 Omnivision Technologies, Inc. Image sensor module having protective structure
JP2019129215A (ja) * 2018-01-24 2019-08-01 キヤノン株式会社 撮像装置および表示装置
US10707089B2 (en) * 2018-03-27 2020-07-07 Texas Instruments Incorporated Dry etch process landing on metal oxide etch stop layer over metal layer and structure formed thereby
WO2019195385A1 (en) * 2018-04-03 2019-10-10 Corning Incorporated Precision structured glass article having emi shielding and methods for making the same
US10707358B2 (en) * 2018-07-04 2020-07-07 Globalfoundries Singapore Pte. Ltd. Selective shielding of ambient light at chip level
US11227836B2 (en) * 2018-10-23 2022-01-18 Taiwan Semiconductor Manufacturing Company, Ltd. Pad structure for enhanced bondability
KR102639539B1 (ko) 2018-11-05 2024-02-26 삼성전자주식회사 이미지 센서 및 이의 형성 방법
US11211352B2 (en) * 2019-10-01 2021-12-28 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure to prevent metal redeposit and to prevent bond pad consumption and corrosion
US20210143114A1 (en) * 2019-11-08 2021-05-13 Nanya Technology Corporation Semiconductor device with edge-protecting spacers over bonding pad
US20220367554A1 (en) * 2021-05-17 2022-11-17 Taiwan Semiconductor Manufacturing Co., Ltd. Bond pad structure with high via density

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090146148A1 (en) * 2007-12-05 2009-06-11 Magnachip Semiconductor, Ltd. Backside illuminated image sensor
US20090185060A1 (en) * 2008-01-21 2009-07-23 Sony Corporation Solid-state imaging device, method of fabricating solid-state imaging device, and camera

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100533166B1 (ko) * 2000-08-18 2005-12-02 매그나칩 반도체 유한회사 마이크로렌즈 보호용 저온산화막을 갖는 씨모스이미지센서및 그 제조방법
JP2004095611A (ja) * 2002-08-29 2004-03-25 Fujitsu Ltd 半導体装置およびその製造方法
JP4858898B2 (ja) 2003-12-26 2012-01-18 富士通セミコンダクター株式会社 半導体装置とその製造方法
US20050142715A1 (en) 2003-12-26 2005-06-30 Fujitsu Limited Semiconductor device with high dielectric constant insulator and its manufacture
US9038973B2 (en) * 2007-07-12 2015-05-26 Panduit Corp. Accessory bracket
US7659595B2 (en) 2007-07-16 2010-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded bonding pad for backside illuminated image sensor
JP5357441B2 (ja) 2008-04-04 2013-12-04 キヤノン株式会社 固体撮像装置の製造方法
JP5422914B2 (ja) * 2008-05-12 2014-02-19 ソニー株式会社 固体撮像装置の製造方法
KR100882991B1 (ko) 2008-08-06 2009-02-12 주식회사 동부하이텍 후면 수광 이미지센서의 제조방법
JP4655137B2 (ja) 2008-10-30 2011-03-23 ソニー株式会社 半導体装置
JP2011003645A (ja) 2009-06-17 2011-01-06 Sharp Corp 半導体装置およびその製造方法
US9013022B2 (en) 2011-08-04 2015-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. Pad structure including glue layer and non-low-k dielectric layer in BSI image sensor chips

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090146148A1 (en) * 2007-12-05 2009-06-11 Magnachip Semiconductor, Ltd. Backside illuminated image sensor
US20090185060A1 (en) * 2008-01-21 2009-07-23 Sony Corporation Solid-state imaging device, method of fabricating solid-state imaging device, and camera

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