CN102915991B - Bsi图像传感器芯片中的焊盘结构 - Google Patents

Bsi图像传感器芯片中的焊盘结构 Download PDF

Info

Publication number
CN102915991B
CN102915991B CN201110353065.0A CN201110353065A CN102915991B CN 102915991 B CN102915991 B CN 102915991B CN 201110353065 A CN201110353065 A CN 201110353065A CN 102915991 B CN102915991 B CN 102915991B
Authority
CN
China
Prior art keywords
semiconductor substrate
dielectric
layer
opening
low
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201110353065.0A
Other languages
English (en)
Other versions
CN102915991A (zh
Inventor
林政贤
杨敦年
刘人诚
王文德
蔡双吉
林月秋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN102915991A publication Critical patent/CN102915991A/zh
Application granted granted Critical
Publication of CN102915991B publication Critical patent/CN102915991B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H01L27/14623—Optical shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1463—Pixel isolation structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1464—Back illuminated imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14685—Process for coatings or optical elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14689—MOS based technologies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11916—Methods of manufacturing bump connectors involving a specific sequence of method steps a passivation layer being used as a mask for patterning other parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H01L2224/48453—Shape of the interface with the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8334—Bonding interfaces of the layer connector
    • H01L2224/83359—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种集成电路结构包括：半导体衬底；以及介电焊盘，该介电焊盘从半导体衬底的底面向上延伸到半导体衬底中。低k介电层被设置在半导体衬底下方。第一非低k介电层位于低k介电层下方。金属焊盘位于第一非低k介电层下方。第二非低k介电层位于金属焊盘下方。开口从半导体衬底的顶面向下延伸，从而穿透半导体衬底、介电焊盘、以及低k介电层，其中，开口位于金属焊盘的顶面上方。钝化层的一部分位于开口的侧壁上，其中，位于开口的底部的钝化层的一部分被去除。本发明还提供了一种BSI图像传感器芯片中的焊盘结构。

Description

BSI图像传感器芯片中的焊盘结构
技术领域
本发明涉及半导体领域，更具体地，本发明涉及一种BSI图像传感器芯片中的焊盘结构。
背景技术
为了捕获光子的更高效率，用背照式(BSI)图像传感器芯片替换前照式传感器芯片。在BSI图像传感器芯片的形成中，在晶圆的硅衬底上方形成图像传感器和逻辑电路，然后在硅芯片的正面上形成互连结构。互连结构包括多个金属层，该多个金属层包括底部金属层M1至顶部金属层Mtop。
然后，翻转该晶圆，在硅衬底上从硅衬底的背面实施背面研磨。可以在保留的硅衬底的背面的上方形成氧化物缓冲层，并且形成从氧化物缓冲层延伸的第一开口，在硅衬底中形成的浅沟槽隔离(STI)焊盘处停止。然而，在第一开口内部形成第二开口，从而进一步蚀刻STI焊盘和层间电介质(ILD)，该层间电介质位于STI焊盘的蚀刻部分正下方，从而将位于底部金属层M1中的金属焊盘暴露出来。第二开口小于第一开口。然后，在第一开口和第二开口中形成铝铜焊盘，并且该铝铜焊盘电连接至位于金属层M1中的金属焊盘。可以将铝铜焊盘用于与BSI芯片相接合。
过去发现，传统的接合结构可能在球剪切试验期间经受膜剥离。位于底部金属层M1中的金属焊盘可能与下层蚀刻停止层分层，其中，金属焊盘接合至铝铜焊盘。可能由于在金属焊盘和蚀刻停止层(通常由碳化硅形成)之间的劣质粘结导致剥离。
发明内容
为了解决现有技术中所存在的问题，根据本发明的一个方面，提供了一种集成电路结构，包括：半导体衬底，包括正面和背面；低k介电层，位于所述半导体衬底的正面上；非低k介电层，位于所述低k介电层上；金属焊盘，位于所述非低k介电层上；开口，从所述半导体衬底的背面延伸，穿透所述半导体衬底、所述非低k介电层、以及所述低k介电层，其中，所述开口暴露出所述金属焊盘的表面；以及钝化层，形成在所述开口的侧壁和底部上，其中，位于所述开口的底部上的所述钝化层部分地覆盖了所述金属焊盘所暴露出的表面。
在该集成电路结构中，进一步包括：介电焊盘，从所述半导体衬底的正面延伸到所述半导体衬底中，其中，所述开口进一步穿透所述介电焊盘。
在该集成电路结构中，进一步包括：图像传感器，被设置在所述半导体衬底的正面上。
在该集成电路结构中，进一步包括：凸块，位于所述开口中，并且电连接至所述金属焊盘。
在该集成电路结构中，述凸块与所述金属焊盘物理接触。
在该集成电路结构中，进一步包括：金属屏蔽层，位于所述半导体衬底的背面上。
在该集成电路结构中，所述钝化层延伸以覆盖所述金属屏蔽层。
在该集成电路结构中，进一步包括：粘合层，位于所述金属焊盘和所述非低k介电层之间，其中，所述开口延伸到所述粘合层中。
根据本发明的另一方面，提供了一种集成电路结构，包括：半导体衬底；浅沟槽隔离(STI)焊盘，从所述半导体衬底的正面延伸到所述半导体衬底中；图像传感器，被设置在所述半导体衬底的正面上；多层介电层，覆盖所述图像传感器和所述半导体衬底的正面；金属焊盘，覆盖所述多层介电层；开口，从所述半导体衬底的背面延伸到所述半导体衬底的正面，穿过所述STI焊盘和所述多层介电层，并且暴露出所述金属焊盘的一部分；以及钝化层，形成在所述开口的侧壁和底部上，其中，位于所述开口的底部上的所述钝化层部分地覆盖了所述金属焊盘所暴露出的部分。
在该集成电路结构中，所述多层介电层包括：至少一层低k介电层，位于所述半导体衬底的正面上方；以及第一非低k介电层，位于所述至少一层低k介电层上。
在该集成电路结构中，进一步包括：第二非低k介电层，位于所述第一非低k介电层上方。
在该集成电路结构中，进一步包括：第一粘合层，位于所述金属焊盘和所述第一非低k介电层之间；以及第二粘合层，位于所述金属焊盘和所述第二非低k介电层之间。
在该集成电路结构中，进一步包括：凸块，位于所述开口中，并且与所述金属焊盘物理接触。
在该集成电路结构中，所述金属焊盘包含铝。
根据本发明的又一方面，提供了一种背照式图像传感器器件，包括：半导体衬底，包括正面和背面；多层介电层，位于所述半导体衬底的正面上；金属焊盘，位于所述多层介电层上；开口，从所述半导体衬底的背面延伸，穿透所述半导体衬底和所述多层介电层，暴露出所述金属焊盘的一部分；以及凸块，形成在所述开口中，以电连接至所述金属焊盘。
在该背照式图像传感器器件中，进一步包括：钝化层，位于所述凸块和所述多层介电层之间。
在该背照式图像传感器器件中，进一步包括：图像传感器，形成在所述半导体衬底的正面上，并且被所述多层介电层覆盖。
在该背照式图像传感器器件中，进一步包括：浅沟槽隔离件，形成在所述半导体衬底的正面上，其中，所述开口穿透所述浅沟槽隔离件。
在该背照式图像传感器器件中，进一步包括：金属屏蔽层，位于所述半导体衬底的背面上。
在该背照式图像传感器器件中，所述金属焊盘包含铝。
附图说明
为了更好地理解实施例及其优点，现在将结合附图所进行的以下描述作为参考，其中：
图1至图6为根据各个实施例的制造背照式图像传感器晶圆的接合焊盘结构的中间阶段的横截面图。
具体实施方式
下面，详细论述本发明实施例的制造和使用。然而，应该理解，本实施例提供了许多可以在各种具体环境中实现的可应用的发明概念。所论述的具体实施例仅仅示出制造和使用本发明的具体方式，而不用于限制本公开的范围。
根据各个实施例提供了一种用于背照式(BSI)图像传感器器件的焊盘结构及其形成方法。示出了形成BSI焊盘结构的中间阶段。论述了形成BSI焊盘结构的中间阶段。论述了实施例的变型例。在整个附图和所描述的实施例中，使用相同的参考标号表示相同的元件。
图1至图6示出了根据一些实施例的制造焊盘结构的中间阶段的横截面图。图1示出了图像传感器芯片20，该图像传感器芯片可以为晶圆22的一部分。图像传感器芯片20包括半导体衬底26，该半导体衬底可以为由其他半导体材料形成的晶体硅衬底或半导体衬底。在通篇描述中，表面26A称为半导体衬底26的正面，表面26B称为半导体衬底26的背面。在半导体衬底26的表面处形成图像传感器24，该图像传感器可以为感光MOS晶体管或者感光二极管。因此，晶圆22可以为图像传感器晶圆。在通篇描述中，将图像传感器24所在的侧面称作半导体衬底的前面，并且将相反侧面称作半导体衬底26的背面。介电焊盘36从半导体衬底26的顶面(该顶面为正面26A)延伸到半导体衬底26中，该介电焊盘可以为浅沟槽隔离(STI)44焊盘。
在半导体衬底26的上方形成互连结构28，将该互连结构用于将图像传感器芯片20中的器件电互连。互连结构28包括形成在半导体衬底26上方的层间介电层(ILD)25，其中，可以在ILD 25中形成接触塞(未示出)。金属层包括：位于介电层30中的金属线/焊盘32和通孔34。图像传感器24可以电连接至金属层M1至Mtop中的金属焊盘/线32和通孔34。
将金属层标记为M1、M2...以及Mtop，其中，金属层M1为互连结构28的底部金属层，并且金属层Mtop为互连结构28的顶部金属层。在所示的实施例中，具有四个金属层，并且金属层Mtop为M4。然而，晶圆22可以包括更多或更少的金属层。在实施例中，在介电层30中形成金属层M1至Mtop的金属线32和通孔34，该介电层30具有低k值，例如，该低k值低于约3.0，或者低于约2.5。
介电层38形成在顶部金属层Mtop上方。介电层38可以由非低k介电材料形成，该非低k介电材料具有大于3.9的k值。在实施例中，介电层38由诸如未掺杂的硅玻璃(USG)、掺硼硅玻璃(BSG)、掺磷硅酸盐玻璃(PSG)、或者掺硼磷硅酸盐玻璃(BPSG)等的氧化物。介电层38还可以由氧化硅层和氧化硅层上的氮化硅层形成。
粘合层40形成在介电层38上方，并且延伸到介电层38中的开口中，从而与金属线32电连接，该金属线位于金属层Mtop中。在实施例中，粘合层40由钽、氮化钽、钛、或氮化钛等形成。金属部件44形成在粘合层40上方，该金属部件包括：金属焊盘44A和金属线44B。金属部件44可以包含铝、铝铜等。粘合层40可以位于介电层38和金属部件44之间，并且与该介电层和金属部件相接触。还可以在金属部件44的上方形成粘合层46，其中，粘合层46可以由钽、氮化钽、钛、或者氮化钛等形成。粘合层40和46以及金属部件44的形成可以包括：形成第一粘合层，在第一粘合层上方形成金属层，在金属层上方形成第二粘合层，以及使用相同的掩模图案化第一粘合层、金属层、和第二粘合层。因此，粘合层40和46以及金属部件44可以为共边界，其中，其相应边缘相互垂直对准。
钝化层47形成在粘合层46和介电层38上方。与介电层38类似，钝化层47可以由非低k介电材料形成，该非低k介电材料具有大于3.9的k值。在实施例中，钝化层47由诸如USG、BSG、或者BPSG等的氧化物形成。例如，钝化层47还可以由氧化硅层和位于氧化硅层上方的氮化硅层形成。钝化层47完全封装(encapsulate)了粘合层40和46以及金属部件44。
参考图2，翻转晶圆2，并且将该晶圆附接至位于晶圆22下方的载体(未示出)。因此，在图1中所示的部件中的每个的顶面变成底面，反之亦然。在图2中，半导体衬底26面朝上。实施例如背面掩模，从而薄化半导体衬底26，直到晶圆22的厚度小于约20μtm，或者小于约10μm。标记生成的半导体衬底26的背面26B。在该厚度处，光可以从半导体衬底26的背面(该背面与正面相反)穿透剩余的半导体衬底26，并且到达图像传感器24。在薄化以后，可以在半导体衬底26的背面上方形成氧化物缓冲层48。在实施例中，氧化物缓冲层48包括：氧化硅层、位于氧化硅层上方的底部防反射涂覆(BARC)层、以及位于BARC层上方的另一氧化层，但是缓冲层48可以具有不同结构，并且该缓冲层可以由不同材料形成。在晶圆22的上方形成掩模50，然后图案化该掩模，该掩模可以为光刻胶。
参考图3，蚀刻氧化物缓冲层48和半导体衬底26，从而形成开口52。然后，去除掩模50。在蚀刻步骤中，将STI焊盘36用作蚀刻停止层，并且在STI焊盘36上蚀刻停止。因此，通过开口52暴露出STI焊盘36的顶面。
图4示出了金属屏蔽层55和氧化物缓冲层56的形成。在实施例中，金属屏蔽层55的形成包括：形成金属层，然后，图案化金属层，从而将金属屏蔽层55保留在半导体衬底26的一部分上方，使得金属屏蔽层55可以防止光到达器件的一部分(例如，晶体管，未示出)，该器件位于金属屏蔽层55正下方。金属屏蔽层55可以包含铝和/或铜。在形成金属屏蔽层55以后，形成氧化物缓冲层56。氧化物缓冲层56可以由与氧化物缓冲层48的材料类似的材料形成。氧化物缓冲层56包括位于半导体衬底26正上方的第一部分，和延伸到开口52中的第二部分。第二部分进一步包括：位于半导体衬底26的侧壁上的部分，和位于STI焊盘36正上方的部分。
接下来，如图5所示，形成和图案化光刻胶58，并且使用光刻胶58作为掩模蚀刻STI焊盘36。因此，形成开口60。注意，为了示出金属层的细节，所示开口60的长宽比大于在实际晶圆上形成的实际开口的长宽比。实际开口的水平尺寸可以显著大于开口60的高度(比如开口60的几十倍)。在蚀刻步骤期间，还蚀刻低k介电层30和非低k介电层38，并且该蚀刻停止于金属焊盘44A上方。可以在蚀刻步骤期间将粘合层40的暴露于开口60的部分去除。结果，金属焊盘44A暴露于开口60。然后，去除光刻胶58。在生成的结构中，开口52和60形成连续开口。
图6示出了钝化层62的形成，该钝化层可以由氧化物层(例如，氧化硅层)和位于氧化物层上方的氮化物层(例如，氮化硅层)形成。钝化层62在氧化物缓冲层56的顶面上延伸，并且延伸到开口52和60中。钝化层62包括位于开口60的侧壁上的部分，从而保护了低k介电层30免于受潮。执行图案化步骤，从而去除了位于开口60的底部处的钝化层62的部分，并且暴露出金属焊盘44A。另外，可以从图像传感器24的正上方去除钝化层62。因此，光(标示为曲线箭头70)可以穿透氧化物缓冲层48/56和半导体衬底26，到达图像传感器24，该图像传感器将光信号转换为电信号。
在实施例中，实施引线接合，从而形成引线接合凸块68，将该引线接合凸块接合至金属焊盘44A。引线接合凸块68可以包括：金、铝等。可以在将晶圆22切割为图像传感器芯片以后实施引线接合。在生成的结构中，引线接合凸块68可以与金属焊盘44A物理接触。
在实施例中，将引线接合凸块68接合至金属凸块44A，该金属焊盘进一步位于粘合层46上方。粘合层46具有与钝化层47和金属焊盘44A的良好粘性。因此，该接合具有比传统接合更好的机械强度。在传统接合中，在底部金属层M1中的金属部件上方形成引线接合凸块，其中，由于劣质粘结，还由于低k介电材料的缺点，金属部件可能与下层蚀刻停止层分层。
根据实施例，一种集成电路结构包括：半导体衬底；以及介电焊盘，从半导体衬底的低面向上延伸到半导体衬底中。低k介电层被设置在半导体衬底下方。第一非低k介电层位于低k介电层下方。金属焊盘位于第一非低k介电层下方。第二非低k介电层位于金属焊盘下方。开口从半导体衬底的顶面向下延伸，穿透半导体衬底、介电焊盘、以及低k介电层，其中，开口位于金属焊盘的顶面上。钝化层包括位于开口的侧壁上的一部分，其中，位于开口底部上的钝化层的部分。
根据其他实施例，集成电路结构包括半导体衬底。STI焊盘从半导体衬底的底面延伸到半导体衬底中。图像传感器被设置在半导体衬底的底面上。多个低k介电层位于半导体衬底下方。第一非低k介电层位于低k介电层下方。金属焊盘位于第一非低k介电层下方。第一开口从半导体衬底的顶面延伸到STI焊盘的顶面。第二开口从STI焊盘的顶面延伸到金属焊盘的顶面，其中，第一开口连接至第二开口，从而形成连续开口。钝化层被形成为具有位于半导体衬底的正上方的第一部分，和位于第一开口的侧壁上和第二开口的侧壁上的第二部分。钝化层具有位于第二开口底部上的开口。
根据又一实施例，一种方法包括：从半导体衬底的背面蚀刻半导体衬底，从而形成第一开口。第一开口停止于半导体衬底中的STI焊盘的顶面处。然后，蚀刻STI焊盘、位于STI焊盘下方的低k介电层、和位于低k介电层下方的非低k介电层，从而形成第二开口，其中，通过第二开口暴露出非低k介电层下方的金属焊盘的顶面。第一开口和第二开口形成连续开口。在半导体衬底的上方形成钝化层，其中，钝化层在第一开口的侧壁和底部以及第二开口的底部上延伸。从第二开口的底部去除钝化层的底部，从而暴露出金属焊盘，其中，钝化层的侧壁部分没有被去除。
尽管已经详细地描述了本实施例及其优势，但应该理解，可以在不背离所附权利要求限定的本实施例的主旨和范围的情况下，做各种不同的改变，替换和更改。而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明，现有的或今后开发的用于执行与本文所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造，材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。此外，每条权利要求构成单独的实施例，并且多个权利要求和实施例的组合在本发明的范围内。

Claims (16)

1.一种集成电路结构，包括：
半导体衬底，包括正面和背面；
金属屏蔽层，位于所述半导体衬底的背面上；
低k介电层，位于所述半导体衬底的正面上；
非低k介电层，位于所述低k介电层上；
金属焊盘，位于所述非低k介电层上；
开口，从所述半导体衬底的背面延伸，穿透所述半导体衬底、所述非低k介电层、以及所述低k介电层，其中，所述开口暴露出所述金属焊盘的表面；
氧化物缓冲层，直接邻接所述半导体衬底的侧壁并且延伸到所述金属屏蔽层上方；以及
第一钝化层，形成在所述开口的侧壁和底部上，其中，位于所述开口的底部上的所述第一钝化层部分地覆盖了所述金属焊盘所暴露出的表面，其中，所述第一钝化层延伸到所述氧化物缓冲层的一部分以及所述金属屏蔽层上方，
粘合层，位于所述金属焊盘和第二钝化层之间，其中，所述第二钝化层形成在所述粘合层和所述非低k介电层上方。
2.根据权利要求1所述的集成电路结构，进一步包括：介电焊盘，从所述半导体衬底的正面延伸到所述半导体衬底中，其中，所述开口进一步穿透所述介电焊盘。
3.根据权利要求1所述的集成电路结构，进一步包括：图像传感器，被设置在所述半导体衬底的正面上。
4.根据权利要求1所述的集成电路结构，进一步包括：凸块，位于所述开口中，并且电连接至所述金属焊盘。
5.根据权利要求4所述的集成电路结构，其中，所述凸块与所述金属焊盘物理接触。
6.根据权利要求1所述的集成电路结构，进一步包括：粘合层，位于所述金属焊盘和所述非低k介电层之间，其中，所述开口延伸到所述粘合层中。
7.一种集成电路结构，包括：
半导体衬底；
浅沟槽隔离STI焊盘，从所述半导体衬底的正面延伸到所述半导体衬底中；
图像传感器，被设置在所述半导体衬底的正面上；
多层介电层，覆盖所述图像传感器和所述半导体衬底的正面；
金属焊盘，覆盖所述多层介电层；
开口，从所述半导体衬底的背面延伸到所述半导体衬底的正面，穿过所述STI焊盘和所述多层介电层，并且暴露出所述金属焊盘的一部分；以及
第一钝化层，形成在所述开口的侧壁和底部上，其中，位于所述开口的底部上的所述第一钝化层部分地覆盖了所述金属焊盘所暴露出的部分，其中，所述第一钝化层在所述开口的侧壁处直接邻接所述多层介电层，
第三粘合层，位于所述金属焊盘和第二钝化层之间，其中，所述第二钝化层形成在所述第三粘合层和所述多层介电层上方。
8.根据权利要求7所述的集成电路结构，其中，所述多层介电层包括：至少一层低k介电层，位于所述半导体衬底的正面上方；以及第一非低k介电层，位于所述至少一层低k介电层上。
9.根据权利要求8所述的集成电路结构，进一步包括：第二非低k介电层，位于所述第一非低k介电层上方。
10.根据权利要求9所述的集成电路结构，进一步包括：
第一粘合层，位于所述金属焊盘和所述第一非低k介电层之间；以及
第二粘合层，位于所述金属焊盘和所述第二非低k介电层之间。
11.根据权利要求7所述的集成电路结构，进一步包括：凸块，位于所述开口中，并且与所述金属焊盘物理接触。
12.根据权利要求7所述的集成电路结构，其中，所述金属焊盘包含铝。
13.一种背照式图像传感器器件，包括：
半导体衬底，包括正面和背面；
金属屏蔽层，位于所述半导体衬底的背面上；
多层介电层，位于所述半导体衬底的正面上；
金属焊盘，位于所述多层介电层上；
开口，从所述半导体衬底的背面延伸，穿透所述半导体衬底和所述多层介电层，暴露出所述金属焊盘的一部分；
凸块，形成在所述开口中，以电连接至所述金属焊盘；以及
第一钝化层具有第一表面和第二表面，所述第二表面与所述第一表面相对，所述第一钝化层的第一表面直接邻接所述凸块和所述第一钝化层的第二表面直接邻接所述多层介电层中的每一层，所述第一钝化层进行延伸以覆盖所述金属屏蔽层的顶面，
粘合层，位于所述金属焊盘和第二钝化层之间，其中，所述第二钝化层形成在所述粘合层和所述多层介电层上方。
14.根据权利要求13所述的背照式图像传感器器件，进一步包括：图像传感器，形成在所述半导体衬底的正面上，并且被所述多层介电层覆盖。
15.根据权利要求13所述的背照式图像传感器器件，进一步包括：浅沟槽隔离件，形成在所述半导体衬底的正面上，其中，所述开口穿透所述浅沟槽隔离件。
16.根据权利要求13所述的背照式图像传感器器件，其中，所述金属焊盘包含铝。
CN201110353065.0A 2011-08-04 2011-11-09 Bsi图像传感器芯片中的焊盘结构 Active CN102915991B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/198,111 2011-08-04
US13/198,111 US9013022B2 (en) 2011-08-04 2011-08-04 Pad structure including glue layer and non-low-k dielectric layer in BSI image sensor chips

Publications (2)

Publication Number Publication Date
CN102915991A CN102915991A (zh) 2013-02-06
CN102915991B true CN102915991B (zh) 2015-08-26

Family

ID=47614303

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110353065.0A Active CN102915991B (zh) 2011-08-04 2011-11-09 Bsi图像传感器芯片中的焊盘结构

Country Status (5)

Country Link
US (4) US9013022B2 (zh)
JP (1) JP5543992B2 (zh)
KR (1) KR101430793B1 (zh)
CN (1) CN102915991B (zh)
TW (1) TWI487082B (zh)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8987855B2 (en) * 2011-08-04 2015-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. Pad structures formed in double openings in dielectric layers
US9013022B2 (en) 2011-08-04 2015-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. Pad structure including glue layer and non-low-k dielectric layer in BSI image sensor chips
US9006900B2 (en) 2013-03-11 2015-04-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with advanced pad structure resistant to plasma damage and method for forming the same
CN104103511B (zh) * 2013-04-03 2017-03-08 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法
JP6200188B2 (ja) * 2013-04-08 2017-09-20 キヤノン株式会社 固体撮像装置、その製造方法及びカメラ
KR20140141400A (ko) * 2013-05-29 2014-12-10 삼성전자주식회사 디스플레이 장치
US9337225B2 (en) * 2013-09-13 2016-05-10 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
CN104637961B (zh) * 2013-11-13 2018-09-11 联华电子股份有限公司 半导体结构及其制造方法
US9117879B2 (en) * 2013-12-30 2015-08-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
JP6200835B2 (ja) 2014-02-28 2017-09-20 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
EP3032583B1 (en) 2014-12-08 2020-03-04 ams AG Integrated optical sensor and method of producing an integrated optical sensor
US9748301B2 (en) * 2015-01-09 2017-08-29 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
KR102437163B1 (ko) 2015-08-07 2022-08-29 삼성전자주식회사 반도체 소자
US10038025B2 (en) 2015-12-29 2018-07-31 Taiwan Semiconductor Manufacturing Co., Ltd. Via support structure under pad areas for BSI bondability improvement
FR3059143B1 (fr) * 2016-11-24 2019-05-31 Stmicroelectronics (Crolles 2) Sas Puce de capteur d'image
US20190027531A1 (en) * 2017-07-19 2019-01-24 Omnivision Technologies, Inc. Image sensor module having protective structure
CN107204349A (zh) * 2017-07-19 2017-09-26 武汉新芯集成电路制造有限公司 一种铝垫放置方法以及铝垫结构
JP2019129215A (ja) * 2018-01-24 2019-08-01 キヤノン株式会社 撮像装置および表示装置
US10707089B2 (en) * 2018-03-27 2020-07-07 Texas Instruments Incorporated Dry etch process landing on metal oxide etch stop layer over metal layer and structure formed thereby
WO2019195385A1 (en) * 2018-04-03 2019-10-10 Corning Incorporated Precision structured glass article having emi shielding and methods for making the same
US10707358B2 (en) * 2018-07-04 2020-07-07 Globalfoundries Singapore Pte. Ltd. Selective shielding of ambient light at chip level
US11227836B2 (en) * 2018-10-23 2022-01-18 Taiwan Semiconductor Manufacturing Company, Ltd. Pad structure for enhanced bondability
KR102639539B1 (ko) 2018-11-05 2024-02-26 삼성전자주식회사 이미지 센서 및 이의 형성 방법
US10991667B2 (en) * 2019-08-06 2021-04-27 Taiwan Semiconductor Manufacturing Co., Ltd. Isolation structure for bond pad structure
US11211352B2 (en) * 2019-10-01 2021-12-28 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure to prevent metal redeposit and to prevent bond pad consumption and corrosion
US12027479B2 (en) 2019-11-08 2024-07-02 Nanya Technology Corporation Semiconductor device with edge-protecting spacers over bonding pad
US11502123B2 (en) * 2020-04-17 2022-11-15 Taiwan Semiconductor Manufacturing Company Limited Methods for forming image sensor devices
US20220367554A1 (en) * 2021-05-17 2022-11-17 Taiwan Semiconductor Manufacturing Co., Ltd. Bond pad structure with high via density

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101582393A (zh) * 2008-05-12 2009-11-18 索尼株式会社 固体摄像器件制造方法和电子装置制造方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100533166B1 (ko) * 2000-08-18 2005-12-02 매그나칩 반도체 유한회사 마이크로렌즈 보호용 저온산화막을 갖는 씨모스이미지센서및 그 제조방법
JP2004095611A (ja) * 2002-08-29 2004-03-25 Fujitsu Ltd 半導体装置およびその製造方法
US20050142715A1 (en) 2003-12-26 2005-06-30 Fujitsu Limited Semiconductor device with high dielectric constant insulator and its manufacture
JP4858898B2 (ja) 2003-12-26 2012-01-18 富士通セミコンダクター株式会社 半導体装置とその製造方法
US9038973B2 (en) * 2007-07-12 2015-05-26 Panduit Corp. Accessory bracket
US7659595B2 (en) 2007-07-16 2010-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded bonding pad for backside illuminated image sensor
US8212328B2 (en) * 2007-12-05 2012-07-03 Intellectual Ventures Ii Llc Backside illuminated image sensor
JP4609497B2 (ja) * 2008-01-21 2011-01-12 ソニー株式会社 固体撮像装置とその製造方法、及びカメラ
JP5357441B2 (ja) 2008-04-04 2013-12-04 キヤノン株式会社 固体撮像装置の製造方法
KR100882991B1 (ko) 2008-08-06 2009-02-12 주식회사 동부하이텍 후면 수광 이미지센서의 제조방법
JP4655137B2 (ja) 2008-10-30 2011-03-23 ソニー株式会社 半導体装置
JP2011003645A (ja) 2009-06-17 2011-01-06 Sharp Corp 半導体装置およびその製造方法
US9013022B2 (en) 2011-08-04 2015-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. Pad structure including glue layer and non-low-k dielectric layer in BSI image sensor chips

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101582393A (zh) * 2008-05-12 2009-11-18 索尼株式会社 固体摄像器件制造方法和电子装置制造方法

Also Published As

Publication number Publication date
US20150228690A1 (en) 2015-08-13
TWI487082B (zh) 2015-06-01
JP2013038391A (ja) 2013-02-21
US10535696B2 (en) 2020-01-14
KR101430793B1 (ko) 2014-08-18
CN102915991A (zh) 2013-02-06
KR20130016017A (ko) 2013-02-14
TW201308555A (zh) 2013-02-16
JP5543992B2 (ja) 2014-07-09
US20130032916A1 (en) 2013-02-07
US20170250215A1 (en) 2017-08-31
US9653508B2 (en) 2017-05-16
US9013022B2 (en) 2015-04-21
US20160260764A1 (en) 2016-09-08
US9362329B2 (en) 2016-06-07

Similar Documents

Publication Publication Date Title
CN102915991B (zh) Bsi图像传感器芯片中的焊盘结构
CN104779243B (zh) 3dic密封环结构及其形成方法
KR101595623B1 (ko) 후면 조사 이미지 센서 상의 본딩 패드
US8796805B2 (en) Multiple metal film stack in BSI chips
TWI714329B (zh) 半導體結構及其形成方法
US9184207B2 (en) Pad structures formed in double openings in dielectric layers
TWI753745B (zh) 影像感測器結構及其製造方法
US9450014B2 (en) Backside illumination image sensor chips and methods for forming the same
CN113725240A (zh) 半导体器件及其形成方法
KR101768292B1 (ko) 이미지 센서 소자, 이미지 센서 소자 제조 방법 및 반도체 소자 제조 방법
CN102916018B (zh) 在介电层中的双开口中形成的焊盘结构
JP2023004854A (ja) 半導体装置及びその製造方法
CN112103302A (zh) 封装结构及其封装方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant