TWI486964B - 高效能快閃記憶體資料傳送方法及裝置 - Google Patents

高效能快閃記憶體資料傳送方法及裝置 Download PDF

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Publication number
TWI486964B
TWI486964B TW096114457A TW96114457A TWI486964B TW I486964 B TWI486964 B TW I486964B TW 096114457 A TW096114457 A TW 096114457A TW 96114457 A TW96114457 A TW 96114457A TW I486964 B TWI486964 B TW I486964B
Authority
TW
Taiwan
Prior art keywords
data
controller
flash memory
input
mode
Prior art date
Application number
TW096114457A
Other languages
English (en)
Chinese (zh)
Other versions
TW200818206A (en
Inventor
Yishai Kagan
Rizwan Ahmed
Farookh Moogat
Jason Lin
Original Assignee
Sandisk Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/379,910 external-priority patent/US7345926B2/en
Priority claimed from US11/379,895 external-priority patent/US7366028B2/en
Priority claimed from US11/424,581 external-priority patent/US7366029B2/en
Priority claimed from US11/424,573 external-priority patent/US7525855B2/en
Priority claimed from US11/458,431 external-priority patent/US7499339B2/en
Priority claimed from US11/458,422 external-priority patent/US7499369B2/en
Application filed by Sandisk Technologies Inc filed Critical Sandisk Technologies Inc
Publication of TW200818206A publication Critical patent/TW200818206A/zh
Application granted granted Critical
Publication of TWI486964B publication Critical patent/TWI486964B/zh

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits

Landscapes

  • Read Only Memory (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
TW096114457A 2006-04-24 2007-04-24 高效能快閃記憶體資料傳送方法及裝置 TWI486964B (zh)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US11/379,910 US7345926B2 (en) 2006-04-24 2006-04-24 High-performance flash memory data transfer
US11/379,895 US7366028B2 (en) 2006-04-24 2006-04-24 Method of high-performance flash memory data transfer
US11/424,581 US7366029B2 (en) 2006-04-24 2006-06-16 High-performance flash memory data transfer
US11/424,573 US7525855B2 (en) 2006-04-24 2006-06-16 Method of high-performance flash memory data transfer
US11/458,431 US7499339B2 (en) 2006-07-19 2006-07-19 High-performance flash memory data transfer
US11/458,422 US7499369B2 (en) 2006-07-19 2006-07-19 Method of high-performance flash memory data transfer

Publications (2)

Publication Number Publication Date
TW200818206A TW200818206A (en) 2008-04-16
TWI486964B true TWI486964B (zh) 2015-06-01

Family

ID=38627002

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096114457A TWI486964B (zh) 2006-04-24 2007-04-24 高效能快閃記憶體資料傳送方法及裝置

Country Status (6)

Country Link
EP (1) EP2011122A2 (ko)
JP (1) JP5226669B2 (ko)
KR (1) KR101458381B1 (ko)
CN (1) CN101479804B (ko)
TW (1) TWI486964B (ko)
WO (1) WO2007127678A2 (ko)

Families Citing this family (14)

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JP5106219B2 (ja) 2008-03-19 2012-12-26 株式会社東芝 メモリデバイス、ホストデバイス、メモリシステム、メモリデバイスの制御方法、ホストデバイスの制御方法、およびメモリシステムの制御方法
KR101087195B1 (ko) * 2008-05-26 2011-11-29 주식회사 하이닉스반도체 불휘발성 메모리 장치
US8677056B2 (en) 2008-07-01 2014-03-18 Lsi Corporation Methods and apparatus for interfacing between a flash memory controller and a flash memory array
JP5266589B2 (ja) * 2009-05-14 2013-08-21 ルネサスエレクトロニクス株式会社 不揮発性半導体記憶装置
JP5449032B2 (ja) * 2009-05-28 2014-03-19 パナソニック株式会社 メモリシステム
JP2011058847A (ja) * 2009-09-07 2011-03-24 Renesas Electronics Corp 半導体集積回路装置
JP2013520759A (ja) * 2010-02-23 2013-06-06 ラムバス・インコーポレーテッド Ｄｒａｍの電力および性能を動的にスケーリングするための方法および回路
US8422315B2 (en) * 2010-07-06 2013-04-16 Winbond Electronics Corp. Memory chips and memory devices using the same
JP2012198965A (ja) * 2011-03-22 2012-10-18 Toshiba Corp 不揮発性半導体記憶装置
US9053066B2 (en) * 2012-03-30 2015-06-09 Sandisk Technologies Inc. NAND flash memory interface
KR102130171B1 (ko) * 2014-01-13 2020-07-03 에스케이하이닉스 주식회사 반도체장치 및 반도체시스템
US9385721B1 (en) 2015-01-14 2016-07-05 Sandisk Technologies Llc Bulk driven low swing driver
US9792994B1 (en) 2016-09-28 2017-10-17 Sandisk Technologies Llc Bulk modulation scheme to reduce I/O pin capacitance
JP6894459B2 (ja) * 2019-02-25 2021-06-30 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． 疑似スタティックランダムアクセスメモリとその動作方法

Citations (6)

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JP2001067870A (ja) * 1999-08-31 2001-03-16 Hitachi Ltd 半導体装置
US20010046163A1 (en) * 2000-05-19 2001-11-29 Fujitsu Limited Memory system and memory controller with reliable data latch operation
US6337832B1 (en) * 1998-06-10 2002-01-08 Mitsubishi Denki Kabushiki Kaisha Operable synchronous semiconductor memory device switching between single data rate mode and double data rate mode
TWI228259B (en) * 2000-05-22 2005-02-21 Samsung Electronics Co Ltd Method and circuit for inputting and outputting data, and system using semiconductor memory device including the same
TW200522076A (en) * 2003-12-30 2005-07-01 Hynix Semiconductor Inc Write circuit of double data rate synchronous dram
US6961269B2 (en) * 2003-06-24 2005-11-01 Micron Technology, Inc. Memory device having data paths with multiple speeds

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US5696917A (en) * 1994-06-03 1997-12-09 Intel Corporation Method and apparatus for performing burst read operations in an asynchronous nonvolatile memory
KR100252057B1 (ko) * 1997-12-30 2000-05-01 윤종용 단일 및 이중 데이터 율 겸용 반도체 메모리 장치
JP2002007200A (ja) * 2000-06-16 2002-01-11 Nec Corp メモリ制御装置及び動作切替方法並びにインターフェース装置、半導体集積チップ、記録媒体
US7370168B2 (en) * 2003-04-25 2008-05-06 Renesas Technology Corp. Memory card conforming to a multiple operation standards
DE102004026808B4 (de) * 2004-06-02 2007-06-06 Infineon Technologies Ag Abwärtskompatibler Speicherbaustein
KR100546418B1 (ko) * 2004-07-27 2006-01-26 삼성전자주식회사 데이터 출력시 ｄｄｒ 동작을 수행하는 비휘발성 메모리장치 및 데이터 출력 방법

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6337832B1 (en) * 1998-06-10 2002-01-08 Mitsubishi Denki Kabushiki Kaisha Operable synchronous semiconductor memory device switching between single data rate mode and double data rate mode
JP2001067870A (ja) * 1999-08-31 2001-03-16 Hitachi Ltd 半導体装置
US6335901B1 (en) * 1999-08-31 2002-01-01 Hitachi, Ltd. Semiconductor device
US6754133B2 (en) * 1999-08-31 2004-06-22 Hitachi, Ltd. Semiconductor device
US20010046163A1 (en) * 2000-05-19 2001-11-29 Fujitsu Limited Memory system and memory controller with reliable data latch operation
TWI228259B (en) * 2000-05-22 2005-02-21 Samsung Electronics Co Ltd Method and circuit for inputting and outputting data, and system using semiconductor memory device including the same
US6961269B2 (en) * 2003-06-24 2005-11-01 Micron Technology, Inc. Memory device having data paths with multiple speeds
TW200522076A (en) * 2003-12-30 2005-07-01 Hynix Semiconductor Inc Write circuit of double data rate synchronous dram

Also Published As

Publication number Publication date
JP2009534785A (ja) 2009-09-24
CN101479804B (zh) 2013-05-01
EP2011122A2 (en) 2009-01-07
WO2007127678A3 (en) 2008-02-07
CN101479804A (zh) 2009-07-08
TW200818206A (en) 2008-04-16
WO2007127678A2 (en) 2007-11-08
KR20090026267A (ko) 2009-03-12
JP5226669B2 (ja) 2013-07-03
KR101458381B1 (ko) 2014-11-07

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