TWI485787B - 具有偏移堆疊與防溢料結構的積體電路封裝件系統 - Google Patents

具有偏移堆疊與防溢料結構的積體電路封裝件系統 Download PDF

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TWI485787B
TWI485787B TW100140081A TW100140081A TWI485787B TW I485787 B TWI485787 B TW I485787B TW 100140081 A TW100140081 A TW 100140081A TW 100140081 A TW100140081 A TW 100140081A TW I485787 B TWI485787 B TW I485787B
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integrated circuit
carrier
device structure
package
flash
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TW100140081A
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English (en)
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TW201214587A (en
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Seng Guan Chow
Heap Hoe Kuan
Linda Pei Ee Chua
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Stats Chippac Ltd
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Description

具有偏移堆疊與防溢料結構的積體電路封裝件系統 [相關申請案之交互參照]
此為2007年12月12日申請共同審查中之美國專利申請案第11/954,613號的分割案。
本發明大體係有關於積體電路封裝件系統，尤其是關於帶有包覆體(encapsulation)的積體電路封裝件系統。
為求介接(interface)積體電路與其他電路，通常會將積體電路安裝於導線架上或基板上。每個積體電路具有連結墊(bonding pad)，該連結墊係使用極纖細的金線或鋁線或者如銲球之導電球而個別地連接至基板的接觸點(contact)或終端墊(terminal pad)。屆時藉由個別地將組件包覆於模造塑膠或陶瓷體(ceramic body)中而予以封裝，以產生積體電路封裝件。
積體電路封裝技術已歷經在單一電路板或基板上所安裝之積體電路之數量上的增加。新穎的封裝設計係更加縮小的形狀因素(form factor)，例如物理尺寸及經封裝的積體電路的形狀，且提供整體積體電路密度之顯著增加。
然而，積體電路密度持續受限於可用於安裝個別的積體電路於基板上之「基板面(real estate)」。即使如個人電腦(personal computer,PC)、計算伺服器(compute server)及儲存伺服器(storage server)等的較大形狀因素系統，係需要更多積體電路於相同或較小的「基板面」中。特別尤其是如行動電話、數位相機、音樂播放器、個人數位助理(personal digital assistant,PDA)及定位裝置(location-based device)之可攜式(portable)個人電子商品，已進一步驅使增加積體電路密度之需求。
所增加的積體電路密度已導致能夠封裝多於一個積體電路之多晶片封裝件之發展。每個封裝件係提供用於個別積體電路及能夠使積體電路電性連接至週邊電路之一層或多層互連線之機械支援。
目前多晶片封裝件亦常被稱為多晶片模組，典型地由有一組分開的積體電路零件直接接置於其上之印刷電路板(printed circuit board,PCB)基板所組成。已發現此種多晶片封裝件來增加積體電路密度和最小化、改善訊號傳遞速度、減縮整體積體電路尺寸及重量、改善效能以及降低成本-所有電腦工業之主要目的。
因多晶片封裝件通常必須於積體電路及積體電路連接能被測試之前便預先組裝，故多晶片封裝件不論是垂直或水平配置，都可能呈現問題。因此，當安裝並連接積體電路於多晶片模組中時，無法個別地測試個別的積體電路及連接，且不可能於組裝至較大電路之前確認「已知良好晶粒(known-good-die,KGD)」。因此，習知多晶片封裝件會導致組裝製程良率的問題。此無法確認KGD之製造流程係因此較不可靠且更易導致組裝缺陷。
再者，於典型的多晶片封裝件中，垂直堆疊之積體電路所呈現的問題可能會多於水平配置之積體電路封裝件之問題，且進一步複雜其製造流程。這會變得較難以測試而因此難以判定個別積體電路之實際故障模式。再者，基板及積體電路經常於組裝或測試期間受損，而複雜其製造流程且增加成本。
對於垂直及水平之多晶片封裝件二者而言，於多重積體電路、經堆疊封裝之積體電路或其結合之積體電路之間，多晶片封裝件之組裝必須具有可靠的電性及機械性接置。舉例而言，用於形成經封裝的積體電路之包覆製程可能造成如模造溢料(flash)及鑄漏(bleed)之污染，進而妨礙可靠的接置。另一範例中，對於在其包覆體中具有凹部之積體電路封裝件而言，係使用順形的(contoured)模具(mold chase)以形成該凹部，該凹部係增加模造溢料風險、由於與模具之順形部分接觸而對封裝結構造成傷害、以及用以於包覆體中之所需凹部而設計特定模具之製造成本。
因此，對積體電路封裝件系統而言，仍需提供低製造成本、增進的良率、改善的可靠度及較佳的靈活度(flexibility)，以提供更多功能性及於印刷電路板上較少的佔板面積(footprint)。有鑑於對節省成本及增進效率的持續增加之需求，發現這些問題的答案變得愈來愈重要。
尋求這些問題的解答已持續了好一段時間，但是習知發展並未教示或建議任何解答，因此，該項技術中熟習技術者長期以來皆引頸期盼這些問題的解答。
本發明係提供一種積體電路封裝方法，係包含：以偏移位置安裝裝置結構於承載件上面，該裝置結構具有連結墊及接觸墊；於該連結墊與該承載件之間連接電性互連；於該裝置結構上面形成防溢料結構，該防溢料結構係外露該接觸墊；以及於該承載件上面相鄰於該防溢料結構形成封裝件包覆體。
本發明之特定實施例具有另外附加或取代該些從上述所提及之其他實施態樣。熟習該項技術者在參照附加的圖式時，可從閱讀詳盡的下文中，明瞭該等態樣。
接下來的具體實施例係經過充分詳細描述，以使熟習該項技術者得以製作及使用本發明。應理解的是，其它實施例會根據本揭露內容而變得明顯，而系統、製程或機械變化可加以達成，而不背離本發明之範疇。
在下列描述中，係給定許多特定細節以提供本發明完整的理解。然而，將清楚的是，毋需該些特定細節也能實施本發明。為求避免混淆本發明，一些廣為周知的電路、系統組構及製程步驟並未詳盡地揭露。同樣地，顯示該系統之具體實施例的附圖係部分圖解且不按比例的，尤其之中的一些尺寸則為了表達清楚而於圖式中顯得特別誇張。一般而言，本發明能於任何方位上進行操作。
此外，為求清楚且易於將其說明、描述及理解，所揭露及描述之具有某些共同特徵之多個具體實施例中，彼此類似或相同的特徵通常以相同的元件符號描述。為了描述上的方便，該些具體實施例係已經以第一具體實施例、第二具體實施例等等來予以標號，而並非有意對本發明具有任何其他含意或提供限制。
為了附註之目的，於此使用之術語「水平(horizontal)」係定義為平行於積體電路之平面或表面，而不管其方位(orientation)。術語「垂直(vertical)」指的是垂直於方才定義之水平之方向。例如「上方(above)」、「下方(below)」、「底部(bottom)」、「頂部(top)」、「側(side)」(如「側壁(sidewall)」)、「較高(higher)」、「較低(lower)」、「較上方(upper)」、「上面(over)」、「下面(under)」之術語則對應於該水平平面而定義。術語「上(on)」則意指元件間的直接接觸。使用於此之術語「處理(processing)」則包含材料的沉積、圖案化、曝光、顯影、蝕刻、清洗、模造及/或材料的移除，或如形成所述結構之所需者。於此使用之術語「系統」則意指依據該詞所使用之內容中本發明之方法及設備。
現在參照第1圖，其係顯示本發明之第一具體實施例中，積體電路封裝件系統100之上視圖。該上視圖係描繪無覆蓋(cover)的積體電路封裝件系統100。該上視圖係描繪具有接觸墊104及連結墊106之裝置結構102(如基板)於承載件108(如基板)上面。該裝置結構102之側邊(side)110係顯示成平行於該承載件108之邊緣112。該裝置結構102係顯示成位於該承載件108上面之偏移位置，而非該承載件108上面之中央位置。
接觸墊104係顯示於裝置結構102之週邊區域上面之防溢料結構114之環內，該防溢料材料114係例如非導電環氧基樹脂、密封劑、聚合物材料、固線樹脂材料(wire lock resin material)或可穿透的膜膠(penetrable film adhesive)。如導線(bond wire)或帶狀導線(ribbon bond wire)之電性互連116能於連結墊106與承載件108之間連接。該防溢料結構114係覆蓋連接於該裝置結構102之該電性互連116之末端。
如積體電路晶粒(dice)或經封裝的積體電路之第一積體電路裝置118以及如離散的(discrete)電阻器或電容器之被動裝置120，係安裝於該承載件108上面。為求說明之目的，該第一積體電路裝置118係顯示成相同類型之裝置，然而應理解的是，該第一積體電路裝置118能彼此相異，例如相異的類型、功能、尺寸或技術。亦為求說明之目的，該被動裝置120係顯示成相同類型之零件，然而應理解的是，該被動裝置120能彼此相異。舉例而言，被動裝置120能包含相異的電阻器、電容器、電感器(inductor)或上述之結合。
現在參照第2圖，其係顯示第1圖沿線2--2之積體電路封裝件系統100之剖面圖。該剖面圖係描繪如積體電路晶粒之第二積體電路222安裝於該承載件108上面。如膜膠之間隔件224能提供空隙(clearance)予電性互連116以於該第二積體電路裝置222與該承載件108之間進行連接。
裝置結構102係安裝於該第二積體電路裝置222及該承載件108上面。該裝置結構102係顯示成位於該承載件108上面之偏移位置，而非該承載件108上面之中央位置。於該裝置結構102之週邊區域上面之防溢料結構114、該裝置結構102、該間隔件224及該第二積體電路裝置222能決定於該承載件108上面之封裝件包覆體228之包覆體高度226。
封裝件包覆體228係於該承載件108上面且覆蓋第一積體電路裝置118、被動裝置120、第二積體電路裝置222、電性互連116及間隔件224。該封裝件包覆體228能相鄰於該防溢料結構114，而形成外露該裝置結構102之接觸墊104之凹部230。
防溢料結構114能提供多種功能。舉例而言，該防溢料結構114係減輕或消除與裝置結構102連接之電性互連116之導線短路(wire sweep)，從而改善良率並降低成本。如另一範例，該防溢料結構114能減輕或消除接觸墊104上面之模造溢料(mold flashing)，從而改善可靠度、增進良率以及降低成本。
如積體電路或被動元件之安裝裝置(mounting device)232能視需要地(optionally)安裝於積體電路封裝件系統100上面，而形成積體電路層疊封裝系統(package-on-package system)。該安裝裝置232係以虛線描繪。該安裝裝置232能安裝於裝置結構102上面且於該凹部230內。
應理解的是，顯示於具體實施例中之第一積體電路裝置118、第二積體電路裝置222以及安裝裝置232係用於說明之目的。該第一積體電路裝置118、該第二積體電路裝置222以及該安裝裝置232能為晶圓級晶片尺寸封裝(wafer level chip scale package,WLCSP)、重新佈線(redistributed line,RDL)晶粒、陣列封裝件、無導腳封裝件(leadless package)、導腳封裝件(leaded package)、系統級封裝(system-in-package,SiP)、堆疊晶粒封裝件、封裝內封裝(package-in-package,PiP)、內嵌晶粒基板(embedded die substrate)或增進散熱封裝、EMI屏蔽封裝。
現在參照第3圖，係顯示本發明之第二具體實施例中以第1圖之上視圖為例之積體電路封裝件系統300之剖面圖。該剖面圖係描繪被動裝置320及第一積體電路裝置318(如積體電路晶粒)安裝於承載件308上面。第二積體電路裝置322(如經封裝的積體電路)係以黏膠334安裝於承載件308上面，且能相鄰於其中一個該第一積體電路裝置318。
該第二積體電路裝置322包含裝置結構302作為其基板。該第二積體電路裝置322係顯示成位於該承載件308上面之偏移位置而非該承載件308上面之中央位置。電性互連316能連接該裝置結構302與該承載件308。如一範例，該第二積體電路裝置322係顯示成倒置組構(inverted configuration)而使裝置結構302背對該承載件308。
防溢料結構314係位於該裝置結構302之週邊區域上面及於該裝置結構302上面之電性互連316之一部份的上面。該防溢料結構314及該第二積體電路裝置322能決定於該承載件308上面之封裝件包覆體328之包覆體高度326。
封裝件包覆體328係於該承載件308上面且覆蓋第一積體電路裝置318、被動裝置320、第二積體電路裝置322及該電性互連316。該封裝件包覆體328能相鄰於該防溢料結構314，而形成外露該裝置結構302之接觸墊304之凹部330。
如積體電路或被動元件之安裝裝置332能視需要地安裝於積體電路封裝件系統300上面，而形成積體電路層疊封裝系統。該安裝裝置332係以虛線描繪。該安裝裝置332能安裝於裝置結構302上面且於該凹部330內。
現在參照第4圖，其係顯示本發明之第三具體實施例中，積體電路封裝件系統400之上視圖。該上視圖係描繪裝置結構402之接觸墊404外露於由防溢料結構414所形成之凹部430中。封裝件包覆體428係相鄰於該防溢料結構414。
現在參照第5圖，係顯示第4圖沿線5--5之積體電路封裝件系統400之剖面圖。該剖面圖係描繪被動裝置520及第一積體電路裝置518(如積體電路晶粒)安裝於承載件508上面。第二積體電路裝置522(如經封裝的積體電路)係以黏膠534安裝於第三積體電路裝置536(如覆晶晶片(flip chip))上面，其中，第三積體電路裝置536係安裝於該承載件508上面。該第三積體電路裝置536能相鄰於其中一個第一積體電路裝置518。該第二積體電路裝置522能懸空(overhang)於該其中一個第一積體電路裝置518。
該第二積體電路裝置522係包含裝置結構402作為其基板。該第二積體電路裝置522係顯示成位於該承載件508上面之偏移位置，而非該承載件508上面之中央位置。電性互連516能連接該裝置結構402與該承載件508。如一範例，該第二積體電路裝置522係顯示成倒置組構而使裝置結構402背對該承載件508。
防溢料結構414係位於該裝置結構402之週邊區域上面及於該裝置結構402上面之電性互連516之一部份的上面。該防溢料結構414、該第二積體電路裝置522及該第三積體電路裝置536能決定於該承載件508上面之封裝件包覆體428之包覆體高度526。
封裝件包覆體428係於該承載件508上面且覆蓋第一積體電路裝置518、被動裝置520、第二積體電路裝置522、該第三積體電路裝置536及該電性互連516。該封裝件包覆體428能相鄰於該防溢料結構414，而形成外露該裝置結構402之接觸墊404之凹部430。
如積體電路或被動元件之安裝裝置532能視需要地安裝於積體電路封裝件系統400上面，而形成積體電路層疊封裝系統。該安裝裝置532係以虛線描繪。該安裝裝置532能安裝於裝置結構402上面且於該凹部430內。
現在參照第6圖，其係顯示本發明之第四具體實施例中，積體電路封裝件系統600之上視圖。該上視圖係描繪無覆蓋的積體電路封裝件系統600。該上視圖係描繪於承載件608(如基板)上面之裝置結構602(如基板)，而各該裝置結構602係具有接觸墊604及連結墊606。各該裝置結構602之側邊610係顯示成平行於該承載件608之邊緣612。各該裝置結構602係顯示成位於該承載件608上面之偏移位置，而非該承載件608上面之中央位置。
為求說明之目的，該裝置結構602係顯示成彼此相同類型，然而應理解的是，該裝置結構602能於尺寸、形狀、方位、接觸墊604之組構以及連結墊606之組構等方面上相異。
對於各個裝置結構602而言，接觸墊604係顯示於裝置結構602之週邊區域上面之防溢料結構614之環內。如導線或帶狀導線之電性互連616能於連結墊606與承載件608之間連接。該防溢料結構614係覆蓋連接於該裝置結構602之該電性互連616之末端。
如積體電路晶粒或經封裝的積體電路之第一積體電路裝置618以及如離散的電阻器或電容器之被動裝置620，係安裝於該承載件608上面。為求說明之目的，該被動裝置620係顯示成相同類型之元件，然而應理解的是，該被動裝置620能為彼此相異的元件。舉例而言，被動裝置620能包含相異的電阻器、電容器、電感器或上述之結合。
現在參照第7圖，其係顯示第6圖沿線7--7之積體電路封裝件系統600之剖面圖。該剖面圖係描繪如積體電路晶粒之第二積體電路722安裝於該承載件608上面。如膜膠之間隔件724能提供空隙予電性互連616以於該第二積體電路裝置722與該承載件608之間進行連接。為求說明之目的，該第二積體電路裝置722係顯示成相同類型之裝置，然而應理解的是，該第二積體電路裝置722能彼此相異，例如相異的類型、功能、尺寸或技術。
裝置結構602係安裝於該第二積體電路裝置722及該承載件608上面。該裝置結構602係顯示成位於該承載件608上面之偏移位置，而非該承載件608上面之中央位置。於該裝置結構602之週邊區域上面之防溢料結構614、該裝置結構602、該間隔件724及該第二積體電路裝置722能決定於該承載件608上面之封裝件包覆體728之包覆體高度726。
封裝件包覆體728係於該承載件608上面且覆蓋第6圖之第一積體電路裝置618、被動裝置620、第二積體電路裝置722、電性互連616及間隔件724。該封裝件包覆體728能相鄰於該防溢料結構614，而形成從各該裝置結構602外露接觸墊604之凹部730。
防溢料結構614能提供多種功能。舉例而言，該防溢料結構614係減輕或消除與裝置結構602連接之電性互連616之導線短路，從而改善良率並降低成本。如另一範例，該防溢料結構614能減輕或消除接觸墊604上面之模造溢料，從而改善可靠度、增進良率以及降低成本。
如積體電路或被動元件之安裝裝置732能視需要地安裝於積體電路封裝件系統600上面，而形成積體電路層疊封裝系統。該安裝裝置732係以虛線描繪。該安裝裝置732能安裝於裝置結構602上面且於該凹部730內。為求說明之目的，該安裝裝置732係顯示成相同類型之裝置，然而應理解的是，該安裝裝置732能彼此相異，例如相異的類型、功能、尺寸或技術。
現在參照第8圖，其係顯示本發明之第五具體實施例中，積體電路封裝件系統800之上視圖。該上視圖係描繪無覆蓋的積體電路封裝件系統800。該上視圖係描繪具有接觸墊804及連結墊806之裝置結構802(如基板)於承載件808(如基板)上面。該裝置結構802之側邊810係顯示成非平行於該承載件808之邊緣812。該裝置結構802係顯示成位於該承載件808上面之偏移位置，而非該承載件808上面之中央位置。
接觸墊804係顯示於裝置結構802之週邊區域上面之防溢料結構814之環內。如導線或帶狀導線之電性互連816能於連結墊806與承載件808之間連接。該防溢料結構814係覆蓋連接於該裝置結構802之該電性互連816之末端。
如積體電路晶粒或經封裝的積體電路之第一積體電路裝置818以及如離散的電阻器或電容器之被動裝置820，係安裝於該承載件808上面。為求說明之目的，該第一積體電路裝置818中的某些裝置係顯示成與其餘的裝置不同而其他的裝置為相同的，然而應理解的是，該第一積體電路裝置818的所有裝置能彼此相異或彼此相同。亦為求說明之目的，該被動裝置820係顯示成相同類型之元件，然而應理解的是，該被動裝置820能為彼此相異的元件。舉例而言，被動裝置820能包含相異的電阻器、電容器、電感器或上述之結合。
現在參照第9圖，其係顯示第8圖沿線9--9之積體電路封裝件系統800之剖面圖。該剖面圖係描繪如積體電路晶粒之第二積體電路922安裝於該承載件808上面。如膜膠之間隔件924能提供空隙予電性互連816以於該第二積體電路裝置922與該承載件808之間進行連接。
裝置結構802係安裝於該第二積體電路裝置922及該承載件808上面。該裝置結構802係顯示成位於該承載件808上面之偏移位置，而非該承載件808上面之中央位置。於該裝置結構802之週邊區域上面之防溢料結構814、該裝置結構802、該間隔件924及該第二積體電路裝置922能決定於該承載件808上面之封裝件包覆體928之包覆體高度926。
封裝件包覆體928係於該承載件808上面且覆蓋第一積體電路裝置818、被動裝置820、第二積體電路裝置922、電性互連816及間隔件924。該封裝件包覆體928能相鄰於該防溢料結構814，而形成外露該裝置結構802之接觸墊804之凹部930。
防溢料結構814能提供多種功能。舉例而言，該防溢料結構814係減輕或消除與裝置結構802連接之電性互連816之導線短路，從而改善良率並降低成本。如另一範例，該防溢料結構814能減輕或消除接觸墊804上面之模造溢料，從而改善可靠度、增進良率以及降低成本。
如積體電路或被動元件之安裝裝置932能視需要地安裝於積體電路封裝件系統800上面，而形成積體電路層疊封裝系統。該安裝裝置932係以虛線描繪。該安裝裝置932能安裝於裝置結構802上面且於該凹部930內。
現在參照第10圖，其係顯示本發明之第六具體實施例中，積體電路封裝件系統1000之上視圖。該上視圖係描繪裝置結構1002之接觸墊1004外露於由防溢料結構1014所形成之凹部1030中。封裝件包覆體1028係相鄰於該防溢料結構1014。
現在參照第11圖，其係顯示第10圖沿線11--11之積體電路封裝件系統1000之剖面圖。該剖面圖係描繪被動裝置1120及如積體電路晶粒之第一積體電路裝置1118安裝於承載件1108上面。如積體電路晶粒之第二積體電路裝置1122係以黏膠1134安裝於承載件1108上面，且能相鄰於該第一積體電路裝置1118。
如包線膜膠(wire-in-film adhesive)之間隔件1124能提供空隙予電性互連1116以於該第二積體電路裝置1122與該承載件1108之間進行連接。連接至該第二積體電路裝置1122之該電性互連1116之末端亦於該間隔件1124中。
裝置結構1002係安裝於該第二積體電路裝置1122及該承載件1108上面。電性互連1116係連接該裝置結構1002之連結墊1106與該承載件1108。該連結墊1106係於該裝置結構1002之週邊區域。該裝置結構1002係顯示成位於該承載件1108上面之偏移位置，而非該承載件1108上面之中央位置。防溢料結構1014能於該裝置結構1002之週邊區域上面且於該連結墊1106與該接觸墊1004之間。該防溢料結構1014並未覆蓋連接至該連結墊1106之電性互連1116。該防溢料結構1014、該裝置結構1002、該間隔件1124及該第二積體電路裝置1122能決定於該承載件1108上面之封裝件包覆體1028之包覆體高度1126。
封裝件包覆體1028係於該承載件1108上面且覆蓋第一積體電路裝置1118、被動裝置1120、第二積體電路裝置1122、電性互連1116及間隔件1124。該封裝件包覆體1028能相鄰於該防溢料結構1014，而形成外露該裝置結構1002之接觸墊1004之凹部1030。該防溢料結構1014能提供多種功能。舉例而言，該防溢料結構1014能減輕或消除接觸墊1004上面之模造溢料，從而改善可靠度、增進良率以及降低成本。
如積體電路或被動元件之安裝裝置1132能視需要地安裝於積體電路封裝件系統1000上面，而形成積體電路層疊封裝系統。該安裝裝置1132係以虛線描繪。該安裝裝置1132能安裝於裝置結構1002上面且於該凹部1030內。
現在參照第12圖，係顯示本發明之第七具體實施例中以第10圖之上視圖為例之積體電路封裝件系統1200之剖面圖。該剖面圖係描繪被動裝置1220及如積體電路晶粒之第一積體電路裝置1218安裝於承載件1208上面。如經封裝的積體電路之第二積體電路裝置1222係以間隔件1224安裝於如積體電路晶粒之第三積體電路裝置1236上面，其中，該第三積體電路裝置1236係安裝於該承載件1208上面。該第三積體電路裝置1236能相鄰於該第一積體電路裝置1218。
該第二積體電路裝置1222係包含裝置結構1202作為其基板。該第二積體電路裝置1222係顯示成位於該承載件1208上面之偏移位置，而非該承載件1208上面之中央位置。電性互連1216能連接該裝置結構1202之連結墊1206與該承載件1208。如一範例，該第二積體電路裝置1222係顯示成倒置組構而使裝置結構1202背對該承載件1208。
如包線膜膠之間隔件1224能提供空隙予電性互連1216以於該第二積體電路裝置1222與該第三積體電路裝置1236之間進行連接。連接至該第三積體電路裝置1236之該電性互連1216之末端亦於該間隔件1224中。
該連結墊1206係於該裝置結構1202之週邊區域。防溢料結構1214能於該裝置結構1202之週邊區域上面且於該連結墊1206與該接觸墊1204之間。該防溢料結構1214並未覆蓋連接至該連結墊1206之電性互連1216。該防溢料結構1214、該裝置結構1202、該間隔件1224及該第二積體電路裝置1222能決定於該承載件1208上面之封裝件包覆體1228之包覆體高度1226。
封裝件包覆體1228係於該承載件1208上面且覆蓋該第一積體電路裝置1218、該被動裝置1220、該第二積體電路裝置1222、該電性互連1216、該第三積體電路裝置1236及該間隔件1224。該封裝件包覆體1228能相鄰於該防溢料結構1214，而形成外露該裝置結構1202之接觸墊1204之凹部1230。該防溢料結構1214能提供多種功能。舉例而言，該防溢料結構1214能減輕或消除接觸墊1204上面之模造溢料，從而改善可靠度、增進良率以及降低成本。
如積體電路或被動元件之安裝裝置1232能視需要地安裝於積體電路封裝件系統1200上面，而形成積體電路層疊封裝系統。該安裝裝置1232係以虛線描繪。該安裝裝置1232能安裝於裝置結構1202上面且於該凹部1230內。
現在參照第13圖，其係顯示本發明之第八具體實施例中，積體電路封裝件系統1300之上視圖。該上視圖係描繪無覆蓋的積體電路封裝件系統1300。該上視圖係描繪被動裝置1320及如經導線連結之積體電路晶粒之第一積體電路裝置1318安裝於承載件1308上面。為求說明之目的，該第一積體電路裝置1318係顯示成彼此不同尺寸，然而應理解的是，該第一積體電路裝置1318能為相同類型之裝置。
該上視圖亦描繪具有接觸墊1304及連結墊1306之裝置結構1302(如積體電路晶粒)於承載件1308(如基板)上面。該裝置結構1302之側邊1310係顯示成平行於該承載件1308之邊緣1312。該裝置結構1302係顯示成位於該承載件1308上面之偏移位置，而非該承載件1308上面之中央位置。
接觸墊1304係顯示於裝置結構1302之週邊區域上面之防溢料結構1314之環內。如導線或帶狀導線之電性互連1316能於連結墊1306與承載件1308之間連接。該防溢料結構1314係覆蓋連接於該裝置結構1302之該電性互連116之末端，且從該裝置結構1302溢出至該承載件1308。
現在參照第14圖，其係顯示第13圖沿線14--14之積體電路封裝件系統1300之剖面圖。該剖面圖係描繪安裝於該承載件1308上面之該裝置結構1302。該電性互連1316係連接於該裝置結構1302與該承載件1308之間。該裝置結構1302係顯示成位於該承載件1308上面之偏移位置，而非該承載件1308上面之中央位置。該防溢料結構1314係於該裝置結構1302之週邊區域上面且溢出至相鄰於該裝置結構1302之該承載件1308的一部分。該防溢料結構1314、該裝置結構1302及該電性互連1316能決定於該承載件1308上面之封裝件包覆體1428之包覆體高度1426。
封裝件包覆體1428係於該承載件1308上面且覆蓋第一積體電路裝置1318、被動裝置1320、裝置結構1302及電性互連1316。該封裝件包覆體1428能相鄰於該防溢料結構1314，而形成外露該裝置結構1302之接觸墊1304之凹部1430。
防溢料結構1314能提供多種功能。舉例而言，該防溢料結構1314係減輕或消除與裝置結構1302連接之電性互連1316之導線短路，從而改善良率並降低成本。如另一範例，該防溢料結構1314能減輕或消除接觸墊1304上面之模造溢料，從而改善可靠度、增進良率以及降低成本。
如積體電路或被動元件之安裝裝置1432能視需要地安裝於積體電路封裝件系統1300上面，而形成積體電路層疊封裝系統。該安裝裝置1432係以虛線描繪。該安裝裝置1432能安裝於裝置結構1302上面且於該凹部1430內。
現在參照第15圖，其係顯示第2圖之積體電路封裝件系統100於形成包覆體1502之步驟中之剖面圖。平面模具(planar mold chase) 1504能壓迫於該防溢料結構114上面。該平面模具1504亦能壓迫於模造停止件(mold stop) 1506上面，例如非導電環氧基樹脂、密封劑、聚合物材料、固線樹脂材料或可穿透的膜膠所製成之停止件。該防溢料結構114、該模造停止件1506或上述之結合能緩衝來自平面模具1504之力量而防止對於裝置結構102之傷害。該防溢料結構114及該模造停止件1506係包含彈回特性(resilient property)而補償因積體電路封裝件系統100之組裝製程中之傾斜之共面誤差(coplanarity error)。
包覆體1502係形成於承載片(carrier strip)1508上面，覆蓋該第一積體電路裝置118、該被動裝置120、該間隔件224及該第二積體電路裝置222。該防溢料結構114係減輕或消除裝置結構102之接觸墊104上面之模造溢料。該包覆體結構(encapsulated structure)能被切割(singulated)形成該積體電路封裝件系統100。
如另一範例，該平面模具1504能為視需要的。該模造停止件1506能作用為如欄壩填充(dam-and-fill)方法之模造製程中之欄壩(dam)，此處液態包覆體製程能鋪設於該承載片1508上面而覆蓋該第一積體電路裝置118、該被動裝置120、該間隔件224及該第二積體電路裝置222。該防溢料結構114亦能作用為模造製程中之欄壩而外露該裝置結構102之接觸墊104。
在此已發現本發明係藉由裝置結構與防溢料結構之偏移位置而增進良率且降低成本。該偏移位置及角度能有各種變化以散佈模造化合物流(molding compound flow)，而使安裝於承載件上之被動裝置或其他積體電路將不會如因導線短路而不慎短路，不會抬起裝置而造成連接破損或於包覆體中產生裂縫。流壓(flow pressure)之分布亦能容許高流量、高壓的模造製程而得以增進生產率(throughput)、增加生產力(productivity)且增加收益(profitability)。
現在參照第16圖，其係顯示本發明之具體實施例中，用於製造積體電路封裝件系統之積體電路封裝方法1600之流程圖。該方法1600係包含：於方塊1602中，將裝置結構安裝於承載件上面之偏移位置，該裝置結構係具有連結墊及接觸墊；於方塊1604中，於該連結墊與該承載件之間連接電性互連；於方塊1606中，於該裝置結構上面形成防溢料結構，該防溢料結構係外露該接觸墊；以及於方塊1608中，於該承載件上面相鄰於該防溢料結構形成封裝件包覆體。
本發明之又一重要的實施態樣在於本發明有益於支持且維護降低成本、簡化系統及增加效能之歷史趨勢。
本發明之該些以及其他有益的實施態樣因此而將技術水平提升到至少下一個等級。
因此，已發現到本發明之積體電路封裝件系統提供了重要、迄今未知且未曾達到的解決方案、性能及功能態樣，以用於電路系統之增進良率、增加可靠度及降低成本。所得到的製程及組構係直接的、符合成本效益的、非複雜的、高度多用途的、精確的、靈敏的且有效的，還能夠採取已知元件而實施，以用於迅速、有效率且經濟的製造、應用及使用。
本發明雖然已揭露結合特定最佳模式來描述，然而應理解的是對於熟習該項技藝者而言，根據先前描述的內容，許多替代方案、修改及變更將變得清楚。因此，本發明係意於囊括所有落入所包含之申請專利範圍之範疇內之此等替代方案、修改及變更。至今於此所提及或顯示於附圖之所有標的皆為例示說明且無限制之意味。
100、300、400、600、800．．．積體電路封裝件系統
102、302、402、602、802．．．裝置結構
104、304、404、604、804．．．接觸墊
106、606、806．．．連結墊
108、308、508、608、808．．．承載件
110、610、810、1310．．．側邊
112、612、812、1312．．．邊緣
114、314、414、614、814．．．防溢料結構
116、316、516、616、816．．．電性互連
118、318、518、618、818．．．第一積體電路裝置
120、320、520、620、820．．．被動裝置
222、322、522、722、922．．．第二積體電路裝置
224、724、924、1124、1224．．．間隔件
226、326、526、726、926．．．包覆體高度
228、328、428、728、928．．．封裝件包覆體
230、330、430、730、930．．．凹部
232、332、532、832、932．．．安裝裝置
334、534、1134．．．黏膠
536、1236．．．第三積體電路裝置
1000、1200、1300．．．積體電路封裝件系統
1002、1202、1302．．．裝置結構
1004、1204、1304．．．接觸墊
1014、1214、1314．．．防溢料結構
1028、1228、1428．．．封裝件包覆體
1030、1230、1430．．．凹部
1106、1206、1306．．．連結墊
1108、1208、1308．．．承載件
1116、1216、1316．．．電性互連
1118、1218、1318．．．第一積體電路裝置
1120、1220、1320．．．被動裝置
1122、1222．．．第二積體電路裝置
1126、1226、1426．．．包覆體高度
1132、1232、1432．．．安裝裝置
1502．．．包覆體
1504．．．平面模具
1506．．．模造停止件
1508．．．承載片
2--2、5--5、7--7、9--9、11--11、14--14．．．線
1600．．．方法
1602、1604、1606、1608．．．方塊
第1圖係本發明之第一具體實施例中，積體電路封裝件系統之上視圖；
第2圖係第1圖沿線2--2之積體電路封裝件系統之剖面圖；
第3圖係本發明之第二具體實施例中以第1圖之上視圖為例之積體電路封裝件系統之剖面圖；
第4圖係本發明之第三具體實施例中，積體電路封裝件系統之上視圖；
第5圖係第4圖沿線5--5之積體電路封裝件系統之剖面圖；
第6圖係本發明之第四具體實施例中，積體電路封裝件系統之上視圖；
第7圖係第6圖沿線7--7之積體電路封裝件系統之剖面圖；
第8圖係本發明之第五具體實施例中，積體電路封裝件系統之上視圖；
第9圖係第8圖沿線9--9之積體電路封裝件系統之剖面圖；
第10圖係本發明之第六具體實施例中，積體電路封裝件系統之上視圖；
第11圖係第10圖沿線11--11之積體電路封裝件系統之剖面圖；
第12圖係本發明之第七具體實施例中以第10圖之上視圖為例之積體電路封裝件系統之剖面圖；
第13圖係本發明之第八具體實施例中，積體電路封裝件系統之上視圖；
第14圖係第13圖沿線14--14之積體電路封裝件系統之剖面圖；
第15圖係第2圖之積體電路封裝件系統於形成包覆體之步驟中之剖面圖；以及
第16圖係本發明之具體實施例中，積體電路封裝件系統之積體電路封裝件製造方法之流程圖。
100．．．積體電路封裝件系統
102．．．裝置結構
104．．．接觸墊
108．．．承載件
114．．．防溢料結構
116．．．電性互連
118．．．第一積體電路裝置
120．．．被動裝置
222．．．第二積體電路裝置
224．．．間隔件
226．．．包覆體高度
228．．．封裝件包覆體
230．．．凹部
232．．．安裝裝置

Claims (10)

  1. 一種積體電路封裝件系統，包括：承載件；裝置結構，係於該承載件上方的偏移位置，該裝置結構具有連結墊和接觸墊；電性互連，係於該連結墊與該承載件之間；防溢料結構，係於該裝置結構上方，該防溢料結構係外露該接觸墊；以及封裝件包覆體，係於該承載件上方相鄰於該防溢料結構。
  2. 如申請專利範圍第1項所述之系統，其中，該裝置結構係插入件。
  3. 如申請專利範圍第1項所述之系統，其中，該裝置結構係積體電路裝置。
  4. 如申請專利範圍第1項所述之系統，其中，於該裝置結構上方的該防溢料結構包含於該連結墊上方的該電性互連的一部分上方的該防溢料結構。
  5. 如申請專利範圍第1項所述之系統，復包括於該承載件上方的第一積體電路裝置。
  6. 如申請專利範圍第1項所述之系統，復包括：積體電路裝置，係於該承載件上方；被動裝置，係於該承載件上方；以及其中，該防溢料結構係於該裝置結構上。
  7. 如申請專利範圍第6項所述之系統，復包括：積體電路晶粒，係於該承載件上方；以及其中，該裝置結構係於該承載件上方，包含：該裝置結構係於該積體電路晶粒上方。
  8. 如申請專利範圍第6項所述之系統，其中，該防溢料結構包含該防溢料結構係於該承載件之上的該裝置結構的一側上方。
  9. 如申請專利範圍第6項所述之系統，其中，於該承載件上方的偏移位置之該裝置結構包含該裝置結構具有該裝置結構的一側非平行於該承載件之邊緣。
  10. 如申請專利範圍第6項所述之系統，復包括安裝裝置，係於該防溢料結構內之該裝置結構上方。
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