TWI483312B - 使用電鍍之導電通孔之形成 - Google Patents

使用電鍍之導電通孔之形成 Download PDF

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Publication number
TWI483312B
TWI483312B TW097105225A TW97105225A TWI483312B TW I483312 B TWI483312 B TW I483312B TW 097105225 A TW097105225 A TW 097105225A TW 97105225 A TW97105225 A TW 97105225A TW I483312 B TWI483312 B TW I483312B
Authority
TW
Taiwan
Prior art keywords
layer
conductive layer
forming
semiconductor substrate
continuous conductive
Prior art date
Application number
TW097105225A
Other languages
English (en)
Chinese (zh)
Other versions
TW200850102A (en
Inventor
史巴克 泰瑞Ｇ
瓊斯 羅伯Ｅ
Original Assignee
飛思卡爾半導體公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 飛思卡爾半導體公司 filed Critical 飛思卡爾半導體公司
Publication of TW200850102A publication Critical patent/TW200850102A/zh
Application granted granted Critical
Publication of TWI483312B publication Critical patent/TWI483312B/zh

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Classifications

    • H10W20/023—
    • H10W20/0234—
    • H10W20/0242—
    • H10W20/0261—
    • H10P14/47—
    • H10W20/057—
    • H10W72/242—
    • H10W72/9415—
    • H10W72/944—

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electroplating Methods And Accessories (AREA)
TW097105225A 2007-02-27 2008-02-14 使用電鍍之導電通孔之形成 TWI483312B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/679,512 US7741218B2 (en) 2007-02-27 2007-02-27 Conductive via formation utilizing electroplating

Publications (2)

Publication Number Publication Date
TW200850102A TW200850102A (en) 2008-12-16
TWI483312B true TWI483312B (zh) 2015-05-01

Family

ID=39716386

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097105225A TWI483312B (zh) 2007-02-27 2008-02-14 使用電鍍之導電通孔之形成

Country Status (5)

Country Link
US (1) US7741218B2 (cg-RX-API-DMAC10.html)
JP (1) JP5366833B2 (cg-RX-API-DMAC10.html)
CN (1) CN101622700B (cg-RX-API-DMAC10.html)
TW (1) TWI483312B (cg-RX-API-DMAC10.html)
WO (1) WO2008106256A1 (cg-RX-API-DMAC10.html)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7939941B2 (en) 2007-06-27 2011-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of through via before contact processing
US7872357B2 (en) * 2008-03-05 2011-01-18 Taiwan Semiconductor Manufacturing Company, Ltd. Protection for bonding pads and methods of formation
US8853830B2 (en) * 2008-05-14 2014-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. System, structure, and method of manufacturing a semiconductor substrate stack
US8691664B2 (en) * 2009-04-20 2014-04-08 Taiwan Semiconductor Manufacturing Company, Ltd. Backside process for a substrate
TWI471977B (zh) * 2009-05-15 2015-02-01 精材科技股份有限公司 功率金氧半場效電晶體封裝體
TWI504780B (zh) * 2009-09-04 2015-10-21 穩懋半導體股份有限公司 一種利用無電解電鍍法將金屬種子層鍍在半導體晶片的背面及導孔的製程方法
US8304863B2 (en) * 2010-02-09 2012-11-06 International Business Machines Corporation Electromigration immune through-substrate vias
US8654541B2 (en) 2011-03-24 2014-02-18 Toyota Motor Engineering & Manufacturing North America, Inc. Three-dimensional power electronics packages
US9105628B1 (en) * 2012-03-29 2015-08-11 Valery Dubin Through substrate via (TSuV) structures and method of making the same
US9219032B2 (en) 2012-07-09 2015-12-22 Qualcomm Incorporated Integrating through substrate vias from wafer backside layers of integrated circuits
US9159699B2 (en) * 2012-11-13 2015-10-13 Delta Electronics, Inc. Interconnection structure having a via structure
JP6104772B2 (ja) * 2013-03-29 2017-03-29 ソニーセミコンダクタソリューションズ株式会社 積層構造体及びその製造方法
US9754883B1 (en) * 2016-03-04 2017-09-05 International Business Machines Corporation Hybrid metal interconnects with a bamboo grain microstructure
US10432172B2 (en) * 2016-09-01 2019-10-01 Samsung Electro-Mechanics Co., Ltd. Bulk acoustic filter device and method of manufacturing the same
JP6877290B2 (ja) * 2017-08-03 2021-05-26 東京エレクトロン株式会社 被処理体を処理する方法
US10699954B2 (en) 2018-04-19 2020-06-30 Teledyne Scientific & Imaging, Llc Through-substrate vias formed by bottom-up electroplating
KR102904447B1 (ko) 2019-07-23 2025-12-29 삼성전자주식회사 반도체 장치
US11949008B2 (en) 2020-12-30 2024-04-02 Win Semiconductors Corp. Semiconductor structure and method for forming the same
US12412810B2 (en) * 2022-03-25 2025-09-09 Applied Materials, Inc. Single side via fill process for through-vias

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040173909A1 (en) * 2003-03-05 2004-09-09 Micron Technology, Inc. Conductive through wafer vias
US20070045780A1 (en) * 2005-09-01 2007-03-01 Salman Akram Methods of forming blind wafer interconnects, and related structures and assemblies

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JPH08279510A (ja) 1995-04-04 1996-10-22 Murata Mfg Co Ltd 半導体装置の製造方法
JPH11135506A (ja) * 1997-10-31 1999-05-21 Nec Corp 半導体装置の製造方法
US6221769B1 (en) * 1999-03-05 2001-04-24 International Business Machines Corporation Method for integrated circuit power and electrical connections via through-wafer interconnects
US7179738B2 (en) * 2004-06-17 2007-02-20 Texas Instruments Incorporated Semiconductor assembly having substrate with electroplated contact pads
US7109068B2 (en) * 2004-08-31 2006-09-19 Micron Technology, Inc. Through-substrate interconnect fabrication methods
JP2006210369A (ja) * 2005-01-25 2006-08-10 Murata Mfg Co Ltd 半導体装置およびその製造方法
JP2007049103A (ja) * 2005-08-05 2007-02-22 Zycube:Kk 半導体チップおよびその製造方法、ならびに半導体装置
US7608538B2 (en) * 2007-01-05 2009-10-27 International Business Machines Corporation Formation of vertical devices by electroplating

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040173909A1 (en) * 2003-03-05 2004-09-09 Micron Technology, Inc. Conductive through wafer vias
US20070045780A1 (en) * 2005-09-01 2007-03-01 Salman Akram Methods of forming blind wafer interconnects, and related structures and assemblies

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
"A Novel Electrically Conductive Wafer Through Hole Filled Vias Interconnect For 3D MEMS Packaging"，C.S.Premachandran, Ranganathan Nagarajan, Chen Yu, Bang Xiolin, Chong Ser Choong，2003 Electronic Components and Technology Conference *

Also Published As

Publication number Publication date
TW200850102A (en) 2008-12-16
JP2010519780A (ja) 2010-06-03
CN101622700A (zh) 2010-01-06
JP5366833B2 (ja) 2013-12-11
US20080206984A1 (en) 2008-08-28
US7741218B2 (en) 2010-06-22
WO2008106256A1 (en) 2008-09-04
CN101622700B (zh) 2011-05-25

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