TWI480987B - 在核心中具有電鍍通孔(pth)的設備及系統，和製作電鍍通孔(pth)於核心中的方法 - Google Patents

在核心中具有電鍍通孔(pth)的設備及系統，和製作電鍍通孔(pth)於核心中的方法 Download PDF

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TWI480987B
TWI480987B TW100145057A TW100145057A TWI480987B TW I480987 B TWI480987 B TW I480987B TW 100145057 A TW100145057 A TW 100145057A TW 100145057 A TW100145057 A TW 100145057A TW I480987 B TWI480987 B TW I480987B
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pth
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TW201240041A (en
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Debendra Mallik
Mihir Roy
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Intel Corp
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Description

在核心中具有電鍍通孔(PTH)的設備及系統，和製作電鍍通孔(PTH)於核心中的方法
本發明的實施例係有關半導體封裝技術，且更明確地說，係有關藉由消除接墊-至-電鍍通孔(PTH)對齊之邊緣並致能基板之核心上的細微跡線而具有縮減尺寸之電鍍通孔(PTH)接墊的半導體封裝技術。
印刷電路板(“PCB”)為多層板，其包括印刷在一或更多層之絕緣(亦稱為介電質)材料上的印刷電路。印刷電路為導體的圖案，其對應於形成在一或更多層絕緣材料上之電子電路的佈線。印刷電路板包括路由安排(routing)於PCB之各種不同層上的電跡線。PCB也包括貫孔(via)，其為將一層連接到另一層的實心電氣路徑。貫孔可被使用而將PCB之一層上的跡線連接到PCB之另一層上的另一跡線。
PCB也包括了其它的金屬層以供接地平面、電源平面或參考電壓平面等用。在很多例子中，信號載帶貫孔必須路由安排通過一或更多的這類平面。信號載帶貫孔不能夠電連接到或耦接到這些平面，如果信號傳送貫孔與這些平面的其中之一耦接或連接，則會危害到電路的完整性。因此，需要抵抗接墊(anti-pad)或隔離孔環(plane clearance)以將信號載帶貫孔與接地平面、電源平面或具有參考電壓的平面隔開。抵抗接墊為隔離孔環。通常，在使傾向使抵抗接墊尺寸最小化之因素與那些使抵抗接墊尺寸最大化之 因素相平衡之後，最小的抵抗接墊間距被載明於該設計中。為了藉由使參考平面緊密屏蔽鄰接之接腳以降低雜訊、為了藉由使參考平面中的孔徑尺寸最小化以降低電磁干擾(EMI)、以及為了使單端信號與接地參考差分信號對於接地保持夠強的參考，抵抗接墊將會被最小化。為了使接腳與參考平面之間的電壓崩潰間隔最大化、為了藉由降低短路之機會而提高可製造性、及藉由降低電鍍通孔(用來取代貫孔)之電容效應而降低高速十億位元串列系統中之反射，抵抗接墊將會被最大化。
近年來，半導體產業在技術上已有驚人的進步，其允許電路密度與複雜度顯著的增加，而在電力消耗與封裝尺寸上同樣有著顯著的降低。現在，目前的半導體技術允許封裝在相當小、空氣冷卻的半導體裝置封裝內的單晶片微處理器具有數百萬個電晶體，以每秒數百萬指令(MIPS)之數十或甚至數百倍之速度操作。在半導體裝置中之如此高密度及高功能性的副作用，係對於製造具有較高密度設計之PCB的壓力不斷增加。隨著較高密度的設計愈來愈多，違反為孔壁與鄰接之導電特徵間之最小介電間隔所建立之產業可靠度規格的風險也變得較大。產業界也有可能隨著裝置密度的增加，更縮小特徵之間的最小介電間距。
本說明書全文所提及“一個實施例”或“一實施例”意指所描述與該實施例有關的特定特徵、結構、或特性，亦包 括在本發明至少一實施例中。因此，出現在本說明書中各處的“在一個實施例中”或“在一實施例中”等片語，並不必須都參考相同的實施例。此外，在一或更多個實施例中，可按任何適當的方式結合特定的特徵、結構、或特性。
現請參閱圖1，圖中顯示說明性半導體封裝組件100的剖面視圖。封裝組件100包括了其中包含有核心102的多層電路板，核心102的兩側包括有積壓之一或更多層的介電層104。可設置複數個導電貫孔106，以建立通過介電層104的導電路徑。可設置電鍍通孔(PTH)108以提供通過核心102到導電層110的垂直連接。半導體晶粒112可用倒裝式晶片接合法而以焊球114連接於外表的導體層。
核心102材料的例子可包含陶瓷或玻璃介電體。例如，核心102可包含一或更多種選擇自包含氧化鋁、氧化鋯、碳化物、氮化物、熔矽石、石英、藍寶石、或任何其它陶瓷或玻璃介電材料的族群。在一個實施例中，用於核心102的陶瓷材料可具有全密度或大量的孔。在另一實施例中，用於核心102的材料可具有高於20 GPa(例如，在室溫中)的楊氏模數。例如，用於核心102的材料可具有高於100 GPa(例如，在室溫中)的楊氏模數。在另一實施例中，用於核心102的材料可具有與要被耦接於核心102之半導體晶粒近似的熱膨脹係數(CTE)。例如，核心102可包含CTE低於12 ppm/℃的材料。在一個實施例中，陶瓷核心102可以結合高k陶瓷薄膜去耦合電容器。
在又一實施例中，用於核心102的陶瓷材料可包含氧 化鋁，其可與氧化矽或其它元素化合。在另一實施例中，陶瓷材料可與例如約50%至100%的三氧化二鋁化合。在另一實施例中，核心102的厚度可由楊氏模數及核心102的剛性來決定。在一個實施例中，核心102的剛性可與Ed3 成比例，其中，E代表楊氏模數及d代表厚度。核心102的厚度可從約50微米至約400微米；不過，在某些實施例中，核心102可具有不同的厚度。在另一實施例中，核心102之材料具有的熱導率可從約2 W/m．k至約50 W/m．k。在另一實施例中，該材料可具有從約9 KV/mm至約50 KV/mm的介電強度。不過，在某些實施例中，也可利用具有不同熱導率及/或不同介電強度的其它材料。
在一個實施例中，該材料可具有低於0.01(例如，在1 GHz)的逸散因數。例如，該材料可具有低於約0.0003的逸散因數。在又另一實施例中，該材料可具有的介電常數從例如約5至約20(例如，在1 GHz)。在另一實施例中，該材料可具有約0的吸水率。不過，在某些實施例中，也可利用具有不同特性組合的其它陶瓷材料或玻璃材料。
在另一實施例中，例如，核心102可包含楊氏模數高於以聚合物為基礎之有機核心材料的無機材料。例如，無機材料的楊氏模數可以高於以聚合物為基礎之有機核心材料的2至14倍；不過，在某些實施例中，無機材料可具有不同的楊氏模數。在一個實施例中，縮減核心厚度的核心102可具有相當或加大的剛性。
導電層110可被選擇性地圖案化，以便在核心102的 上方側及/或下方側提供一或更多之導電元件中的第一組，諸如跡線、平面或互連接腳。介電層104可被設置在核心102的上方。介電層104之實例材料例如可包含顆粒填充的材料，諸如Ajinomoto積壓膜(ABF)或玻璃纖維強化環氧樹脂，諸如預浸的材料，或其它絕緣或介電材料。在一個實施例中，可利用表面粗糙化法及/或諸如矽烷處理的黏著促進法而將介電層104接合於核心102。例如，用於核心102的一或更多片生坯薄板可被粗糙化，例如在火烤之前，以增加核心102的表面粗糙度。
在該結構中可選擇性地形成一或更多個通孔108的組。在一個實施例中，可使用雷射器來提供通孔108。雷射器可具有奈秒級的脈衝寬度。在某些實施例中，雷射的脈衝寬度可短於奈秒。在一個實施例中，雷射器的光譜範圍可從紅外線輻射(IR)到深紫外線(DUV)。例如，雷射器可包含具有1064 nm、532 nm、355 nm、266 nm之諧波或任何其它諧波的Q切換型(Q-switched)或模式鎖定型(mode-locked)Nd：YAG或Nd：YVO4雷射器；具有1053 nm、527 nm、351 nm、263 nm之諧波或任何其它諧波的Q切換型或模式鎖定型Nd：YLF雷射器；或纖維雷射器。在另一實施例中，雷射器可具有從kHz至MHz之位準的脈衝重複頻率；不過，在某些實施例中，可使用任何其它的雷射器或裝置。
現請參閱圖2A-2E，圖中顯示使用雷射鑽孔法以製造通過核心200而垂直互連之電鍍通孔(PTH)的處理流程。 在圖2A中顯示核心200具有富含樹脂的外部區域202。在此，富含樹脂意味著基板核心之該區帶中被用來提供所想要之機械特性(諸如，高剛性或較低的CTE)的玻璃纖維及填充材料，被優先地拉入到基板之核心的內部側，留下頂部與底部最多(~10-20微米)約90-100%的有機環氧樹脂。在圖2B中，以雷射鑽孔法鑽出通孔208，且具有的直徑範圍從頂部側與底部側的約100微米，及通孔(TH)之中央部位處的60-90微米，使得實際的TH看似為沙漏結構。在某些實施例中，通孔(TH)208可具有不同的尺寸。在另一實施例中，在結構中會鑽一或更多個多餘的通孔(未顯示出)。塗覆銅(Cu)箔條片204，之後，利用乾膜光阻(DFR)製程來產生圖案。
在圖2C中，DFR被曝光，接著剝除以形成210的細線與間隔(FLS)圖案(寬度<20微米)。在圖2D中，通孔208例如可以使用無電電鍍，而後使用電解銅電鍍來予以填充，以填滿垂直互連210。在其它實施例中，也可使用其它的導電材料。銅也可填滿其它的圖案空隙，以產生導電區212。
如圖2E所示，開始其它介電層214的積壓製程，諸如Ajinomoto積壓膜(ABF)。
再參閱圖2A至2E，圖中顯示基板面板之在連續製程步驟期間的剖面，其經由對基板之核心進行半加成製程(SAP)而致能基板具有縮減的接墊尺寸。圖2A描繪引入之預浸核心200，其具有恰位於被包覆到引入之核心材料內 之銅箔下方的富含樹脂區202。圖2B顯示的基板面板，其具有藉由蝕刻而被去除到厚度約1-2微米的銅箔，而後經由雷射鑽孔法來鑽通孔(TH)貫孔208，隨後是無電銅電鍍206，然後施加乾膜光阻以完成後續的圖案化204。接著，圖2C描繪曝光、顯影、而後剝除DFR材料以形成用於路由跡線之溝槽212的剖面。圖2D描繪基板被填以電解銅填料(filling)的剖面視圖。此填料同時填滿TH貫孔210、溝槽212及貫孔接墊216。接著，圖2E顯示的剖面視圖為DFR被完全剝除，而後在正側與背側上層疊介電材料之基板製程214。接著，可以繼續後續的BU製程。
圖3說明依據本發明之實施例之縮減接墊尺寸之基板的剖面視圖。基板包含具有富含樹脂外層202的核心200，在核心200的兩側上具有一或更多層ABF積壓層214。複數個電鍍通孔(PTH)210提供通過核心200之垂直的電路徑，並連接到貫孔206及其它導電區，諸如，各種不同ABF層214中的跡線212。在基板的上方側上設置有焊球300，諸如用於以倒裝式晶片接合法與半導體晶粒連接，且在基板之底側上也設置有焊球。
參閱依據本發明之實施例的圖4A與4B，用來在核心200內產生通孔之雷射鑽孔尺寸約為100微米。此實質上小於目前使用的鑽孔尺寸，目前使用的鑽孔尺寸為250微米以上。使用雷射鑽孔製程可允許接墊尺寸小至100微米至150微米或甚至更小(圖2D中的216)。此外，由於在頂部富含樹脂核心應用銅箔的半減成製程，或如圖2A-2E中 所示在核心中應用半加成製程(SAP)，因此允許20微米/20微米的核心路由安排(RTG)與線間距離(L/S)。以此製程，抵抗接墊尺寸可小至200微米，其允許習知技術之設計所無法做到的核心參照(core referencing)。
接墊愈小，則各接墊間所允許的導線(如圖4B所示)愈多。此外，較小的接墊可使抵抗接墊更小，以致於核心層可做為參考層。這些優點可提供封裝組件層數縮減。除了這些優點之外，藉由較小的鑽孔尺寸可做到較小的接墊，藉由雷射鑽孔可避免機械鑽孔的成本，以雷射所鑽之孔可用電鍍銅來予以填充，使其對於用在電感式供電的封裝組件更為堅固。
縮小的PTH接墊與縮小的溝槽寬度，允許各接墊之間通過更多的跡線、尺寸縮小的抵抗接墊、及縮小的PTH間距。所有這些都有利於基板封裝組件設計。同時，在相同的封裝組件空間(real estate)內愈多的跡線允許愈多的路由線路，做到在相同的空間上具有較高輸入/輸出(IO)數的封裝效果，較緊密的PTH間距使得封裝組件尺寸(形狀因數)有效地變得更小。
比較圖4A與4B，依據實施例的圖4B顯示，現在可通過各接墊間之不同的跡線及路由佈線的數量為接墊尺寸的函數。跡線的數量增加，允許將更多的信號可被侷限在層1F中(圖2E中的212)。如果此信號計數增加的足夠，即有可能減消BU層中的層對。
以上對本發明之說明性實施例的描述，包括摘要中之 描述，並無意窮舉或將本發明限制在所揭示之精確的形式。雖然本文基於說明之目的而描述了本發明的特定實施例及例子，但在本發明的範圍內可做各種等同物的修改，而熟悉相關技術之人士都可識出這些修改。
根據以上的詳細描述，可對本發明做到這些修改。以下申請專利範圍中所使用的術語不應被解釋成將本發明限制於說明書及申請專利範圍中所揭示的特定實施例。更確切地說，本發明的範圍完全由以下的申請專利範圍來決定，申請專利範圍應被理解為與申請專利範圍解釋的確立文件一致。
100‧‧‧半導體封裝組件
102‧‧‧核心
104‧‧‧介電層
106‧‧‧導電貫孔
108‧‧‧電鍍通孔(PTH)
110‧‧‧導電層
112‧‧‧半導體晶粒
114‧‧‧焊球
202‧‧‧富含樹脂區
208‧‧‧通孔
210‧‧‧垂直互連
212‧‧‧導電區
214‧‧‧介電層
200‧‧‧核心
212‧‧‧溝槽
216‧‧‧貫孔接墊
206‧‧‧貫孔
300‧‧‧焊球
當結合附圖閱讀對於配置、例示之實施例及申請專利範圍之詳細描述，將會對前文及本發明有更佳的瞭解，所有為構成本發明之揭示的一部分。雖然前文及後文所撰及所說明的揭示係集中在揭示本發明的配置及例示實施例，但應明白地瞭解，這些僅是藉由說明及例示，且本發明並不受限於此。
圖1係依據本發明之實施例之多層半導體封裝組件的剖面視圖。
圖2A-2E係說明依據本發明之實施例，在核心中製造電鍍通孔之製程的剖面視圖。
圖3係依據本發明之實施例之縮減之接墊基板的剖面視圖。
圖4A及4B係從封裝組件1F層(僅圖2E中標示為212之層的正面)之頂視來顯示目前之PTH接墊與依據本發明之實施例之PTH接墊、抵抗接墊、路由跡線(也稱為細線與間隔-FLS)，及PTH間距的比較。
100‧‧‧半導體封裝組件
102‧‧‧核心
104‧‧‧介電層
106‧‧‧導電貫孔
108‧‧‧電鍍通孔(PTH)
110‧‧‧導電層
112‧‧‧半導體晶粒
114‧‧‧焊球

Claims (17)

  1. 一種在核心中具有電鍍通孔(PTH)的設備，包含：基板核心；在該核心上的富含樹脂外層；複數個電鍍通孔(PTH)以提供通過該核心之垂直電路徑，該等電鍍通孔(PTH)在該核心之頂側與底側具有約100微米之直徑；以及在該等電鍍通孔之間的複數條跡線，其具有約20微米/20微米的線間距離(L/S)。
  2. 如申請專利範圍第1項的設備，進一步包含：在該核心之該頂側與底側上的積壓層；以及在該等積壓層中的貫孔，係電連接到該等電鍍通孔(PTH)。
  3. 如申請專利範圍第1項的設備，其中，該等電鍍通孔(PTH)具有沙漏形狀。
  4. 如申請專利範圍第3項的設備，其中，該等電鍍通孔(PTH)在該核心之該頂側與底側具有約100微米之直徑，且在提供該沙漏形狀之中央部位的直徑約為60-90微米。
  5. 如申請專利範圍第1項的設備，其中，該富含樹脂外層的厚度為約10-20微米。
  6. 如申請專利範圍第1項的設備，其中，該富含樹脂外層包含約90-100%的有機環氧樹脂。
  7. 如申請專利範圍第2項的設備，進一步包含電連接 到該貫孔的接墊，及以倒裝式晶片接合法而被連接到該等接墊的半導體晶粒。
  8. 一種製作電鍍通孔(PTH)於核心中的方法，包含：提供具有富含樹脂外層的基板核心；在該富含樹脂外層上提供銅箔；蝕刻該銅箔以縮減其厚度；雷射鑽孔該基板核心而產生通孔，以提供通過該核心的垂直路徑；提供銅電鍍層；使用乾膜光阻而將該銅電鍍層圖案化，以形成用來形成跡線及貫孔的溝槽；以電解銅來填充而同時填滿該跡線及貫孔及通孔，以形成電鍍通孔(PTH)，其中，該等電鍍通孔(PTH)在該核心之頂側與底側具有約100微米之直徑，並且在提供沙漏形狀之中央部位的直徑約為60-90微米；以及繼續而形成介電積壓層。
  9. 如申請專利範圍第8項的方法，其中，在該等電鍍通孔(PTH)之間的該複數條跡線具有約20微米/20微米的線間距離(L/S)。
  10. 如申請專利範圍第8項的方法，其中，該富含樹脂外層的厚度為約10-20微米。
  11. 如申請專利範圍第8項的方法，其中，該富含樹脂外層包含約90-100%的有機環氧樹脂。
  12. 如申請專利範圍第8項的方法，進一步包含： 在該貫孔上形成接墊；以及以倒裝式晶片接合法而將半導體晶粒連接到該等接墊。
  13. 一種在核心中具有電鍍通孔(PTH)的系統，包含：基板核心，在該核心上的富含樹脂外層；複數個電鍍通孔(PTH)以提供通過該核心之垂直電路徑，該等電鍍通孔(PTH)在該核心之頂側與底側具有約100微米之直徑；在該等電鍍通孔(PTH)之間的複數條跡線，具有約20微米/20微米的線間距離(L/S)；在該核心之該頂側與底側上的積壓層；在該積壓層中電連接到該等電鍍通孔(PTH)的貫孔；係電連接到該等積壓層的接墊；以及以倒裝式晶片接合法連接到該等接墊的半導體晶粒。
  14. 如申請專利範圍第13項的系統，其中，該等電鍍通孔(PTH)具有沙漏形狀。
  15. 如申請專利範圍第14項的系統，其中，該等電鍍通孔(PTH)在該核心的頂側與底側具有約100微米之直徑，且在提供該沙漏形狀之中央部位的直徑約為60-90微米。
  16. 如申請專利範圍第13項的系統，其中，該富含樹 脂外層的厚度為約10-20微米。
  17. 如申請專利範圍第13項的系統，其中，該富含樹脂外層包含約90-100%的有機環氧樹脂。
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