TWI480964B - 線接合結構以及消除特殊線接合加工與縮減基板上之接合間距的方法 - Google Patents
線接合結構以及消除特殊線接合加工與縮減基板上之接合間距的方法 Download PDFInfo
- Publication number
- TWI480964B TWI480964B TW097129182A TW97129182A TWI480964B TW I480964 B TWI480964 B TW I480964B TW 097129182 A TW097129182 A TW 097129182A TW 97129182 A TW97129182 A TW 97129182A TW I480964 B TWI480964 B TW I480964B
- Authority
- TW
- Taiwan
- Prior art keywords
- bonding
- wire
- substrate
- finger
- bond
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4807—Shape of bonding interfaces, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48095—Kinked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48455—Details of wedge bonds
- H01L2224/48456—Shape
- H01L2224/48458—Shape of the interface with the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
- H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
- H01L2224/48477—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding)
- H01L2224/48478—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball
- H01L2224/48479—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
- H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
- H01L2224/48477—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding)
- H01L2224/48478—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball
- H01L2224/4848—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
- H01L2224/48499—Material of the auxiliary connecting means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
- H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/48644—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
- H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/48647—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
- H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48738—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/48744—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
- H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48738—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/48747—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
- H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48838—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/48844—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
- H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48838—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/48847—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85009—Pre-treatment of the connector or the bonding area
- H01L2224/85051—Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/85444—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/85447—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01027—Cobalt [Co]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01049—Indium [In]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Description
本申請案為2005年11月14日提出之美國專利申請案第11/273,635號,現為美國專利第7,453,156號的部份連續案,並主要該案之優先權,而該案係主張2004年11月12日提出之美國暫時專利申請案第60/627,650號的優先權。
本發明大致係關於半導體裝置,且詳言之,係關於具有消除線接合加工與縮減基板上之接合間距的需要的線接合結構。
在使用於現代社會中的許多產品中可找到半導體裝置。半導體在消費者項目中找到應用,例如娛樂、通訊、和家用項目市場。在工業或商業市場中,半導體可應用在軍事、航空、汽車、工業控制、和辦公設備。
半導體裝置的製造從形成具有複數個晶粒的晶圓開始。每個晶粒包含數百或數千的電晶體和其他用以執行一個或更多個電氣功能的電氣裝置。對於既定的晶圓,每個來自該晶圓的晶粒係執行相同的電氣功能。前端製造一般係指形成在晶圓上的電晶體。後端製造一般係指將該完成的晶圓切割或分離成個別的晶粒,然後封裝該晶粒用於結構支撐和環境隔離。
該封裝件具有用以傳遞電氣訊號進出該晶粒的外部金
屬觸點(contact)。該晶粒具有許多接合墊,其藉由線接合以連接該封裝件的外部觸點。線接合提供在該半導體裝置與其他在該半導體封裝件外部的電路之間的電氣互連。該線接合係用以在該晶粒的主動面上的墊(pad)與在該基板上的導線架(lead frame)或接合指狀墊(bond finger)的接合部之間造成連接。
線接合通常涉及使用鍍膜槽(plating buss)的電解鍍膜製程,以在鎳層(約5至10微米(micron))上鋪設金層(約0.5微米)。不幸地,該鍍膜槽很佔空間,且難以高密度設計。此外,該鍍膜槽係造成不必要的寄生效應(parasitic effect)且需要另一製程步驟以移除該槽。因此需要消除該以鎳為主的電鍍製程和來自該線接合需求的鍍膜槽。
在一個實施例中,本發明係為一種半導體封裝件,包括基板和設置在該基板上的半導體晶粒。接合線係連接於在該半導體晶粒上的第一接合部與在該基板上的第二接合部之間。該第二接合部具有形成於該基板上的接合指狀墊、直接物理接觸該接合指狀墊的銅層、耦接到該結合線並直接物理接觸該銅層的接合栓(stud),其傳導來自該半導體晶粒的電氣訊號到該接合指狀墊。
在另一個實施例中,本發明係為一種半導體封裝件,包括基板和設置在該基板上的半導體晶粒。接合線係連接於在該半導體晶粒上的第一接合部與在該基板上的第二接合部之間。該第二接合部具有形成於該基板上的接合指狀
墊、直接物理接觸該接合指狀墊的導電層、耦接到該結合線並直接物理接觸該導電層的接合栓(stud),其傳導來自該半導體晶粒的電氣訊號到該接合指狀墊。
在另一個實施例中,本發明係為一種半導體封裝接合部,包括接合線、接合指狀墊、接觸該接合指狀墊的導電層、與耦接到該結合線並直接物理接觸該導電層以傳導電氣訊號的接合栓。
在另一個實施例中,本發明係為一種製造半導體封裝件的方法,包括下列步驟:形成基板、在該基板上設置半導體晶粒、以及在該半導體晶粒上的第一接合部與在該基板上的第二接合部之間連接接合線。連接該接合線的步驟包含:在該基板上形成接合指狀墊、形成直接物理接觸該接合指狀墊的導電層、以及形成耦接到該結合線並直接物理接觸該導電層的接合栓,其傳導來自該半導體晶粒的電氣訊號到該接合指狀墊。
本發明係參照圖式的下列描述以藉由一個或更多個實施例來描述。其相似的元件符號代表相同或相似的元件。雖然係以達成本發明目的之最佳態樣來描述本發明,但是熟習此技藝之人士應了解的是,本發明係涵蓋所有落於如由下列揭露與圖式所支持的所附申請專利範圍與其等效物所界定之本發明之精神和範圍內之替代、修飾和等效內容。
該半導體裝置的製造係開始於形成具有複數個晶粒的晶圓。每個晶粒包含數百或數千的電晶體和其他用以執行
一個或更多個的電氣功能的電氣裝置。對於既定的晶圓,每個來自該晶圓的晶粒係執行相同的電氣功能。前端製造一般係指形成在晶圓上的電晶體。後端製造一般係指將該完成的晶圓切割或分離成個別的晶粒,然後封裝該晶粒用於結構支撐和環境隔離。
該封裝件具有用以傳遞電氣訊號進出該晶粒的外部金屬觸點。該晶粒具有許多接合墊,其藉由線接合以連接該封裝件的外部觸點。線接合提供在該半導體裝置與其他在該半導體封裝件外部的電路之間的電氣互連。該線接合係用以在該晶粒的主動面上的墊與在該基板上的導線架或接合指狀墊的接合部之間造成連接。
在第1圖(先前技術)中,係顯示傳統的線結合互連。半導體晶粒14係主動側(active side)朝上地安裝在基板12的貼晶面(die attach surface)上且係使用貼晶黏著劑13來貼上。該晶粒14的主動側係設置有互連墊(interconnect pad)22。基板12係包含至少一層介電材料和至少一圖案化金屬層。在基板12的該貼晶側中的金屬層係圖案化以提供適當的電路跡線(trace),包括接合指狀墊32。該晶粒14係藉由線26以電性互連至該基板12上的電路,該線26係形成於晶粒墊22與接合指狀墊32之間。
線接合26係使用機器來形成,該機器包含毛細管接合工具、要線接合的該裝置的支撐物、熱源、給予超音波振動到該毛細管接合工具的來源和轉能器(transducer)、以及用以調整這些機器元件的移動與功能的自動控制。線通常
是鋁或金,係攜帶在該毛細管的管腔中,而該機器控制該線移動通過該毛細管的尖端(tip)。要形成如第1圖(先前技術)中的範例的線接合,該晶粒係貼到該基板,然後該晶粒和基板被安裝在該支撐台上。該支撐物藉由加熱該基板和晶粒而設置。該毛細管懸在該晶粒和基板上不動,線係經由該毛細管腔來供給,俾使其從該毛細管尖端突出所選擇的長度。
為了形成該球接合,打出(strike)電弧(electric arc)以在該線的突出端上形成熔化的球(molten ball)。該毛細管移到該晶粒和基板的上方,俾使該尖端對準在例如該晶粒墊的目標接合部上方的x-y平面中。當該毛細管降低以帶著該球接觸該目標接合部時,拉張力於該線以拉該球回到該毛細管尖端中的凹槽(chamfer)中。該毛細管係在z方向上移動以將該球壓向該結合部,而該轉能器係啟動以給予超音波振動給該毛細管。當該球被壓向該目標時,該毛細管尖端、且特別是在抓住該球的該凹槽係給予振動至該球。在該球與目標之間形成冶金接合以完成該球接合。
為了形成該線迴路,經由該毛細管以供給該線,該毛細管抬升並遠離該目標,然後控制以關於該晶粒與基板的路徑來移動,朝向對準該第二目標接合部上的x-y平面的位置以控制該完成線接合的最終形狀。
為了對接合指狀墊32形成針法接合(stitch bond),該毛細管降低以將該線壓向該接合指狀部,當該線被擠壓向該目標部時,該轉能器再次啟動以給予振動到該線,在該
線與目標部之間形成冶金接合。該毛細管沿著該接合部移動,然後抬高,形成從該毛細管尖端突出的線尾。最後,當該毛細管進一步抬高時緊抓該線,導致該線在靠近該第二接合處斷裂,並留下從該毛細管尖端突出的該線尾,以準備給藉由在該線端的電弧形成之後的球。
該球接合係以兩個視圖來顯示在第2A圖(先前技術)和第2B圖(先前技術)中,而該針法接合係以兩個視圖來顯示在第3A圖(先前技術)和第3B圖(先前技術)中。該完成的球接合包含冶金接合至晶粒墊22的壓縮球24。該完成的針法接合包含冶金接合至接合指狀墊32上的平坦面或墊的壓扁的線端34。該線的殘留物(residue)可適當地餘留在該墊上,如區域35所指出。將瞭解的是,依據其他的該毛細管尖端的形狀與尺寸以及不同的其他製程參數,將預期有一些該接合的形狀變化。特別是,使用的已知機器與製程參數可導致在該針法接合的一些變化,這是由於該線是斷裂以完成該接合的事實。
如第3A圖(先前技術)中所具體顯示的,該接合指狀墊或接合墊典型上具有在一般平坦平台表面上的該接合部,有時稱為「平坦面(flat)」,該接合形成於其上,其通常顯著地寬於形成於其上的該完成的針法接合,如上面所討論。
上述的該製程通常稱為正向線接合製程(forward wire bonding process),相對於反向線接合製程(reverse wire bonding process)。在反向線接合製程中,該球接合形成在
該引線指狀平坦面(lead finger flat)或墊上,且該針法接合係形成在該晶粒墊上。可適當的將反向線接合製程連接基板至晶粒,抬升靠近該針法接合的該線的第二端,避免接觸該線至該晶粒的主動面。因此在反向線接合製程中,球可形成在該晶粒墊上,該針法接合也形成於其上。這樣的程序係顯示在美國專利第6561411號中。
反向線接合互連的說明範例係顯示在第4圖(先前技術)中。如同在第1圖(先前技術)的該正向線接合之範例中,半導體晶粒14係主動側向上地裝在基板12的貼晶面上並使用貼晶黏著劑13來固定。該晶粒14的主動側係提供有互連墊22。基板12包含至少一層介電材料與至少一圖案化金屬層。在該基板12的貼晶側中的金屬層係圖案化以提供適當的電路跡線(trace),包含接合指狀墊32。該晶粒14係藉由形成於晶粒墊22和接合指狀墊32之間的線26以電性互連至基板12上的該電路系統。在該反向線接合組構中,球接合24係形成在接合指狀墊32的平坦面或墊上,而針法接合54係形成在腳座(pedestal)56上,其係為之前沉積於晶粒墊22上而形成的球。形成在腳座56上的針法接合54係依序形成在晶粒墊22上,第5圖中顯示進一步的細節。
在使用正向線接合的地方原則上有可能藉由降低該接合部的寬度以讓該基板上的該互連的間距更小。第6A圖與第6B圖係說明具有較窄接合指狀墊的針法接合的適當對準(alignment)與不良對準(misalignment)的結果。在此,
該接合指狀墊係窄於該針法接合且可比做使用該相同毛細管的球接合中的該壓縮球的直徑。
當充分精確地對準時,如第6A圖中所說明的理想情況,該針法接合可為令人滿意的堅固。在此,在該第二線端66的部分64與該狹窄的接合指狀墊62之間可有足夠好的冶金接合,雖然這可依據由斷裂線65所略述的該平坦線的該平坦殘留物的程度,該斷裂線65的形狀是不可靠的,該斷裂線65可幫助提供好的導電互連。
當沒那麼完美地對準時,如第6B圖中所說明的,該第二結合製程可失去使接合指狀墊62有好的連接的作用。沒辦法確定該第二接合製程的線端66的該最後部分66和殘留物65的組構,但是在任何的情況中,可能無法適當地確保前後一致或可靠的或堅固的接合。因此,嘗試藉由窄化在該指狀引線(lead finger)上的該平坦寬度以減少指狀引線間距一般是無法接受的。
該接合指狀墊在該針法接合部處是狹窄的,腳座係形成在該狹窄結合部上,且該針法接合係形成在該腳座上。該腳座可以形成栓凸塊(stud bump)的方式來形成為球。也就是,利用線接合設備以在該狹窄的接合指狀墊上形成球,猶如形成球接合互連,但是之後不是拉該線以形成迴路,而是當該毛細管向上移時夾住該線,俾使該線剛好在該球上斷裂,留下線尾。該球的上方包含該線尾,可在形成該針法接合之前藉由整平(coining)來平坦化以形成大致平坦的表面。該針法接合係大致如上述地參照第3A和3B
圖來形成,除了該針法接合係形成在該腳座72的平坦表面上而不是該接合指狀墊32的平坦平台表面上之外。該完成的針法接合包含冶金接合至腳座72的壓扁的線端74,而該線的殘留物可適當地殘留在該墊上,如區域75中所指出的。依據其他的該毛細管尖端的形狀與尺寸以及不同的其他製程參數,將預期該第一和第二接合有一些形狀變化。特別是,使用的已知機器與製程參數可導致在該第二接合的外表的一些變化,這是由於該線是斷裂以完成該接合的事實。
最終的第二接合係顯示在第7A和7B圖中。在指狀引線上的狹窄接合部62具有大致梯形的、或大約三角形或截頭形的(truncated)、或大約具有圓形尖端的三角剖面(見第7C至7E圖)。該指狀引線的該接合部部份62具有大致梯形剖面、大約平坦的上端,在該接合部上的該接合指狀墊的平坦上端71的該寬度WP係小於支撐腳座72的該寬度WB。稍微大於該平坦上端71的寬度WP的在該接合部處的該接合指狀墊的底邊73的寬度WF係通常也小於支撐腳座72的該寬度WB。典型上,該接合指狀墊的接合部部分的頂端71係並不完美地平坦且該邊緣並不清楚地界定。如第7D圖中所說明的,可圓角該接合指狀墊的該接合部部分的頂端77。該接合指狀墊的該接合部部分的頂端係窄於該腳座直徑,而在該接合指狀墊的該接合部部分上形成支撐腳座72的該製程係使得該球變形在該接合部處的該指狀引線周圍。因此,可使該接合指狀墊成比例地遠窄於該
腳座直徑WB,且如第7E圖所說明的,可窄化該接合部處的該接合指狀墊,俾使該剖面形狀近似三角形並帶有頂點79,如第7E圖中的例子所說明的。如第7C至7E圖中的該斷面圖所顯示,不論在該接合部處的該指狀引線具有大致平坦或圓形的台地(plateau)、還是具有尖銳或圓形的頂點,支撐腳座72適應該台地或頂點的形狀;也就是,當形成該支撐腳座時,其適應於該指狀引線的至少一側的至少該上面部分。該支撐腳座係在其形成過程中精確地對準該接合部,俾使其對稱地沉積在該指狀引線上,且因此部分該腳座已經同等地變形在該指狀引線的兩側上。不必要完美地對準該支撐腳座,而實際上該變形在某種程度上可為非對稱的。此外,如第8圖中的範例所說明的,該指狀引線係在z方向上是足夠地薄的,部分支撐腳座82可沿著該指狀引線63的底邊接觸該基板12的表面。在球與該指狀引線的相對窄的接合部部分之間係可形成該堅固的電性連接,且可可靠地在因此形成的支撐腳座72、82上形成針法接合75,如在第7C至7E圖與第8圖中所說明的。
由於該線長度和基板面積係取決於該指狀引線接合墊間距,減低該接合間距可導致顯著的線長度縮短和基板面積減少。
可了解的是,該特徵寬度可在該基板上的該不同引線和指狀引線之中變化,且可沿著已知引線或指狀引線的該長度來變化,該指狀引線係小於該接合部上的該支撐腳座直徑,也就是,在沿著形成該支撐腳座的該引線的長度的
地方;該跡線在其他點可較窄或較寬,俾使獲得該想要的指狀引線密度和該指狀引線接合墊間距。
第9A和9B圖係以俯視圖顯示兩種指狀引線排列方式,其中,該晶粒墊間距PDP係相等於該指狀引線接合墊間距PLF,俾使該線平行排列,而不是在該指狀引線接合墊間距大於該晶粒墊間距時其必須的扇形散開(fan out)。這樣的排列有時稱作「正交的(orthogonal)」,而其提供最小線長和基板面積。晶粒墊22係沿著晶粒14的邊緣15呈一列的陣列排列。在該接合部處窄化的指狀引線62係在基板12的該貼晶表面中排列成一列,該接合指狀墊係大致對準該對應的晶粒墊。例如第9A圖中的支撐腳座72與第9B圖中的支撐腳座72和72’係形成在每個指狀引線上的該指狀引線接合部;在第9A圖中,該支撐腳座係排列成單一列,而在第9B圖中,它們排列成交錯的兩列。第9B圖的排列係在最近的支撐腳座之間提供較大的距離並同時維持該相同的間距,請參照晶粒墊間距PDP’和指狀引線接合墊間距PLF’。
參照第10A和10B圖,線接合形成在該晶粒墊和相對接合指狀墊之間,其乃是藉由在晶粒墊22上形成球接合墊24、拉線66到該相對指狀引線71接合部、與在支撐腳座72上形成針法接合74來形成,如第7A至7E圖和第8圖所描述的。
實際上,即使在該接合部的該指狀引線的寬度係如第7E和8圖所顯示地最小化,實際的製程技術極限限制在相
鄰指狀引線的間隔可最小化的程度。使用標準製程,實際上最小值的間隔可為約40μm。例如50μm或更小的非常細的晶粒墊間距係可能無法獲得排列如第9A或9B圖顯示的正交線接合。要獲得非常細的晶粒墊間距的正交線接合,可使用如第10A和10B圖中所說明的階梯式基板(tiered substrate)。在此,如同在第9A、9B圖中的,該晶粒墊係沿著晶粒14的邊緣來排成一列。具有狹窄接合部62的指狀引線係排列在第一列的較低基板12的該貼晶表面中,該指狀引線大致間隔地(第一、第三、第五等)對準該晶粒墊;具有狹窄接合部62’的指狀引線係排列在第二列的較高基板112的該貼晶表面中,該指狀引線大致間隔地(第二、第四、第六等)對準沒有在第一基板中對應到的指狀引線的該晶粒墊。該較高基板的邊緣係向後退,俾使暴露出該較低基板上的該指狀引線上的該接合部。
支撐腳座72的第一列係形成在該基板112的較低層上的指狀引線71的該暴露的指狀引線接合部,而支撐腳座172的第二列係形成在該基板112的較高層上的指狀引線171的該指狀引線接合部。線接合係形成在該晶粒墊22和個別接合指狀墊71、171之間,其藉由在晶粒墊22上形成球接合24、拉線到該個別指狀引線71、171接合部、與在支撐腳座72、172上形成針法接合74、174,如第7A至7E圖和第8圖所描述的。在該指狀引線的較低和較高列兩者中的該指狀引線接合墊間距PLF”係為該晶粒墊間距PDP’的兩倍大。在每列的該指狀引線中可獲得範圍在約80
μm與100μm之間的細的指狀引線接合墊間距,且因為兩列的該指狀引線係交錯的,所以組合的有效指狀引線接合墊間距係大小如同每一列的一半,其可提供具有範圍小到約40μm與約50μm的墊間距的晶粒的正交線接合互連,而短到1mm或更短的線長度是可能的。
第11A至11D圖係說明用以製造線接合互連的一般製程的階段。第11圖係顯示提供使用貼晶黏著劑13而裝到基板12的貼晶側上的晶粒22的階段。電性互連墊22係位於該晶粒的主動側。在基板上圖案化金屬層以形成具有狹窄接合部62的指狀引線。使用線接合設備,藉由栓凸塊程序以在該指狀引線62的接合部上形成球72,如第11B圖所示。該球之後藉由整平來平坦化以在該指狀引線上的該接合部形成支撐腳座72,如第11C圖所示。該球接合24係形成在晶粒墊22上,線26拉到指狀引線62上的該接合部,而針法接合74係形成在支撐腳座72上。
第12A圖(先前技術)係說明傳統針法接合的側視圖。在指狀引線213上形成銅(Cu)層212。藉由電鍍製程以在Cu層212上形成鎳(Ni)層214。藉由電鍍以在Ni層214上形成金(Au)層216。金線接合218係連接到Au層216以在該晶粒接合墊和指狀引線213之間造成該電性接觸。第12B圖(先前技術)係顯示該針法接合的剖視圖。該Cu層212、Ni層214、和Au層216係藉由電鍍以形成在該相鄰層上,而每層都使得接觸至指狀引線213。該傳統線接合係需要在該Cu層上電解電鍍Ni和Au以形成該針法接
合。或者,該針法接合在該Cu層上使用另一同性質表面塗層的銀(Ag)或鈀(Pd)。
上述的針法接合需要額外的製造步驟以在該Cu層上鍍有該Ni層、或其他同性質表面塗層的銀(Ag)或鈀(Pd)以提供可線接合的表面。該針法接合需要用在該電鍍製程中的鍍膜槽,其之後必須被移除。該Ni層因為電鍍該側壁及形成從該電鍍槽中餘留的栓(stud)而增加了該指狀接合墊間距。想要消除來自該線接合製程的鎳-金電解電鍍以及該電鍍槽以減少製造步驟、空間需要、接合指狀墊間距、與寄生效應(parasitic effect)。
在第13圖中,半導體裝置230係顯示在半導體晶粒232和接合指狀墊234之間具有線接合電性互連236。接合指狀墊234是由銅所製成的。線接合236造成在半導體晶粒232上的主動裝置和接合指狀墊234之間的電性連接。半導體晶粒232使用貼晶黏著劑以裝在基板238的表面。第一互連墊240係形成在該晶粒232的主動裝置側上。第二互連墊242係形成在接合指狀墊234上。線接合236提供在墊240至242之間的電性連接。接合指狀墊234經由導電穿孔(via)244以電性連接焊料球(solder ball)248。半導體晶粒232也可經由導電穿孔246以電性連接焊料球248。
互連墊242的進一步細節係顯示在第14A和14B圖中。在第14A圖中,銅層250形成在接合指狀墊234上。金針法接合栓252之後直接連接裸銅層250,不需要中間電鍍層或其他處理以提供可接合的接合指狀墊234表面。
或者,針法接合栓252可直接連接至浸金層或玻璃鈍化塗層(glass passivation coating)。第14B圖說明直接連接至形成在接合指狀墊234上的銅層250的針法接合栓252的側視圖。
雖然接合到裸銅層250是較佳實施例,但有些情況中雖然不是藉由電鍍而針對接合指狀墊234加入非常薄的保護表面塗層仍是個選項。該保護表面塗層係可為錫(Sn)、金、鎳、鈀、或其組合,其藉由無電鍍或浸製程來沉積,仍然避免使用電鍍槽。該保護表面塗層也可為氧化層,其沉積薄膜或生長在該銅表面上。舉例來說,該氧化物可為黑氧化物或銦錫氧化物(indium tin oxide,簡稱ITO)。該保護表面塗層的厚度在0.005至0.05微米(micron)之間。
然而,在銅層250上直接施用針法接合栓252仍是最佳解決方案且消除在該基板上的該電鍍連接桿,其解放用在路由(routing)的真實財產且避免來自該連接桿的電性寄生作用且減少用以線接合的有效接合指狀墊間距,這可導致較短的線與較小的封裝尺寸。在此揭露的該接合製程將密度最大化、將最終接合指狀墊間距最小化、與減少製造成本。該技術對於疊片基板(laminate substrate)更為有用;然而,也可應用在引線框架(leadframe),其中,可消除選擇性Ag電鍍步驟。
雖然已經詳細說明本發明的一個或更多個實施例,該技術領域中熟習技術者將理解到可在沒有脫離如下述申請專利範圍中所提出的本發明的範疇下對那些實施例作出修
改與改編。
12、112、238‧‧‧基板
13‧‧‧貼晶黏著劑
14、232‧‧‧半導體晶粒
15‧‧‧邊緣
22‧‧‧互連墊
24‧‧‧壓縮球
26‧‧‧線
32、62、62’、234‧‧‧接合指狀墊
34‧‧‧壓扁的線端
35‧‧‧區域
54、75‧‧‧針法接合
56、72、72’、82、172‧‧‧腳座
63、213‧‧‧指狀引線
64‧‧‧部分
65‧‧‧斷裂線
66、166‧‧‧第二線端
71、171‧‧‧上端
73‧‧‧底邊
74、174‧‧‧線端
75‧‧‧區域
77、79‧‧‧頂端
WP、WB、WF‧‧‧寬度
PDP、PLF、PDP’、PLF’、PLF”‧‧‧間距
212、250‧‧‧銅層
214‧‧‧鎳層
216‧‧‧金層
218‧‧‧金線接合
230‧‧‧半導體裝置
236‧‧‧電性互連
240‧‧‧第一互連墊
242‧‧‧第二互連墊
244、246‧‧‧導電穿孔
248‧‧‧焊料球
252‧‧‧接合栓
第1圖(先前技術)係說明固定到基板的半導體晶粒,其在該晶粒和基板之間具有已知正向線接合互連;第2A圖(先前技術)係說明如在第1圖(先前技術)中的傳統正向線接合互連,其顯示到該晶粒上之墊的該線的第一接合;第2B圖(先前技術)係說明如在第2A圖(先前技術)中的傳統第一接合;第3A圖(先前技術)係說明如在第1圖(先前技術)中的傳統正向線接合互連,其顯示到該基板上之接合指狀墊的該線的第二接合;第3B圖(先前技術)係說明如在第3A圖(先前技術)中的傳統第二接合;第4圖(先前技術)係說明固定到基板的半導體晶粒,其在該晶粒和基板之間具有已知反向線接合互連;第5圖(先前技術)係說明在該晶粒墊之球上的該線的傳統第二接合;第6A圖係說明如在第1圖(先前技術)中的正向線接合互連,其顯示該線適當地對準第二接合到該基板上的狹窄接合指狀墊;第6B圖係說明如在第1圖(先前技術)中的正向線接合互連,其顯示該線不良地對準第二接合到該基板上的狹窄接合指狀墊;
第7A圖係說明正向線接合互連到狹窄接合指狀墊,其顯示該線的第二接合到該基板上的狹窄接合指狀墊上的腳座;第7B圖係說明如在第7A圖中的該第二接合;第7C圖係說明如沿著在第7A、7B圖中7C-7C處的該第二接合的剖視圖;第7D至7E圖係說明不同的狹窄接合指狀墊組構的剖視圖;第8圖係說明該第二接合的剖視圖;第9A至9B圖係說明晶粒高密度互連至基板;第10A至10B圖係說明晶粒高密度互連至階梯基板;第11A至11D圖係說明形成具有基板的晶粒的第一和第二互連的步驟的剖視圖;第12A和12B圖(先前技術)係說明具有中間銅、鎳和金層的指狀引線的傳統線接合的側視和剖視圖;第13圖係說明半導體晶粒固定到基板的半導體封裝件,其在該晶粒和基板之間具有線接合互連;以及第14A至14B圖係說明線接合至具有直接物理接觸銅層之金層的指狀引線的側視和剖視圖。
12、112‧‧‧基板
14‧‧‧半導體晶粒
66、166‧‧‧第二線端
71、171‧‧‧上端
72、172‧‧‧腳座
74、174‧‧‧線端
PDP’、PLF”‧‧‧間距
Claims (9)
- 一種半導體封裝件,包括:基板;半導體晶粒,係配置在該基板上;以及接合線,係連接在該半導體晶粒上的第一接合部與該基板上的第二接合部之間,該第二接合部包含:(a)接合指狀墊,係形成在該基板上,(b)裸銅層,係直接物理接觸該接合指狀墊,以及(c)接合栓,係耦接至該接合線且直接物理接觸該裸銅層以從該半導體晶粒傳導電性訊號到該接合指狀墊。
- 如申請專利範圍第1項所述之半導體封裝件,其中,該接合指狀墊係由銅所製成。
- 如申請專利範圍第1項所述之半導體封裝件,其中,該接合栓係由金所製成。
- 如申請專利範圍第1項所述之半導體封裝件,其中,該接合栓係覆蓋該裸銅層的側面部分和頂部部分。
- 如申請專利範圍第1項所述之半導體封裝件,其中,該第一接合部係包含晶粒接合墊。
- 如申請專利範圍第1項所述之半導體封裝件,其中,該第二接合部係包含針法接合。
- 一種製造半導體封裝件的方法,包括:形成基板; 在該基板上配置半導體晶粒;以及在該半導體晶粒上的第一接合部與該基板上的第二接合部之間連接接合線,其連接方式為:(a)在該基板上形成接合指狀墊,(b)形成直接物理接觸該接合指狀墊的裸銅層,以及(c)形成接合栓,其耦接至該接合線並直接物理接觸該裸銅層以將電氣訊號從該半導體晶粒傳導到該接合指狀墊。
- 如申請專利範圍第7項所述之方法,其中,該裸銅層係接觸玻璃鈍化塗層。
- 如申請專利範圍第7項所述之方法,其中,該裸銅層係接觸浸金層。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/839,020 US7868468B2 (en) | 2004-11-12 | 2007-08-15 | Wire bonding structure and method that eliminates special wire bondable finish and reduces bonding pitch on substrates |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200913102A TW200913102A (en) | 2009-03-16 |
TWI480964B true TWI480964B (zh) | 2015-04-11 |
Family
ID=40707882
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW097129182A TWI480964B (zh) | 2007-08-15 | 2008-08-01 | 線接合結構以及消除特殊線接合加工與縮減基板上之接合間距的方法 |
Country Status (3)
Country | Link |
---|---|
US (2) | US7868468B2 (zh) |
KR (1) | KR101496997B1 (zh) |
TW (1) | TWI480964B (zh) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090045061A1 (en) * | 2007-06-20 | 2009-02-19 | New Jersey Institute Of Technology | Nanotube Devices and Vertical Field Effect Transistors |
EP2133915A1 (de) * | 2008-06-09 | 2009-12-16 | Micronas GmbH | Halbleiteranordnung mit besonders gestalteten Bondleitungen und Verfahren zum Herstellen einer solchen Anordnung |
US8362601B2 (en) * | 2008-12-04 | 2013-01-29 | Stats Chippac Ltd | Wire-on-lead package system having leadfingers positioned between paddle extensions and method of manufacture thereof |
EP2444999A4 (en) * | 2009-06-18 | 2012-11-14 | Rohm Co Ltd | SEMICONDUCTOR DEVICE |
US8402406B2 (en) | 2010-12-28 | 2013-03-19 | International Business Machines Corporation | Controlling plating stub reflections in a chip package |
US11373974B2 (en) * | 2016-07-01 | 2022-06-28 | Intel Corporation | Electronic device packages and methods for maximizing electrical current to dies and minimizing bond finger size |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060113665A1 (en) * | 2004-11-12 | 2006-06-01 | Chippac, Inc | Wire bond interconnection |
TW200627584A (en) * | 2005-01-31 | 2006-08-01 | Taiwan Semiconductor Mfg Co Ltd | Novel method for copper wafer wire bonding |
Family Cites Families (62)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5933894A (ja) * | 1982-08-19 | 1984-02-23 | 電気化学工業株式会社 | 混成集積用回路基板の製造法 |
US4742023A (en) * | 1986-08-28 | 1988-05-03 | Fujitsu Limited | Method for producing a semiconductor device |
US5007576A (en) * | 1989-12-26 | 1991-04-16 | Hughes Aircraft Company | Testable ribbon bonding method and wedge bonding tool for microcircuit device fabrication |
JP2601666Y2 (ja) * | 1992-05-08 | 1999-11-29 | 株式会社村田製作所 | 積層型コイル |
US5340772A (en) * | 1992-07-17 | 1994-08-23 | Lsi Logic Corporation | Method of increasing the layout efficiency of dies on a wafer and increasing the ratio of I/O area to active area per die |
US5340770A (en) * | 1992-10-23 | 1994-08-23 | Ncr Corporation | Method of making a shallow junction by using first and second SOG layers |
US5328079A (en) * | 1993-03-19 | 1994-07-12 | National Semiconductor Corporation | Method of and arrangement for bond wire connecting together certain integrated circuit components |
US5561086A (en) * | 1993-06-18 | 1996-10-01 | Lsi Logic Corporation | Techniques for mounting semiconductor dies in die-receiving areas having support structure having notches |
US5480834A (en) * | 1993-12-13 | 1996-01-02 | Micron Communications, Inc. | Process of manufacturing an electrical bonding interconnect having a metal bond pad portion and having a conductive epoxy portion comprising an oxide reducing agent |
KR0130534B1 (ko) * | 1994-07-12 | 1998-04-09 | 김광호 | 세탁기용 리니어 모터 |
US5444303A (en) * | 1994-08-10 | 1995-08-22 | Motorola, Inc. | Wire bond pad arrangement having improved pad density |
JPH08102517A (ja) * | 1994-09-30 | 1996-04-16 | Nec Corp | 半導体装置及びリードフレーム |
US5465899A (en) * | 1994-10-14 | 1995-11-14 | Texas Instruments Incorporated | Method and apparatus for fine pitch wire bonding using a shaved capillary |
US5994169A (en) * | 1994-10-27 | 1999-11-30 | Texas Instruments Incorporated | Lead frame for integrated circuits and process of packaging |
US5842628A (en) * | 1995-04-10 | 1998-12-01 | Fujitsu Limited | Wire bonding method, semiconductor device, capillary for wire bonding and ball bump forming method |
JPH0982742A (ja) | 1995-09-11 | 1997-03-28 | Fujitsu Ltd | ワイヤボンディング方法 |
US5686762A (en) * | 1995-12-21 | 1997-11-11 | Micron Technology, Inc. | Semiconductor device with improved bond pads |
US5734559A (en) * | 1996-03-29 | 1998-03-31 | Intel Corporation | Staggered bond finger design for fine pitch integrated circuit packages |
US5904288A (en) * | 1996-04-08 | 1999-05-18 | Texas Instruments Incorporated | Wire bond clamping method |
US6001671A (en) * | 1996-04-18 | 1999-12-14 | Tessera, Inc. | Methods for manufacturing a semiconductor package having a sacrificial layer |
US5735030A (en) * | 1996-06-04 | 1998-04-07 | Texas Instruments Incorporated | Low loop wire bonding |
US5976964A (en) * | 1997-04-22 | 1999-11-02 | Micron Technology, Inc. | Method of improving interconnect of semiconductor device by utilizing a flattened ball bond |
JP3022819B2 (ja) * | 1997-08-27 | 2000-03-21 | 日本電気アイシーマイコンシステム株式会社 | 半導体集積回路装置 |
EP0903780A3 (en) * | 1997-09-19 | 1999-08-25 | Texas Instruments Incorporated | Method and apparatus for a wire bonded package for integrated circuits |
US5960262A (en) * | 1997-09-26 | 1999-09-28 | Texas Instruments Incorporated | Stitch bond enhancement for hard-to-bond materials |
US6008532A (en) * | 1997-10-23 | 1999-12-28 | Lsi Logic Corporation | Integrated circuit package having bond fingers with alternate bonding areas |
US6046075A (en) * | 1997-12-23 | 2000-04-04 | Vlsi Technology, Inc. | Oxide wire bond insulation in semiconductor assemblies |
US6064113A (en) * | 1998-01-13 | 2000-05-16 | Lsi Logic Corporation | Semiconductor device package including a substrate having bonding fingers within an electrically conductive ring surrounding a die area and a combined power and ground plane to stabilize signal path impedances |
JPH11312749A (ja) * | 1998-02-25 | 1999-11-09 | Fujitsu Ltd | 半導体装置及びその製造方法及びリードフレームの製造方法 |
US6158647A (en) * | 1998-09-29 | 2000-12-12 | Micron Technology, Inc. | Concave face wire bond capillary |
TW410446B (en) * | 1999-01-21 | 2000-11-01 | Siliconware Precision Industries Co Ltd | BGA semiconductor package |
US6462414B1 (en) * | 1999-03-05 | 2002-10-08 | Altera Corporation | Integrated circuit package utilizing a conductive structure for interlocking a conductive ball to a ball pad |
US6329278B1 (en) * | 2000-01-03 | 2001-12-11 | Lsi Logic Corporation | Multiple row wire bonding with ball bonds of outer bond pads bonded on the leads |
JP2001338955A (ja) * | 2000-05-29 | 2001-12-07 | Texas Instr Japan Ltd | 半導体装置及びその製造方法 |
US6333562B1 (en) * | 2000-07-13 | 2001-12-25 | Advanced Semiconductor Engineering, Inc. | Multichip module having stacked chip arrangement |
US6972484B2 (en) * | 2000-10-13 | 2005-12-06 | Texas Instruments Incorporated | Circuit structure integrating the power distribution functions of circuits and leadframes into the chip surface |
JP2002198374A (ja) * | 2000-10-16 | 2002-07-12 | Sharp Corp | 半導体装置およびその製造方法 |
US7135759B2 (en) * | 2000-10-27 | 2006-11-14 | Texas Instruments Incorporated | Individualized low parasitic power distribution lines deposited over active integrated circuits |
US6597065B1 (en) * | 2000-11-03 | 2003-07-22 | Texas Instruments Incorporated | Thermally enhanced semiconductor chip having integrated bonds over active circuits |
TW465064B (en) * | 2000-12-22 | 2001-11-21 | Advanced Semiconductor Eng | Bonding process and the structure thereof |
JP2002368176A (ja) * | 2001-06-11 | 2002-12-20 | Rohm Co Ltd | 半導体電子部品のリードフレーム |
TW495940B (en) * | 2001-07-20 | 2002-07-21 | Via Tech Inc | Method for forming a grid array packaged integrated circuit |
US6787926B2 (en) * | 2001-09-05 | 2004-09-07 | Taiwan Semiconductor Manufacturing Co., Ltd | Wire stitch bond on an integrated circuit bond pad and method of making the same |
US6762122B2 (en) * | 2001-09-27 | 2004-07-13 | Unitivie International Limited | Methods of forming metallurgy structures for wire and solder bonding |
KR100396787B1 (ko) * | 2001-11-13 | 2003-09-02 | 엘지전자 주식회사 | 반도체 패키지용 인쇄회로기판의 와이어 본딩패드 형성방법 |
US7190060B1 (en) * | 2002-01-09 | 2007-03-13 | Bridge Semiconductor Corporation | Three-dimensional stacked semiconductor package device with bent and flat leads and method of making same |
JP3824545B2 (ja) | 2002-02-07 | 2006-09-20 | 松下電器産業株式会社 | 配線基板、それを用いた半導体装置、それらの製造方法 |
US7229906B2 (en) * | 2002-09-19 | 2007-06-12 | Kulicke And Soffa Industries, Inc. | Method and apparatus for forming bumps for semiconductor interconnections using a wire bonding machine |
US6731000B1 (en) | 2002-11-12 | 2004-05-04 | Koninklijke Philips Electronics N.V. | Folded-flex bondwire-less multichip power package |
US6815836B2 (en) * | 2003-03-24 | 2004-11-09 | Texas Instruments Incorporated | Wire bonding for thin semiconductor package |
US6927479B2 (en) * | 2003-06-25 | 2005-08-09 | St Assembly Test Services Ltd | Method of manufacturing a semiconductor package for a die larger than a die pad |
US6956286B2 (en) * | 2003-08-05 | 2005-10-18 | International Business Machines Corporation | Integrated circuit package with overlapping bond fingers |
US7005752B2 (en) * | 2003-10-20 | 2006-02-28 | Texas Instruments Incorporated | Direct bumping on integrated circuit contacts enabled by metal-to-insulator adhesion |
US20050133928A1 (en) * | 2003-12-19 | 2005-06-23 | Howard Gregory E. | Wire loop grid array package |
US7375978B2 (en) * | 2003-12-23 | 2008-05-20 | Intel Corporation | Method and apparatus for trace shielding and routing on a substrate |
TWI304238B (en) * | 2004-09-07 | 2008-12-11 | Advanced Semiconductor Eng | Wire-bonding method for connecting wire-bond pads and chip and the structure formed thereby |
US7731078B2 (en) * | 2004-11-13 | 2010-06-08 | Stats Chippac Ltd. | Semiconductor system with fine pitch lead fingers |
JP2007035863A (ja) * | 2005-07-26 | 2007-02-08 | Toshiba Corp | 半導体装置 |
US8399989B2 (en) * | 2005-07-29 | 2013-03-19 | Megica Corporation | Metal pad or metal bump over pad exposed by passivation layer |
US8421227B2 (en) * | 2006-06-28 | 2013-04-16 | Megica Corporation | Semiconductor chip structure |
US7582966B2 (en) * | 2006-09-06 | 2009-09-01 | Megica Corporation | Semiconductor chip and method for fabricating the same |
TWI368286B (en) * | 2007-08-27 | 2012-07-11 | Megica Corp | Chip assembly |
-
2007
- 2007-08-15 US US11/839,020 patent/US7868468B2/en active Active
-
2008
- 2008-08-01 TW TW097129182A patent/TWI480964B/zh active
- 2008-08-18 KR KR20080080590A patent/KR101496997B1/ko active IP Right Grant
-
2010
- 2010-12-20 US US12/973,410 patent/US8269356B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060113665A1 (en) * | 2004-11-12 | 2006-06-01 | Chippac, Inc | Wire bond interconnection |
TW200627584A (en) * | 2005-01-31 | 2006-08-01 | Taiwan Semiconductor Mfg Co Ltd | Novel method for copper wafer wire bonding |
Also Published As
Publication number | Publication date |
---|---|
US20070273043A1 (en) | 2007-11-29 |
TW200913102A (en) | 2009-03-16 |
US20110089566A1 (en) | 2011-04-21 |
KR101496997B1 (ko) | 2015-02-27 |
KR20090018014A (ko) | 2009-02-19 |
US7868468B2 (en) | 2011-01-11 |
US8269356B2 (en) | 2012-09-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7453156B2 (en) | Wire bond interconnection | |
TWI480964B (zh) | 線接合結構以及消除特殊線接合加工與縮減基板上之接合間距的方法 | |
JP3133341B2 (ja) | 半導体ダイのための接触ピンおよび相互接続部を形成する方法 | |
US20090289360A1 (en) | Workpiece contact pads with elevated ring for restricting horizontal movement of terminals of ic during pressing | |
JP6073529B2 (ja) | ボンドワイヤの基板外キンク形成 | |
JP2000036511A (ja) | 電子部品の製造方法 | |
JP2010251483A (ja) | 半導体装置およびその製造方法 | |
JPH02503616A (ja) | 金の圧縮接着 | |
JP2004336062A (ja) | より大きな基板にばね接触子を定置させるための接触子担体(タイル) | |
JP2009076851A (ja) | 実装基板構造物及びその製造方法 | |
JP2006253289A (ja) | 電子回路およびその製造方法 | |
TWI453844B (zh) | 四方平面無導腳半導體封裝件及其製法 | |
TW201146107A (en) | Substrate layout and method for forming the same | |
JP2003508898A (ja) | マイクロビームアセンブリおよび集積回路と基板との内部連結方法 | |
JP2010118534A (ja) | 半導体装置およびその製造方法 | |
TWI254390B (en) | Packaging method and structure thereof | |
JP2010123817A (ja) | ワイヤボンディング方法および電子装置とその製造方法 | |
TWI496250B (zh) | 封裝基板及其製法 | |
TWI440108B (zh) | 形成一致銲線轉折角之打線方法 | |
JP6762871B2 (ja) | 平坦化によってはんだパッド形態差を低減する方法 | |
TWI478221B (zh) | Semiconductor device manufacturing method and bonding device | |
TWI816255B (zh) | 打線結構、打線結構形成方法以及電子裝置 | |
JP3675374B2 (ja) | 半導体装置 | |
JP2010056349A (ja) | 半導体素子、半導体素子製造装置用ツールおよび半導体素子の製造方法 | |
JP2009076767A (ja) | 半導体装置の製造方法及びワイヤボンディング装置 |