TWI470701B - 用於半導體元件之超接面結構及其製程 - Google Patents

用於半導體元件之超接面結構及其製程 Download PDF

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TWI470701B
TWI470701B TW101147146A TW101147146A TWI470701B TW I470701 B TWI470701 B TW I470701B TW 101147146 A TW101147146 A TW 101147146A TW 101147146 A TW101147146 A TW 101147146A TW I470701 B TWI470701 B TW I470701B
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conductivity type
layer
super junction
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mask layer
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TW201423868A (zh
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Chung Chen Paul Chang
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Pfc Device Holdings Ltd
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Description

用於半導體元件之超接面結構及其製程
本發明係為一種半導體結構及其製程，尤指一種半導體元件之超接面結構及其製程。
自陳星弼博士於1991年(例如可參見美國專利第5,216,275號)提出超接面(super junction)之概念之後，已經有許多研究企圖發展並增進上述發明的超接面效果。
例如美國專利第6,608,350即提出一種溝槽型超接面裝置，參見第一圖，為說明此專利溝槽型超接面裝置概念之示意圖，此溝槽型超接面MOS裝置主要包含一基板81、一N型磊晶層82、複數之平行溝槽83、位在平行溝槽83側壁上之P型層84、位在N型磊晶層82上之P基底(base)93、在兩個平行溝槽83之間及在N型磊晶層82上之閘極氧化層87及閘極88、位在P基底93上之源極區89及源極電極91，及在P型層84內之介電質(未加圖號)。在導通模式時，在閘極88上施加一偏壓，而源極電極89係為接地。此時於P基底93及閘極氧化層87之間會形成一通道(channel)，在渠極上施加小偏壓時即可在此元件中產生電流，且在溝槽83中的P型層84可提供低的導通電阻RDSON。在習知的MOS裝置之中，如要降低導通電阻RDSON，則必須降低N型磊晶層82之電阻係數，亦即要增加 摻雜濃度。然而若N型磊晶層82之摻雜濃度增加，則會影響此MOS元件之耐壓性能。
藉由上述之超接面結構，即可兼具高耐壓能力及低導通電阻。然而要在N型磊晶層82上形成具有高深寬比之溝槽83並不容易，因此若能提供一種新的半導體元件超接面結構及其製程，以改善習知技術缺點，即非常有利於超接面裝置之製作。
為了克服習知技術問題，本發明之一目的為提供一種可進一步提高反向耐壓且可製作高深寬比之用於半導體元件之超接面結構及其製程。
為了達成本發明目的，本發明提供一種用於半導體元件之超接面結構製程，包含：(a)提供一矽基板，並於該矽基板上形成一第一導電型磊晶層；(b)於該第一導電型磊晶層上塗布光阻，以製作一罩幕層圖案，並移除裸露之罩幕層；(c)利用該光阻層圖案作為罩幕，佈植一高濃度第二導電型離子佈植於罩幕層被移除之第一導電型磊晶層上；(d)移除該光阻層下之部分罩幕層周緣部份，使部分光阻層懸空；(e)去除光阻層，利用剩餘之該罩幕層作為罩幕，佈植一低濃度第二導電型離子佈植於未被罩幕層覆蓋之第一導電型磊晶層上；(f)移除該剩餘之罩幕層及在所得結構上形成一第一導電型磊晶覆蓋層；(g)重複上述步驟(b)至(f)，以形成複數之高濃度第二導電型離子層及複數之低濃度第二導電型離子層；及(h)在所得結構上形成一場氧化層及進行熱驅入，以使各層之高濃度第二導電型離子層及低濃度第二導電型離子層連接在一起，在第一導電型磊晶層中形成高濃度第二導電型柱及 低濃度第二導電型側壁。
為了達成本發明目的，本發明提供一種用於半導體元件之超接面結構，包含：一矽基板，該矽基板上具有一第一導電型磊晶層；複數之高濃度第二導電型柱，形成於該第一導電型磊晶層內；及複數之低濃度第二導電型側壁，形成於該第一導電型磊晶層內且位於該高濃度第二導電型柱之外側面上。
上述之半導體元件為超接面MOSFET、超接面MESFET、超接面Schottky電晶體、超接面IGBT、閘流體(thyristor)、或超接面二極體。
[習知]
81‧‧‧基板
82‧‧‧N型磊晶層
83‧‧‧平行溝槽
84‧‧‧P型層
87‧‧‧閘極氧化層
88‧‧‧閘極
89‧‧‧源極區
91‧‧‧源極電極
93‧‧‧P基底
[本發明]
20‧‧‧基板
201‧‧‧高掺雜濃度N型矽基板
202‧‧‧低掺雜濃度N型磊晶層
203‧‧‧低掺雜濃度P型磊晶層
210‧‧‧第一光阻層
211‧‧‧外側光阻
212‧‧‧中心點光阻
220‧‧‧罩幕層
221‧‧‧外側罩幕層
222‧‧‧中心點罩幕層
223‧‧‧缺口
30‧‧‧高濃度P型離子佈植區
32‧‧‧低濃度P型離子佈植區
34‧‧‧高濃度P型柱
36‧‧‧低濃度P型側壁
40‧‧‧高濃度N型離子佈植區
42‧‧‧低濃度N型離子佈植區
44‧‧‧高濃度N型柱
46‧‧‧低濃度N型側壁
60‧‧‧場氧化層
本案得藉由下列圖式及說明，俾得一更深入之了解：第一圖為習知技術之溝槽型超接面裝置側視圖。
第二A圖至第二D圖為說明本發明第一實施例之上視圖。
第三A圖至第三F圖為說明本發明第一實施例之側視圖。
第四A圖至第四D圖為說明本發明第二實施例之上視圖。
第五A圖至第五F圖為說明本發明第二實施例之側視圖。
第六A圖至第六D圖為說明本發明第三實施例之上視圖。
第七A圖至第七F圖為說明本發明第三實施例之側視圖。
請參閱第二A圖及第三A圖，其係為說明本案用於半導體元件之超接面製程之第一較佳具體實例步驟上視圖及側視圖。如第三A圖 所示，首先，提供一基板20，該基板20係為一高掺雜濃度N型矽基板201(N+矽基板)與一低掺雜濃度N型磊晶層202(N-磊晶層)所構成。於此圖中所繪示的低掺雜濃度N型磊晶層202與較高掺雜濃度N型矽基板201有近似厚度，但是須知此圖僅為示意說明本發明之具體實例，於實際之元件中，低掺雜濃度N型磊晶層202在實際上應比較高掺雜濃度N型矽基板201來的薄。隨後透過一氧化製程於該基板20上形成一罩幕層(未標號，例如一場氧化層)；然後於該第一罩幕層上以光阻佈形步驟形成一第一光阻層210。復參見第二A圖及第三A圖所示，該第一光阻層210包含外側光阻層211及中心點光阻層212，以在外側光阻層211及中心點光阻層212之間界定出環形溝槽(未標號)。在此須知第二A圖及第三A圖所示之溝槽僅為範例，任何封閉形狀之溝槽(例如四邊形及橢圓形)皆可達成本案之功效。隨後以此第一光阻層210為罩幕以對於該罩幕層蝕刻，以形成如第三A圖所示之罩幕層220(包含外側罩幕層221及中心點罩幕層222)。隨後在所得結構上以該些光阻層211,212作為作為罩幕進行高濃度P型離子佈植，例如可以植入濃度為1013cm-3之硼離子於低掺雜濃度N型磊晶層202之上，即形成如第三A圖所示之結構，其中該結構具有高濃度P型離子佈植區30。
隨後如第三B圖所示，利用第一光阻層210作為罩幕，對於其下之罩幕層220進行等向性蝕刻(isotropic etching)，例如可以用緩衝氧化物蝕刻劑(buffered oxide etchant,BOE)對於為場氧化層之罩幕層220進行等向性蝕刻，以將罩幕層220向內推而形成缺口223，亦即移除該光阻層210下之部份罩幕層220周緣部份，使 部份光阻層210懸空。
隨後如第三C圖所示，在去除第一光阻層210之後，即可利用再一次之BOE製程，且控制蝕刻速率，以將中心點罩幕層222移除。此時，如第二C圖所示，在所得結構之表面上留下者為罩幕層220(其僅包含外側罩幕層221)。
隨後如第三D圖所示，在所得結構上以該罩幕層220為罩幕進行低濃度之P型離子佈植，且控制離子佈植深度，以在高濃度P型離子佈植區30之旁形成低濃度P型離子佈植區32，隨後移除剩餘之罩幕層220，並於所得結構上再磊晶成長一低掺雜濃度N型磊晶層覆蓋層(未圖式)。
隨後如第三E圖所示，可在反覆進行上述步驟之後(例如進行如第三A圖到第三D圖所示步驟六次)，即可形成如圖示之多層高濃度P型離子佈植區30及低濃度P型離子佈植區32結構。
隨後如第三F圖所示，在所得結構上形成一場氧化層60，及進行離子驅入步驟(drive in)，以使上下層之P型離子佈植區30及低濃度P型離子佈植區32分別上下連接在一起，以形成如此圖所示之高濃度P型柱34及低濃度P型側壁36，即可以此結構為基礎，製作後續之半導體元件，如超接面MOSFET、超接面MESFET、超接面Schottky電晶體、超接面IGBT、閘流體(thyristor)、及超接面二極體。
再者，如第三F圖所示，由於高濃度P型柱34可由低濃度P型側壁36作為與低掺雜濃度N型磊晶層202之間的緩衝層，因此可以進一步提高所製成元件之反向耐壓。
如第四A圖及第五A圖所示，為說明本案用於半導體元件之超接面製程之第二較佳具體實例步驟上視圖及側視圖。如第五A圖所示，首先，提供一基板20，該基板20係為一高掺雜濃度N型矽基板201(N+矽基板)與一低掺雜濃度N型磊晶層202(N-磊晶層)所構成。隨後透過一氧化製程於該基板20上形成一罩幕層(未標號，例如一場氧化層)；然後於該第一罩幕層上以光阻佈形步驟形成一第一光阻層210。復參見第四A圖及第五A圖所示，該第一光阻層210界定出一圓形空心溝槽(未標號)。
在此須知第四A圖及第五A圖所示之溝槽僅為範例，任何封閉形狀之溝槽(例如四邊形及橢圓形)皆可達成本案之功效。隨後以此第一光阻層210之為罩幕以對於該第一罩幕層蝕刻，以形成如第五A圖所示之罩幕層220。隨後在所得結構上以該光阻層210作為作為罩幕進行高濃度P型離子佈植，例如可以植入濃度為1013cm-3之硼離子於低掺雜濃度N型磊晶層202之上，即形成如第五A圖所示之結構，其中該結構具有高濃度P型離子佈植區30。
隨後如第四B圖及第五B圖所示，利用第一光阻層210作為罩幕，對於其下之罩幕層220進行等向性蝕刻(isotropic etching)，例如可以用緩衝氧化物蝕刻劑(buffered oxide etchant,BOE)對於為場氧化層之罩幕層220進行等向性蝕刻，以將罩幕層220向內推而形成缺口223，亦即移除該光阻層210下之部份罩幕層220周緣部份，使部份光阻層210懸空。
隨後如第四C及第五C圖所示，在去除第一光阻層210之後，即再一次進行BOE製程，以去除罩幕層220表面雜質，此時所得結構之上表面為罩幕層220。
隨後如第五D圖所示，在所得結構上以罩幕層220為罩幕進行低濃度之P型離子佈植，且控制離子佈植深度，以在高濃度P型離子佈植區30之旁形成低濃度P型離子佈植區32，隨後移除剩餘之罩幕層220，並於所得結構上再磊晶成長一低掺雜濃度N型磊晶層覆蓋層(未圖式)。
隨後如第五E圖所示，可在反覆進行上述步驟之後(例如進行如第五A圖到第五D圖所示步驟六次)，即可形成如圖示之多層高濃度P型離子佈植區30及低濃度P型離子佈植區32結構。
隨後如第五F圖所示，在所得結構上形成一場氧化層60，及進行離子驅入步驟(drive in)，以使上下層之P型離子佈植區30及低濃度P型離子佈植區32分別上下連接在一起，以形成如此圖所示之高濃度P型柱34及低濃度P型側壁36，即可以此結構為基礎，製作後續之半導體元件，如超接面MOSFET、超接面MESFET、超接面Schottky電晶體、超接面IGBT、閘流體(thyristor)、及超接面二極體。
如第六A及第七A圖所示，為說明本案用於半導體元件之超接面製程之第三較佳具體實例步驟上視圖及側視圖。如第七A圖所示，首先，提供一基板20，該基板20係為一高掺雜濃度N型矽基板201(N+矽基板)與一低掺雜濃度N型磊晶層202(N-磊晶層)所構成。隨後進行一低掺雜濃度P型磊晶層製程，以在低掺雜濃度N型磊晶層202上形成一低掺雜濃度P型磊晶層203。隨後透過一氧化製程於該低掺雜濃度P型磊晶層203上形成一罩幕層(未標號，例如一場氧化層)；然後於該罩幕層上以光阻佈形步驟形成一第一光阻層210。復參見第六A圖所示，該第一光阻層210例如可為一圓 形圖案。在此須知第六A圖所示之第一光阻層210僅為範例，該第一光阻層210也可為其他封閉圖案(例如四邊形及橢圓形)皆可達成本案之功效。隨後以此第一光阻層210之為罩幕以對於該罩幕層蝕刻，以形成如第七A圖所示之罩幕層220。隨後在所得結構上以光阻層210為罩幕進行高濃度N型離子佈植，例如可以植入濃度為1013cm-3之磷離子於低掺雜濃度P型磊晶層203，即形成如第七A圖所示之結構，其中該結構具有高濃度N型離子佈植區40。
隨後如第七B圖所示，利用第一光阻層210作為罩幕，對於其下之罩幕層220進行等向性蝕刻(isotropic etching)，例如可以用緩衝氧化物蝕刻劑(buffered oxide etchant,BOE)對於為場氧化層之罩幕層220進行等向性蝕刻，以將罩幕層220向內推而形成缺口223，亦即移除該光阻層210下之部份罩幕層220周緣部份，使部份光阻層懸空。
隨後如第七C圖所示，在去除第一光阻層210之後，即再一次進行BOE製程，以去除罩幕層220表面雜質，此時所得結構之上表面為罩幕層220。
隨後如第七D圖所示，在所得結構上以罩幕層220為罩幕進行低濃度之N型離子佈植，且控制離子佈植深度，以在高濃度N型離子佈植區40之旁形成低濃度N型離子佈植區42，隨後移除剩餘之第一罩幕層220，並於所得結構上再磊晶成長一低掺雜濃度P型磊晶層覆蓋層(未圖式)。
隨後如第七E圖所示，可在反覆進行上述步驟之後(例如進行如第七A圖到第七D圖所示步驟六次)，即可形成如圖示之多層高濃 度N型離子佈植區40及低濃度N型離子佈植區42結構。
隨後如第七F圖所示，在所得結構上形成一場氧化層60，及進行離子驅入步驟(drive in)，以使上下層之N型離子佈植區40及低濃度N型離子佈植區42分別上下連接在一起，以形成如此圖所示之高濃度N型柱44及低濃度N型側壁46，即可以此結構為基礎，製作後續之半導體元件，如超接面MOSFET、超接面MESFET、超接面Schottky電晶體、超接面IGBT、閘流體(thyristor)、及超接面二極體。
綜上所述，雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
20‧‧‧基板
201‧‧‧高掺雜濃度N型矽基板
202‧‧‧低掺雜濃度N型磊晶層
34‧‧‧高濃度P型柱
36‧‧‧低濃度P型側壁
60‧‧‧場氧化層

Claims (12)

  1. 一種用於半導體元件之超接面結構製程，包含：(a)提供一矽基板，並於該矽基板上形成一第一導電型磊晶層；(b)於該第一導電型磊晶層上製作一罩幕層；(c)佈植一高濃度第二導電型離子於未被罩幕層覆蓋之第一導電型磊晶層上；(d)移除該罩幕層周緣部份；(e)佈植一低濃度第二導電型離子於未被罩幕層覆蓋之第一導電型磊晶層上；(f)移除該罩幕層及在所得結構上形成一第一導電型磊晶覆蓋層；(g)重複上述步驟(b)至(f)，以形成複數之高濃度第二導電型離子層及複數之低濃度第二導電型離子層；及(h)在所得結構上形成一場氧化層及進行熱驅入，以使各層之高濃度第二導電型離子層及低濃度第二導電型離子層連接在一起，在第一導電型磊晶層中形成高濃度第二導電型柱及低濃度第二導電型側壁。
  2. 如申請專利範圍第1項之用於半導體元件之超接面結構製程，其中第一導電型為N型，第二導電型為P型。
  3. 如申請專利範圍第2項之用於半導體元件之超接面結構製程，其中該罩幕層包含外側罩幕層及中心點罩幕層。
  4. 如申請專利範圍第3項之用於半導體元件之超接面結構製程，其 中在步驟(d)之後更包含：(d1)移除中心點罩幕層。
  5. 如申請專利範圍第2項之用於半導體元件之超接面結構製程，其中該罩幕層空心缺口圖案。
  6. 如申請專利範圍第1項之用於半導體元件之超接面結構製程，其中第一導電型為P型，第二導電型為N型。
  7. 如申請專利範圍第6項之用於半導體元件之超接面結構製程，其中該罩幕層為封閉圖形圖案。
  8. 如申請專利範圍第7項之用於半導體元件之超接面結構製程，其中該罩幕層為大體圓形圖案。
  9. 一種用於半導體元件之超接面結構，包含：一矽基板，該矽基板上具有一第一導電型磊晶層；複數之高濃度第二導電型柱，形成於該第一導電型磊晶層內；及複數之低濃度第二導電型側壁，形成於該第一導電型磊晶層內且位於該高濃度第二導電型柱之外側面上。
  10. 如申請專利範圍第9項之用於半導體元件之超接面結構，其中第一導電型為N型，第二導電型為P型。
  11. 如申請專利範圍第9項之用於半導體元件之超接面結構，其中第一導電型為P型，第二導電型為N型。
  12. 如申請專利範圍第9項之用於半導體元件之超接面結構，其中該半導體元件為超接面MOSFET、超接面MESFET、超接面Schottky電晶體、超接面IGBT、閘流體(thyristor)、或超接面二極體。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5216275A (en) * 1991-03-19 1993-06-01 University Of Electronic Science And Technology Of China Semiconductor power devices with alternating conductivity type high-voltage breakdown regions
US7858475B2 (en) * 2006-08-11 2010-12-28 Denso Corporation Method for manufacturing a vertical transistor that includes a super junction structure
TW201133853A (en) * 2009-10-30 2011-10-01 Alpha & Omega Semiconductor Staggered column superjunction
TWI358089B (en) * 2003-12-19 2012-02-11 Third Dimension 3D Semiconductor Inc Method of manufacturing a superjunction device
TW201207957A (en) * 2010-07-22 2012-02-16 Fairchild Semiconductor Trench superjunction MOSFET with thin EPI process

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4047384B2 (ja) 1996-02-05 2008-02-13 シーメンス アクチエンゲゼルシヤフト 電界効果により制御可能の半導体デバイス
JP2001119022A (ja) 1999-10-20 2001-04-27 Fuji Electric Co Ltd 半導体装置及びその製造方法
JP4765012B2 (ja) * 2000-02-09 2011-09-07 富士電機株式会社 半導体装置及びその製造方法
US6608350B2 (en) 2000-12-07 2003-08-19 International Rectifier Corporation High voltage vertical conduction superjunction semiconductor device
JP4785335B2 (ja) 2001-02-21 2011-10-05 三菱電機株式会社 半導体装置およびその製造方法
EP1696490A1 (en) * 2005-02-25 2006-08-30 STMicroelectronics S.r.l. Charge compensation semiconductor device and relative manufacturing process
JP4564510B2 (ja) * 2007-04-05 2010-10-20 株式会社東芝 電力用半導体素子
TWI381455B (zh) * 2008-04-22 2013-01-01 Pfc Device Co 金氧半ｐ－ｎ接面二極體結構及其製作方法
US8785306B2 (en) * 2011-09-27 2014-07-22 Alpha And Omega Semiconductor Incorporated Manufacturing methods for accurately aligned and self-balanced superjunction devices
US20140097491A1 (en) * 2012-10-05 2014-04-10 Texas Instruments Incorporated Dielectrically Terminated Superjunction FET

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5216275A (en) * 1991-03-19 1993-06-01 University Of Electronic Science And Technology Of China Semiconductor power devices with alternating conductivity type high-voltage breakdown regions
TWI358089B (en) * 2003-12-19 2012-02-11 Third Dimension 3D Semiconductor Inc Method of manufacturing a superjunction device
US7858475B2 (en) * 2006-08-11 2010-12-28 Denso Corporation Method for manufacturing a vertical transistor that includes a super junction structure
TW201133853A (en) * 2009-10-30 2011-10-01 Alpha & Omega Semiconductor Staggered column superjunction
TW201207957A (en) * 2010-07-22 2012-02-16 Fairchild Semiconductor Trench superjunction MOSFET with thin EPI process

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