TWI456574B - 低功率存取相位改變記憶體裝置之方法 - Google Patents

低功率存取相位改變記憶體裝置之方法 Download PDF

Info

Publication number
TWI456574B
TWI456574B TW098140395A TW98140395A TWI456574B TW I456574 B TWI456574 B TW I456574B TW 098140395 A TW098140395 A TW 098140395A TW 98140395 A TW98140395 A TW 98140395A TW I456574 B TWI456574 B TW I456574B
Authority
TW
Taiwan
Prior art keywords
group
bit line
selecting
bit
line
Prior art date
Application number
TW098140395A
Other languages
English (en)
Other versions
TW201027537A (en
Inventor
Claudio Resta
Ferdinando Bedeschi
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of TW201027537A publication Critical patent/TW201027537A/zh
Application granted granted Critical
Publication of TWI456574B publication Critical patent/TWI456574B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/02—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5678—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0078—Write using current through the cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)

Claims (13)

  1. 一種用於存取一相位改變記憶體裝置之方法，該方法包括：提供在複數個位元線及複數個字線之交點連接之複數個相位改變記憶體單元；將一第一子複數個位元線分組在一第一群組中且將一第二子複數個位元線分組在一第二群組中；在該等第一及第二群組中選擇至少一位元線；供應電流給該等選定之位元線；加偏壓於一選定之字線，其中在該等第一及第二群組中選擇至少一位元線包括在該第一群組中選擇一第一位元線，且當選定該第一位元線時，在該第二群組中選擇一第二位元線，該第二位元線係與該第一群組中之該第一位元線對稱地配置於該選定之字線上。
  2. 如請求項1之方法，其中分組一第一子複數個及分組一第二子複數個包括將n 個位元線分組在每個子複數個中，在該第一群組中選擇該第一位元線包括在該第一群組中選擇位元線BL<i>，且選擇該第二位元線包括在該第二群組中選擇位元線BL<2n-1-i>。
  3. 如請求項1之方法，該方法進一步包括取消選定該第一及第二位元線，在該第一群組中選擇不同於該第一位元線之一第三位元線，且當仍選定該第三位元線時，在該第二群組中選擇一第四位元線，該第四位元線係與該第 一群組中之該第三位元線對稱地配置。
  4. 如請求項1之方法，其中分組一第一子複數個及分組一第二子複數個包括將n個位元線分組在每個子複數個中，該方法進一步包括重複以下步驟：在該第一及第二子複數個中選擇對稱位元線直到達到在該第一群組中之一第n位元線。
  5. 如請求項1之方法，該方法進一步包括將一第三子複數個位元線分組在鄰近於該第一及第二群組之一第三群組中，其中當仍選定該第一及第二位元線時，在該第三群組中選擇一位元線，在該第三群組中之該位元線係與該第一或該第二群組中之一位元線對稱地配置。
  6. 如請求項1之方法，該方法進一步包括寫入連接至該等選定之位元線之諸相位改變記憶體單元。
  7. 如請求項1之方法，該方法進一步包括讀取連接至該等選定之位元線之諸相位改變記憶體單元。
  8. 如請求項1之方法，該方法進一步包括：提供複數個沿著一方向對齊且耦合至一周邊電路之區塊，每個區塊包含至少一字線，選址一第一區塊，且當仍選定該第一區塊時，選擇沿著該方向對稱於該第一區塊而配置之一第二區塊。
  9. 一種相位改變記憶體裝置，其包括：複數個位元線(BL)，該等位元線包含一第一群組之位元線及一第二群組之位元線；複數個跨越該等位元線之字線(WL)； 複數個在該等位元線及該等字線之交點連接之相位改變記憶體單元；一選擇階段，其用於在該第一及該第二群組中選擇至少一位元線；一電流產生器，其用於供應存取電流給該等選定之位元線；一偏壓階段，其用於加偏壓於一選定之字線，其中該選擇階段包括用於在該第一群組中選擇一第一位元線之構件，且當仍選定該第一位元線時，在該第二群組中選擇一第二位元線，該第二位元線係與該第一群組中之該第一位元線對稱地配置。
  10. 如請求項9之相位改變記憶體，其中該第一及該第二群組各者包括n個位元線，其中該選擇階段包括用於相繼在該第一群組中選擇一位元線BL<i>及在該第二群組中選擇一位元線BL<2n-1-i>之構件。
  11. 如請求項9之相位改變記憶體，其中該電流產生器包括一寫入階段。
  12. 如請求項9之相位改變記憶體，其中該電流產生器包括一感測階段。
  13. 如請求項9之相位改變記憶體，其中該等字線被分組在複數個沿著一方向對齊且耦合至一周邊電路的區塊中，該記憶體包括用於選址一第一區塊及用於選址一第二區塊之構件，當仍選址該第一區塊時該第二區塊係沿著該方向對稱地配置。
TW098140395A 2008-12-29 2009-11-26 低功率存取相位改變記憶體裝置之方法 TWI456574B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/345,411 US7869267B2 (en) 2008-12-29 2008-12-29 Method for low power accessing a phase change memory device

Publications (2)

Publication Number Publication Date
TW201027537A TW201027537A (en) 2010-07-16
TWI456574B true TWI456574B (zh) 2014-10-11

Family

ID=42221044

Family Applications (1)

Application Number Title Priority Date Filing Date
TW098140395A TWI456574B (zh) 2008-12-29 2009-11-26 低功率存取相位改變記憶體裝置之方法

Country Status (6)

Country Link
US (1) US7869267B2 (zh)
JP (1) JP5518441B2 (zh)
KR (1) KR101273979B1 (zh)
CN (1) CN101923894B (zh)
DE (1) DE102009050745B4 (zh)
TW (1) TWI456574B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120118356A (ko) 2011-04-18 2012-10-26 삼성전자주식회사 반도체 메모리 장치
ITTO20120412A1 (it) * 2012-05-08 2013-11-09 St Microelectronics Srl Circuito decodificatore di riga per un dispositivo di memoria non volatile a cambiamento di fase
KR102151176B1 (ko) * 2014-08-22 2020-09-02 삼성전자 주식회사 크로스 포인트 어레이 구조의 메모리 장치, 메모리 시스템 및 메모리 장치의 동작방법
IT201900010419A1 (it) * 2019-06-28 2020-12-28 St Microelectronics Srl Metodo di programmazione di un dispositivo di memoria a cambiamento di fase di tipo differenziale, dispositivo di memoria, e sistema elettronico
US11508436B2 (en) * 2020-09-29 2022-11-22 Sharp Semiconductor Innovation Corporation Memory device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200632923A (en) * 2004-11-24 2006-09-16 Freescale Semiconductor Inc Reduced power magnetoresistive random access memory elements
US20060221734A1 (en) * 2005-03-30 2006-10-05 Ferdinando Bedeschi Detecting switching of access elements of phase change memory cells
US20070058425A1 (en) * 2005-09-08 2007-03-15 Woo-Yeong Cho Phase change random access memory device having variable drive voltage circuit
US20070184613A1 (en) * 2006-02-07 2007-08-09 Samsung Electronics Co. Ltd. Phase change RAM including resistance element having diode function and methods of fabricating and operating the same
US20080055972A1 (en) * 2006-09-05 2008-03-06 Hyung-Rok Oh Phase change random access memory
TWI304586B (en) * 2006-03-20 2008-12-21 Univ Nat Yunlin Sci & Tech System for reducing critical current of magnetic random access memory

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE60217120T2 (de) * 2002-10-08 2007-10-25 Stmicroelectronics S.R.L., Agrate Brianza Zellenanordnung mit einem darin enthaltenen Auswähl-Bipolartransistor sowie Verfahren zum Herstellen derselben
US7459715B2 (en) * 2003-04-03 2008-12-02 Kabushiki Kaisha Toshiba Resistance change memory device
EP1548744A1 (en) * 2003-12-23 2005-06-29 STMicroelectronics S.r.l. Fast reading, low power consumption memory device and reading method thereof
KR100719383B1 (ko) * 2006-04-12 2007-05-18 삼성전자주식회사 멀티 프로그램 방법을 사용하는 상 변화 메모리 장치
WO2008032394A1 (fr) * 2006-09-15 2008-03-20 Renesas Technology Corp. Dispositif semi-conducteur
KR101258983B1 (ko) * 2006-09-19 2013-04-29 삼성전자주식회사 가변저항 소자를 이용한 반도체 메모리 장치 및 그 동작방법
US7440316B1 (en) * 2007-04-30 2008-10-21 Super Talent Electronics, Inc 8/9 and 8/10-bit encoding to reduce peak surge currents when writing phase-change memory
KR101308549B1 (ko) * 2007-07-12 2013-09-13 삼성전자주식회사 멀티-레벨 상변환 메모리 장치 및 그것의 쓰기 방법
JP2008252112A (ja) * 2008-05-15 2008-10-16 Renesas Technology Corp 不揮発性半導体記憶装置および不揮発性メモリセル
CN101329905A (zh) * 2008-07-24 2008-12-24 复旦大学 一种新型不挥发动态存储器及其存储操作方法
JP2010061727A (ja) * 2008-09-02 2010-03-18 Renesas Technology Corp 不揮発性半導体記憶装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200632923A (en) * 2004-11-24 2006-09-16 Freescale Semiconductor Inc Reduced power magnetoresistive random access memory elements
US20060221734A1 (en) * 2005-03-30 2006-10-05 Ferdinando Bedeschi Detecting switching of access elements of phase change memory cells
US20070058425A1 (en) * 2005-09-08 2007-03-15 Woo-Yeong Cho Phase change random access memory device having variable drive voltage circuit
US20070184613A1 (en) * 2006-02-07 2007-08-09 Samsung Electronics Co. Ltd. Phase change RAM including resistance element having diode function and methods of fabricating and operating the same
TWI304586B (en) * 2006-03-20 2008-12-21 Univ Nat Yunlin Sci & Tech System for reducing critical current of magnetic random access memory
US20080055972A1 (en) * 2006-09-05 2008-03-06 Hyung-Rok Oh Phase change random access memory

Also Published As

Publication number Publication date
US20100165713A1 (en) 2010-07-01
KR101273979B1 (ko) 2013-06-12
CN101923894A (zh) 2010-12-22
DE102009050745B4 (de) 2015-06-03
CN101923894B (zh) 2013-07-10
JP2010157305A (ja) 2010-07-15
TW201027537A (en) 2010-07-16
DE102009050745A1 (de) 2010-07-01
US7869267B2 (en) 2011-01-11
JP5518441B2 (ja) 2014-06-11
KR20100080349A (ko) 2010-07-08

Similar Documents

Publication Publication Date Title
TW200802364A (en) Nonvolatile semiconductor memory device
CN101925961B (zh) 具有共享源极线的mram装置
EP1916665A3 (en) Combined read/write circuit for memory
TW200737182A (en) High-bandwidth magnetoresistive random access memory devices and methods of operation thereof
JP2007087526A5 (zh)
KR102151176B1 (ko) 크로스 포인트 어레이 구조의 메모리 장치, 메모리 시스템 및 메모리 장치의 동작방법
ATE545934T1 (de) Speichersystem
TWI456574B (zh) 低功率存取相位改變記憶體裝置之方法
WO2008002813A3 (en) Current driven switching of magnetic storage cells utilizing spin transfer and magnetic memories using such cells having enhanced read and write margins
US20100061153A1 (en) Refresh Method for a Non-volatile Memory
TW200710866A (en) Semiconductor storage device
WO2006031551A3 (en) Selective replication of data structure
TW200620281A (en) MRAM with staggered cell structure
JP6397773B2 (ja) 磁気記憶装置及び磁気記憶方法
TW200629269A (en) Nonvolatile semiconductor memory device and phase change memory
JP2008158955A5 (zh)
TW201243846A (en) Semiconductor memory device
JP2013527550A5 (zh)
JP2003204001A5 (zh)
US20100182819A1 (en) Nonvolatile semiconductor memory device
CN106158001A (zh) 用于嵌入式flash应用的stt‑mram位格
US20090279351A1 (en) Semiconductor memory devices and methods having core structures for multi-writing
US6853599B2 (en) Magnetic memory device implementing read operation tolerant to bitline clamp voltage (VREF)
KR20150028727A (ko) 공유 판독 및 기록 회로들을 가진 타일들을 포함하는 메모리 장치
TW200636721A (en) Memory device with pre-fetch circuit and pre-fetch method