TWI454195B - 固設半導體晶片於線路基板之方法及其結構 - Google Patents
固設半導體晶片於線路基板之方法及其結構 Download PDFInfo
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Description
本發明是有關於一種固設半導體晶片於線路基板之方法及其結構,特別是有關於一種用於液晶顯示器的固設半導體晶片於線路基板之方法及其結構。
近年來,電子產品的特性需求已往高構裝密度及高電氣可靠度發展。為了達到這些需求,發展出如可撓基板上晶片(chip on film,COF)與玻璃上晶片(chip on glass,COG)之技術。而玻璃上晶片技術目前已廣泛運用於液晶顯示器領域中。
一般而言,玻璃上晶片製程的步驟如下。首先,覆蓋一層異向性導電膠於接合墊及其周圍的絕緣層上。然後,在異向性導電膠上熱壓半導體晶片,使半導體晶片的凸塊與接合墊間可透過異向性導電膠電性連接。然而,在高溫高濕的可靠度測試中,絕緣層下方的金屬線會隨機地發生腐蝕現象而使得金屬線斷線,進而導致面板的報廢。
因此,需開發一種固設半導體晶片於線路基板之方法及其結構,以解決上述問題。
本發明之目的在於提供一種固設半導體晶片於線路基板之方法,以避免在高溫高濕的可靠度測試中金屬線發生腐蝕現象。
根據本發明一實施方式,該方法包含下列步驟。提供線路基板,線路基板包含基材、至少一金屬線與絕緣層。基材具有一晶片接合區。金屬線位於基材上,其由晶片接合區外延伸進入晶片接合區內,且金屬線具有一接合墊位於晶片接合區。絕緣層配置於金屬線上,且絕緣層具有一開口露出接合墊。形成有機絕緣材於晶片接合區外緣之絕緣層上。形成異向性導電膠覆蓋晶片接合區以及有機絕緣材之一部分。熱壓半導體晶片於異向性導電膠上,使半導體晶片之凸塊藉由異向性導電膠與接合墊電性連接。
在另一實施方式中,該方法包含下列步驟。提供線路基板,線路基板包含基材、至少一金屬線與絕緣層。基材具有一晶片接合區。金屬線位於基材上,其由晶片接合區外延伸進入晶片接合區內,且金屬線具有一接合墊位於晶片接合區。絕緣層配置於金屬線上,且絕緣層具有一開口露出接合墊。絕緣層配置於金屬線上,且絕緣層具有一開口露出接合墊。形成非導電膠於晶片接合區以及晶片接合區外緣之絕緣層上,其中非導電膠覆蓋金屬線之一部分。形成異向性導電膠於晶片接合區之非導電膠以及晶片接合區外緣之絕緣層上。熱壓半導體晶片於異向性導電膠上,使半導體晶片之凸塊藉由異向性導電膠與接合墊電性連接。
本發明之另一態樣是在提供一種半導體晶片封裝結構,其包含有基材、至少一金屬線、絕緣層、有機絕緣材、異向性導電膠與晶片。基材具有一晶片接合區。金屬線位於基材上,其由晶片接合區外延伸進入晶片接合區內,且金屬線具有一接合墊位於晶片接合區。絕緣層位於金屬線上,且絕緣層具有一開口露出接合墊。有機絕緣材位於晶片接合區外緣之絕緣層上。異向性導電膠覆蓋晶片接合區以及有機絕緣材之一部分。半導體晶片位於晶片接合區之異向性導電膠上,其中半導體晶片之凸塊藉由異向性導電膠與接合墊電性連接。
為了使本揭示內容的敘述更加詳盡與完備,下文針對了本發明的實施態樣與具體實施例提出了說明性的描述;但這並非實施或運用本發明具體實施例的唯一形式。以下所揭露的各實施例,在有益的情形下可相互組合或取代,也可在一實施例中附加其他的實施例,而無須進一步的記載或說明。
本發明之一態樣是在提供一種固設半導體晶片於線路基板之方法。第1圖繪示方法100的流程圖。第2A圖繪示依照本發明一實施方式之線路基板的俯視示意圖。第2B圖繪示依照本發明一實施方式的線路基板的剖面示意圖,其為沿著第2A圖中之2A-2A’的剖面線段。第3A圖繪示依照本發明一實施方式的半導體晶片封裝結構的俯視示意圖。第3B與3C圖繪示方法100的各製程階段的剖面示意圖,其為沿著第3A圖中之3A-3A’的剖面線段。
在步驟110中,提供線路基板210,其包含基材202、金屬線204、206與絕緣層208,如第2A與2B圖所示。線路基板210可為薄膜電晶體基板的一部分,如欲封裝閘驅動晶片的部分。基材202具有至少一晶片接合區212以及晶片接合區外緣214。金屬線204、206位於基材202上,其可分別為外金屬線與端子部的金屬線。金屬線204、206由晶片接合區212外延伸進入晶片接合區212內。並且,每一金屬線204、206各具有一接合墊204a、206a位於晶片接合區212內。絕緣層208配置於金屬線204、206上,且絕緣層208具有開口208a,以露出接合墊204a、206a。在一實施例中,絕緣層208的材料由無機材料所製成,例如為氮化矽。
在步驟120中,形成有機絕緣材220於晶片接合區外緣214之絕緣層208上,如第3A與3B圖所示。這是為了在形成異向性導電膠(步驟130)和熱壓半導體晶片(步驟140)後,讓異向性導電膠230與絕緣層208間隔離,以解決金屬線腐蝕問題。習知封裝結構中金屬線腐蝕機制將在步驟130中詳細說明。有機絕緣材220本身可具有黏性,如橡膠或非導電膠(non-conductive film,NCF)。或者,有機絕緣材220的一表面上具有黏著層(未繪示)以與絕緣層208黏著,例如可為絕緣膠帶。
在步驟130中,形成異向性導電膠(anisotropic conductive film,ACF) 230覆蓋晶片接合區212及一部分的有機絕緣材220,如第3A與3B圖所示。也就是說,有機絕緣材220隔離異向性導電膠230與絕緣層208,以解決金屬線腐蝕問題。習知封裝結構中金屬線腐蝕的機制推論如下。當施加電壓於金屬線時,金屬線會與異向性導電膠中的導電粒子會形成感應電場。感應電場可能使異向性導電膠下方的絕緣層破裂。當進行高溫高濕的可靠度測試時,水氣可能從裂隙進入與金屬線反應,導致金屬線腐蝕。因此,在本實施方式中,藉由有機絕緣材220來隔離異向性導電膠230與絕緣層208以使感應電場減低,而可防止絕緣層208破裂。在一實施例中,有機絕緣材220的厚度W2大於絕緣層208的厚度W1。具體來說,絕緣層208的厚度W1可小於1μm,而有機絕緣材220的厚度W2可遠大於1μm。
在步驟140中,熱壓半導體晶片240於異向性導電膠230上,使凸塊242藉由異向性導電膠230與接合墊204a、206a電性連接,如第3A與3C圖所示。半導體晶片240可用以提供大於10 V之電壓至金屬線204、206。半導體晶片240例如可為閘驅動晶片。在熱壓製程中,異向性導電膠230流動且填入開口208a內。異向性導電膠230藉由有機絕緣材220與絕緣層208的上表面隔離,而可避免金屬線腐蝕現象發生。此外,凸塊242與接合墊204a、206a間可透過變形的導電粒子垂直電性連接。
第4圖繪示方法400的流程圖。步驟410可與第1圖中的步驟110相同。以下將列舉兩種實施例。第5A與5B圖分別繪示兩實施例之半導體晶片封裝結構的俯視示意圖。第5C與5D圖繪示方法400中各製程階段的剖面示意圖,其為沿著第5A圖中之5A-5A’或第5B圖中之5B-5B’的剖面線段。
在步驟420中,形成非導電膠222於晶片接合區212及晶片接合區外緣214之絕緣層208上,如第5C圖所示。並且,非導電膠222覆蓋金屬線204、206之一部分。在一實施例中,一非導電膠222用以覆蓋一個晶片接合區212及晶片接合區212外緣的絕緣層208上,如第5A圖所示。在另一實施例中,一非導電膠222用以覆蓋數個晶片接合區212及晶片接合區以外的部分,如第5B圖所示。
在步驟430中,形成異向性導電膠230於晶片接合區212上方之非導電膠222上,如第5C圖所示。類似於方法100中的有機絕緣材220,非導電膠222可用以隔離絕緣層208與異向性導電膠230。在一實施例中,非導電膠222之維度D1大於異向性導電膠230之維度D2,如第5A及5B圖所示。在此提及的維度,是指長度與寬度構成的二維維度。這是為了防止在熱壓製程時,異向性導電膠230溢流而與絕緣層208的上表面接觸。在一實施例中,非導電膠222的厚度W3大於絕緣層208的厚度W1。異向性導電膠230中的膠成分可與非導電膠222大致相同,但非導電膠222中不含導電粒子。
在步驟440中,熱壓半導體晶片240於異向性導電膠230上,使凸塊242藉由異向性導電膠230與接合墊204a、206a電性連接,如第5D圖所示。在熱壓製程中,非導電膠222與異向性導電膠230流動且相互融合,而填入開口208a中。另外,凸塊242與接合墊204a、206a間可透過變形的導電粒子垂直電性連接。
上述兩種實施方式製造的結構在經過高溫高濕的可靠度測試後,皆沒有發生金屬線腐蝕現象。因此本發明所揭露之實施方式可有效解決習知金屬線腐蝕問題。
本發明之另一態樣是在提供一種半導體晶片封裝結構。如第3C與5D圖所示,半導體晶片封裝結構300、500皆包含有基材202、至少一金屬線204、絕緣層208、有機絕緣材220、異向性導電膠230a與半導體晶片240。
基材202可為玻璃基材,其具有至少一晶片接合區212。
金屬線204、206可分別為外金屬線與端子部的金屬線,其位於基材202上。金屬線204、206由晶片接合區212外延伸進入晶片接合區212內。並且,每一金屬線204、206各具有一接合墊204a、206a位於晶片接合區212內。
絕緣層208配置於金屬線204、206上。並且,絕緣層208具有開口208a,以露出接合墊204a、206a。在一實施例中,絕緣層208的材料由無機材料所製成,例如為氮化矽。
有機絕緣材220位於晶片接合區外緣214之絕緣層208上。在一實施例中,有機絕緣材220為絕緣膠帶、橡膠或非導電膠,如第3C圖所示。在另一實施例中,有機絕緣材220為非導電膠222,如第5D圖所示。
異向性導電膠230a覆蓋晶片接合區212以及有機絕緣材220之一部分。在半導體晶片封裝結構300中,異向性導電膠230a為由異向性導電膠230經熱壓製程所形成。在半導體晶片封裝結構500中,異向性導電膠230a為由非導電膠222及異向性導電膠230經熱壓製程所形成。
半導體晶片240位於晶片接合區212之異向性導電膠230a上。凸塊242藉由異向性導電膠230a與接合墊204a、206a電性連接。
由上述可知,藉由設置有機絕緣材於絕緣層上,可有效避免絕緣層下方金屬線腐蝕。進一步地,可減少面板報廢的數量以及降低報廢成本。
雖然本發明已以實施方式揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100、400...製造方法
110、120、130、140、410、420、430、440...步驟
204、206...金屬線
204a、206a...接合墊
208...絕緣層
208a...開口
210...線路基板
212...晶片接合區
214...晶片接合區外緣
220...有機絕緣材
222...非導電膠
230、230a...異向性導電膠
240...半導體晶片
242...凸塊
300、500...半導體晶片封裝結構
D1...非導電膠之維度
D2...異向性導電膠之維度
W1...絕緣層之厚度
W2...有機絕緣材之厚度
W3...非導電膠之厚度
第1圖繪示依照本發明一實施方式的固設半導體晶片於線路基板之方法的流程圖。
第2A圖繪示依照本發明一實施方式的線路基板的俯視示意圖。
第2B圖繪示依照本發明一實施方式的線路基板的剖面示意圖。
第3A圖繪示依照本發明一實施方式的半導體晶片封裝結構的俯視示意圖。
第3B、3C圖繪示依照本發明一實施方式之固設半導體晶片於線路基板之方法的各製程階段的剖面示意圖。
第4圖繪示依照本發明另一實施方式的固設半導體晶片於線路基板之方法的流程圖。
第5A圖繪示依照本發明另一實施方式的半導體晶片封裝結構的俯視示意圖。
第5B圖繪示依照本發明又一實施方式的半導體晶片封裝結構的俯視示意圖。
第5C、5D圖繪示依照本發明另一實施方式之固設半導體晶片於線路基板之方法中各製程階段的剖面示意圖。
100...製造方法
110、120、130、140...步驟
Claims (3)
- 一種固設一半導體晶片於一線路基板之方法,包含:提供該線路基板,該線路基板包含:一基材,具有一晶片接合區;至少一金屬線,位於該基材上,該金屬線由該晶片接合區外延伸進入該晶片接合區內,且該金屬線具有一接合墊位於該晶片接合區;以及一絕緣層,配置於該金屬線上,且該絕緣層具有一開口露出該接合墊;形成一非導電膠全面覆蓋該晶片接合區以及覆蓋該晶片接合區外緣之該絕緣層上,其中該非導電膠覆蓋該金屬線之一部分;形成一異向性導電膠於該晶片接合區之該非導電膠以及該晶片接合區外緣之該絕緣層上;以及熱壓該半導體晶片於該異向性導電膠上,使該半導體晶片之一凸塊藉由該異向性導電膠與該接合墊電性連接。
- 如請求項1所述之方法,其中該非導電膠之一厚度大於該絕緣層之一厚度。
- 如請求項1所述之方法,其中該絕緣層包括一無機材料所製成。
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Publication number | Priority date | Publication date | Assignee | Title |
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