TWI447815B - 使用蝕刻終止層以最佳化源極與汲極壓力層的形成之半導體製造方法 - Google Patents
使用蝕刻終止層以最佳化源極與汲極壓力層的形成之半導體製造方法 Download PDFInfo
- Publication number
- TWI447815B TWI447815B TW096108790A TW96108790A TWI447815B TW I447815 B TWI447815 B TW I447815B TW 096108790 A TW096108790 A TW 096108790A TW 96108790 A TW96108790 A TW 96108790A TW I447815 B TWI447815 B TW I447815B
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- Taiwan
- Prior art keywords
- layer
- source
- esl
- semiconductor
- drain
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 69
- 238000004519 manufacturing process Methods 0.000 title claims description 28
- 238000000034 method Methods 0.000 title claims description 28
- 230000015572 biosynthetic process Effects 0.000 title description 6
- 238000005530 etching Methods 0.000 claims description 16
- 229910052732 germanium Inorganic materials 0.000 claims description 15
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 15
- 230000006378 damage Effects 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 150000001875 compounds Chemical class 0.000 claims description 6
- 150000001622 bismuth compounds Chemical class 0.000 claims description 4
- KCFIHQSTJSCCBR-UHFFFAOYSA-N [C].[Ge] Chemical compound [C].[Ge] KCFIHQSTJSCCBR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052684 Cerium Inorganic materials 0.000 claims description 2
- 229910052797 bismuth Inorganic materials 0.000 claims description 2
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 2
- VQYPKWOGIPDGPN-UHFFFAOYSA-N [C].[Ta] Chemical compound [C].[Ta] VQYPKWOGIPDGPN-UHFFFAOYSA-N 0.000 claims 1
- ZMIGMASIKSOYAM-UHFFFAOYSA-N cerium Chemical compound [Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce] ZMIGMASIKSOYAM-UHFFFAOYSA-N 0.000 claims 1
- 150000001785 cerium compounds Chemical class 0.000 claims 1
- NCPHGZWGGANCAY-UHFFFAOYSA-N methane;ruthenium Chemical compound C.[Ru] NCPHGZWGGANCAY-UHFFFAOYSA-N 0.000 claims 1
- 229910052715 tantalum Inorganic materials 0.000 claims 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims 1
- 239000000463 material Substances 0.000 description 13
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 10
- 239000007943 implant Substances 0.000 description 7
- 230000008901 benefit Effects 0.000 description 6
- 125000006850 spacer group Chemical group 0.000 description 6
- 239000010408 film Substances 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 4
- 229910052707 ruthenium Inorganic materials 0.000 description 4
- 238000002513 implantation Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000002291 germanium compounds Chemical class 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 2
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 description 1
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 description 1
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000003776 cleavage reaction Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910001507 metal halide Inorganic materials 0.000 description 1
- 150000005309 metal halides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 230000007017 scission Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/01—Manufacture or treatment
- H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
- H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
- H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/393,340 US7494856B2 (en) | 2006-03-30 | 2006-03-30 | Semiconductor fabrication process using etch stop layer to optimize formation of source/drain stressor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200802624A TW200802624A (en) | 2008-01-01 |
| TWI447815B true TWI447815B (zh) | 2014-08-01 |
Family
ID=38575839
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW096108790A TWI447815B (zh) | 2006-03-30 | 2007-03-14 | 使用蝕刻終止層以最佳化源極與汲極壓力層的形成之半導體製造方法 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US7494856B2 (enExample) |
| EP (1) | EP2005477A4 (enExample) |
| JP (1) | JP5203352B2 (enExample) |
| KR (1) | KR20080108498A (enExample) |
| TW (1) | TWI447815B (enExample) |
| WO (1) | WO2007117775A2 (enExample) |
Families Citing this family (51)
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|---|---|---|---|---|
| TW200802544A (en) * | 2006-04-25 | 2008-01-01 | Osram Opto Semiconductors Gmbh | Composite substrate and method for making the same |
| KR100703986B1 (ko) * | 2006-05-22 | 2007-04-09 | 삼성전자주식회사 | 동작 특성과 플리커 노이즈 특성이 향상된 아날로그트랜지스터를 구비하는 반도체 소자 및 그 제조 방법 |
| US8003454B2 (en) * | 2008-05-22 | 2011-08-23 | Freescale Semiconductor, Inc. | CMOS process with optimized PMOS and NMOS transistor devices |
| US20090289280A1 (en) * | 2008-05-22 | 2009-11-26 | Da Zhang | Method for Making Transistors and the Device Thereof |
| KR101797964B1 (ko) | 2010-10-01 | 2017-11-15 | 삼성전자주식회사 | 반도체 장치의 제조 방법 및 그 방법으로 제조된 반도체 장치 |
| KR20120073727A (ko) * | 2010-12-27 | 2012-07-05 | 삼성전자주식회사 | 스트레인드 반도체 영역을 포함하는 반도체 소자와 그 제조방법, 및 그것을 포함하는 전자 시스템 |
| US8466502B2 (en) | 2011-03-24 | 2013-06-18 | United Microelectronics Corp. | Metal-gate CMOS device |
| US8445363B2 (en) | 2011-04-21 | 2013-05-21 | United Microelectronics Corp. | Method of fabricating an epitaxial layer |
| US8324059B2 (en) | 2011-04-25 | 2012-12-04 | United Microelectronics Corp. | Method of fabricating a semiconductor structure |
| US8426284B2 (en) | 2011-05-11 | 2013-04-23 | United Microelectronics Corp. | Manufacturing method for semiconductor structure |
| US8481391B2 (en) | 2011-05-18 | 2013-07-09 | United Microelectronics Corp. | Process for manufacturing stress-providing structure and semiconductor device with such stress-providing structure |
| US8431460B2 (en) | 2011-05-27 | 2013-04-30 | United Microelectronics Corp. | Method for fabricating semiconductor device |
| US8946064B2 (en) | 2011-06-16 | 2015-02-03 | International Business Machines Corporation | Transistor with buried silicon germanium for improved proximity control and optimized recess shape |
| WO2013025748A1 (en) * | 2011-08-15 | 2013-02-21 | King Abdullah University Of Science And Technology | Method for producing mechanically flexible silicon substrate |
| US8609518B2 (en) * | 2011-07-22 | 2013-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Re-growing source/drain regions from un-relaxed silicon layer |
| US8716750B2 (en) | 2011-07-25 | 2014-05-06 | United Microelectronics Corp. | Semiconductor device having epitaxial structures |
| US8575043B2 (en) | 2011-07-26 | 2013-11-05 | United Microelectronics Corp. | Semiconductor device and manufacturing method thereof |
| US8647941B2 (en) | 2011-08-17 | 2014-02-11 | United Microelectronics Corp. | Method of forming semiconductor device |
| US8674433B2 (en) | 2011-08-24 | 2014-03-18 | United Microelectronics Corp. | Semiconductor process |
| US8476169B2 (en) | 2011-10-17 | 2013-07-02 | United Microelectronics Corp. | Method of making strained silicon channel semiconductor structure |
| US8691659B2 (en) | 2011-10-26 | 2014-04-08 | United Microelectronics Corp. | Method for forming void-free dielectric layer |
| US8754448B2 (en) | 2011-11-01 | 2014-06-17 | United Microelectronics Corp. | Semiconductor device having epitaxial layer |
| US8647953B2 (en) | 2011-11-17 | 2014-02-11 | United Microelectronics Corp. | Method for fabricating first and second epitaxial cap layers |
| US8709930B2 (en) | 2011-11-25 | 2014-04-29 | United Microelectronics Corp. | Semiconductor process |
| US9059248B2 (en) * | 2012-02-09 | 2015-06-16 | International Business Machines Corporation | Junction butting on SOI by raised epitaxial structure and method |
| US9136348B2 (en) | 2012-03-12 | 2015-09-15 | United Microelectronics Corp. | Semiconductor structure and fabrication method thereof |
| US9202914B2 (en) | 2012-03-14 | 2015-12-01 | United Microelectronics Corporation | Semiconductor device and method for fabricating the same |
| US8664069B2 (en) | 2012-04-05 | 2014-03-04 | United Microelectronics Corp. | Semiconductor structure and process thereof |
| US8866230B2 (en) | 2012-04-26 | 2014-10-21 | United Microelectronics Corp. | Semiconductor devices |
| US8835243B2 (en) | 2012-05-04 | 2014-09-16 | United Microelectronics Corp. | Semiconductor process |
| KR101908451B1 (ko) | 2012-06-04 | 2018-10-16 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
| US8951876B2 (en) | 2012-06-20 | 2015-02-10 | United Microelectronics Corp. | Semiconductor device and manufacturing method thereof |
| US8796695B2 (en) | 2012-06-22 | 2014-08-05 | United Microelectronics Corp. | Multi-gate field-effect transistor and process thereof |
| US8710632B2 (en) | 2012-09-07 | 2014-04-29 | United Microelectronics Corp. | Compound semiconductor epitaxial structure and method for fabricating the same |
| US9117925B2 (en) | 2013-01-31 | 2015-08-25 | United Microelectronics Corp. | Epitaxial process |
| US8753902B1 (en) | 2013-03-13 | 2014-06-17 | United Microelectronics Corp. | Method of controlling etching process for forming epitaxial structure |
| US9034705B2 (en) | 2013-03-26 | 2015-05-19 | United Microelectronics Corp. | Method of forming semiconductor device |
| US9064893B2 (en) | 2013-05-13 | 2015-06-23 | United Microelectronics Corp. | Gradient dopant of strained substrate manufacturing method of semiconductor device |
| US9076652B2 (en) | 2013-05-27 | 2015-07-07 | United Microelectronics Corp. | Semiconductor process for modifying shape of recess |
| US8853060B1 (en) | 2013-05-27 | 2014-10-07 | United Microelectronics Corp. | Epitaxial process |
| US8765546B1 (en) | 2013-06-24 | 2014-07-01 | United Microelectronics Corp. | Method for fabricating fin-shaped field-effect transistor |
| US8895396B1 (en) | 2013-07-11 | 2014-11-25 | United Microelectronics Corp. | Epitaxial Process of forming stress inducing epitaxial layers in source and drain regions of PMOS and NMOS structures |
| US8981487B2 (en) | 2013-07-31 | 2015-03-17 | United Microelectronics Corp. | Fin-shaped field-effect transistor (FinFET) |
| US9917189B2 (en) | 2015-07-31 | 2018-03-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for detecting presence and location of defects in a substrate |
| US9831324B1 (en) | 2016-08-12 | 2017-11-28 | International Business Machines Corporation | Self-aligned inner-spacer replacement process using implantation |
| US10461152B2 (en) | 2017-07-10 | 2019-10-29 | Globalfoundries Inc. | Radio frequency switches with air gap structures |
| US10833153B2 (en) * | 2017-09-13 | 2020-11-10 | Globalfoundries Inc. | Switch with local silicon on insulator (SOI) and deep trench isolation |
| US10446643B2 (en) | 2018-01-22 | 2019-10-15 | Globalfoundries Inc. | Sealed cavity structures with a planar surface |
| US11410872B2 (en) | 2018-11-30 | 2022-08-09 | Globalfoundries U.S. Inc. | Oxidized cavity structures within and under semiconductor devices |
| US10923577B2 (en) | 2019-01-07 | 2021-02-16 | Globalfoundries U.S. Inc. | Cavity structures under shallow trench isolation regions |
| US11127816B2 (en) | 2020-02-14 | 2021-09-21 | Globalfoundries U.S. Inc. | Heterojunction bipolar transistors with one or more sealed airgap |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060024898A1 (en) * | 2004-07-29 | 2006-02-02 | Chidambaram Pr | Increased drive current by isotropic recess etch |
| US20060030093A1 (en) * | 2004-08-06 | 2006-02-09 | Da Zhang | Strained semiconductor devices and method for forming at least a portion thereof |
| US7018901B1 (en) * | 2004-09-29 | 2006-03-28 | Freescale Semiconductor, Inc. | Method for forming a semiconductor device having a strained channel and a heterojunction source/drain |
| US7018910B2 (en) * | 2002-07-09 | 2006-03-28 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Transfer of a thin layer from a wafer comprising a buffer layer |
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| US6649480B2 (en) | 2000-12-04 | 2003-11-18 | Amberwave Systems Corporation | Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs |
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| JP2003078116A (ja) * | 2001-08-31 | 2003-03-14 | Canon Inc | 半導体部材の製造方法及び半導体装置の製造方法 |
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| US20030230778A1 (en) * | 2002-01-30 | 2003-12-18 | Sumitomo Mitsubishi Silicon Corporation | SOI structure having a SiGe Layer interposed between the silicon and the insulator |
| US20040256671A1 (en) * | 2003-06-17 | 2004-12-23 | Kuo-Tai Huang | Metal-oxide-semiconductor transistor with selective epitaxial growth film |
| US7045407B2 (en) * | 2003-12-30 | 2006-05-16 | Intel Corporation | Amorphous etch stop for the anisotropic etching of substrates |
| US6881635B1 (en) * | 2004-03-23 | 2005-04-19 | International Business Machines Corporation | Strained silicon NMOS devices with embedded source/drain |
| US6893936B1 (en) * | 2004-06-29 | 2005-05-17 | International Business Machines Corporation | Method of Forming strained SI/SIGE on insulator with silicon germanium buffer |
-
2006
- 2006-03-30 US US11/393,340 patent/US7494856B2/en not_active Expired - Fee Related
-
2007
- 2007-02-22 WO PCT/US2007/062559 patent/WO2007117775A2/en not_active Ceased
- 2007-02-22 KR KR1020087023819A patent/KR20080108498A/ko not_active Withdrawn
- 2007-02-22 EP EP07757316A patent/EP2005477A4/en not_active Withdrawn
- 2007-02-22 JP JP2009503114A patent/JP5203352B2/ja not_active Expired - Fee Related
- 2007-03-14 TW TW096108790A patent/TWI447815B/zh not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7018910B2 (en) * | 2002-07-09 | 2006-03-28 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Transfer of a thin layer from a wafer comprising a buffer layer |
| US20060024898A1 (en) * | 2004-07-29 | 2006-02-02 | Chidambaram Pr | Increased drive current by isotropic recess etch |
| US20060030093A1 (en) * | 2004-08-06 | 2006-02-09 | Da Zhang | Strained semiconductor devices and method for forming at least a portion thereof |
| US7018901B1 (en) * | 2004-09-29 | 2006-03-28 | Freescale Semiconductor, Inc. | Method for forming a semiconductor device having a strained channel and a heterojunction source/drain |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2007117775A3 (en) | 2007-12-21 |
| TW200802624A (en) | 2008-01-01 |
| US20070238250A1 (en) | 2007-10-11 |
| WO2007117775A2 (en) | 2007-10-18 |
| KR20080108498A (ko) | 2008-12-15 |
| EP2005477A2 (en) | 2008-12-24 |
| JP2009532875A (ja) | 2009-09-10 |
| US7494856B2 (en) | 2009-02-24 |
| JP5203352B2 (ja) | 2013-06-05 |
| EP2005477A4 (en) | 2012-06-13 |
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