JP5203352B2 - エッチング停止層を用いてソース／ドレイン・ストレッサの形成を最適化する半導体の製造方法 - Google Patents

エッチング停止層を用いてソース／ドレイン・ストレッサの形成を最適化する半導体の製造方法 Download PDF

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JP5203352B2
JP5203352B2 JP2009503114A JP2009503114A JP5203352B2 JP 5203352 B2 JP5203352 B2 JP 5203352B2 JP 2009503114 A JP2009503114 A JP 2009503114A JP 2009503114 A JP2009503114 A JP 2009503114A JP 5203352 B2 JP5203352 B2 JP 5203352B2
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layer
source
semiconductor
wafer
esl
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JP2009532875A5 (enExample
JP2009532875A (ja
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チャン、ダー
ホワイト、テッド
イエン グエン、ビック
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NXP USA Inc
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NXP USA Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2009503114A 2006-03-30 2007-02-22 エッチング停止層を用いてソース／ドレイン・ストレッサの形成を最適化する半導体の製造方法 Expired - Fee Related JP5203352B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/393,340 US7494856B2 (en) 2006-03-30 2006-03-30 Semiconductor fabrication process using etch stop layer to optimize formation of source/drain stressor
US11/393,340 2006-03-30
PCT/US2007/062559 WO2007117775A2 (en) 2006-03-30 2007-02-22 Semiconductor fabrication process using etch stop layer to optimize formation of source/drain stressor

Publications (3)

Publication Number Publication Date
JP2009532875A JP2009532875A (ja) 2009-09-10
JP2009532875A5 JP2009532875A5 (enExample) 2010-03-18
JP5203352B2 true JP5203352B2 (ja) 2013-06-05

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JP2009503114A Expired - Fee Related JP5203352B2 (ja) 2006-03-30 2007-02-22 エッチング停止層を用いてソース／ドレイン・ストレッサの形成を最適化する半導体の製造方法

Country Status (6)

Country Link
US (1) US7494856B2 (enExample)
EP (1) EP2005477A4 (enExample)
JP (1) JP5203352B2 (enExample)
KR (1) KR20080108498A (enExample)
TW (1) TWI447815B (enExample)
WO (1) WO2007117775A2 (enExample)

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KR20120073727A (ko) * 2010-12-27 2012-07-05 삼성전자주식회사 스트레인드 반도체 영역을 포함하는 반도체 소자와 그 제조방법, 및 그것을 포함하는 전자 시스템
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US8609518B2 (en) * 2011-07-22 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Re-growing source/drain regions from un-relaxed silicon layer
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US8647941B2 (en) 2011-08-17 2014-02-11 United Microelectronics Corp. Method of forming semiconductor device
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US8691659B2 (en) 2011-10-26 2014-04-08 United Microelectronics Corp. Method for forming void-free dielectric layer
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US9059248B2 (en) * 2012-02-09 2015-06-16 International Business Machines Corporation Junction butting on SOI by raised epitaxial structure and method
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Also Published As

Publication number Publication date
WO2007117775A3 (en) 2007-12-21
TW200802624A (en) 2008-01-01
US20070238250A1 (en) 2007-10-11
WO2007117775A2 (en) 2007-10-18
KR20080108498A (ko) 2008-12-15
EP2005477A2 (en) 2008-12-24
JP2009532875A (ja) 2009-09-10
TWI447815B (zh) 2014-08-01
US7494856B2 (en) 2009-02-24
EP2005477A4 (en) 2012-06-13

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