Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/01—Manufacture or treatment
  • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
  • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
  • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
  • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
  • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
  • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
  • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
  • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
  • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain

Definitions

• the invention is in the field of semiconductor fabrication and, more particularly, semiconductor fabrication processes that use strained transistor channels.
• a transistor channel is subjected to tensile or compressive stress along one or more axes to improve carrier mobility in the channel and thereby enhance transistor performance.
• One technique for subjecting the channel to stress includes the use of a source/drain stressor.
• a source/drain (S/D) stressor refers to the use of a source/drain material having a different lattice constant than the lattice constant of the transistor channel material, which is usually silicon.
• a S/D stressor is typically realized by etching device S/D regions followed by epitaxial growth of a strained film in the etched cavities. Forming source/drain stressors of this type can be problematic because of difficulty in controlling the source/drain etch process.
• the S/D etch rate typically varies across the wafer, and it changes for areas with different device feature densities. As a result, the etch process induces unwanted S/D recessing depth variation. It would be desirable to implement a process that addressed the processing variability associated with conventional techniques for creating source/drain stressors.
• FIG. 1 is a partial cross sectional view of a semiconductor wafer at an early stage in the fabrication of an integrated circuit according to an embodiment of the invention emphasizing the formation of an etch stop layer on a semiconductor substrate of a donor wafer;
• FIG. 2 depicts processing subsequent to FIG. 1 in which a dielectric layer is formed on the etch stop layer
• FIG. 3 depicts processing subsequent to FIG. 2 in which a damage layer is formed in the donor wafer substrate
• FIG. 4 depicts processing subsequent to FIG. 3 in which the dielectric layer of the donor wafer is bonded to a dielectric layer on a handle wafer to form an integrated circuit wafer;
• FIG. 5 depicts processing subsequent to FIG. 4 in which the donor wafer is cleaved at the damage layer of FIG. 3 to expose a new upper surface
• FIG. 6 depicts processing subsequent to FIG. 5 in which the new upper surface of FIG . 5 is prepared for device processing
• FIG. 7 depicts processing subsequent to FIG. 6 in which a gate structure is formed on the active semiconductor layer over a transistor channel of the active semiconductor layer;
• FIG. 8 depicts processing subsequent to FIG. 7 in which source/drain voids are etched into source/drain regions of the wafer displaced on either side of the transistor channel;
• FIG. 9 depicts processing subsequent to FIG. 8 in which the source/drain voids are filled with source/drain stressors.
• a semiconductor fabrication process incorporates an etch stop layer (ESL) between the active layer and a BOX layer of a silicon on insulator (SOI) wafer.
• the ESL facilitates the formation of a source/drain stressor.
• the ESL is of a material for which an etch process with a high selectivity between the active layer and the ESL is available.
• the active layer is a silicon active layer
• the ESL is silicon germanium
• the source/drain stressor is a semiconductor compound, such as silicon germanium for PMOS transistors or silicon carbon for NMOS transistors, having a lattice constant that differs from the lattice constant of silicon.
• the depicted sequence includes processing a first wafer (the donor wafer) to form a stack including a dielectric layer, the ESL, and the active semiconductor layer. This processing may include cleaving the substrate of the donor wafer to form the active semiconductor layer. A dielectric layer is deposited on the semiconductor substrate of a second wafer (the handle wafer). The dielectric layer of the donor wafer is then bonded to the dielectric layer of the handle wafer. The bonded dielectric layers form the BOX layer.
• FIG. 1 a partial cross sectional view of an integrated circuit 100 at an intermediate stage in a fabrication process is depicted.
• ESL 109 has been formed overlying a semiconductor bulk 104 of a first wafer, referred to herein as donor wafer 90.
• ESL 109 is preferably a relatively thin film having a thickness in the range of approximately 5 to 30 nm and is still more preferably, having a thickness that is less than or equal to approximately 10 nm.
• the composition of ESL 109 is chosen primarily for its etch characteristics. More specifically, ESL 109 is preferably of a material that is etch selective with respect to the material of semiconductor bulk 104.
• a material is etch selective with respect to another material if an etch process can be found that is highly selective to one of the material.
• the selectivity between ESL 109 and semiconductor bulk 104 is preferably in excess of 10:1.
• a second consideration for ESL 109 is the effect ESL 109 may have on transistor performance.
• semiconductor bulk 104 is crystalline silicon and ESL layer is a semiconductor compound that is pseudomorphic with respect to semiconductor bulk 104.
• a silicon germanium compound Si(i. ⁇ )Ge ⁇
• the germanium content (X) of ESL 109 in these embodiments is preferably in the range of approximately 5 to 15 % and, in some embodiments, is a function of the germanium content in a subsequently formed silicon germanium source/drain stressor as described below with respect to FIG. 9.
• a dielectric layer 86 is deposited or otherwise formed overlying ESL 109.
• Dielectric layer 86 will serve as at least a portion of the BOX layer in the finished integrated circuit.
• a thickness of dielectric layer 86 is preferably in the range of approximately 20 to 200 nm.
• Dielectric layer 86 may be a CVD silicon oxide layer such as a silicon oxide layer conventionally formed using a TEOS (tetraethylorthosilicate) source.
• ion implantation 82 is performed to form an implant damage layer 84 within semiconductor bulk 104.
• Implant damage layer 84 divides semiconductor bulk 104 into a first region 105 that is adjacent to ESL 109 and a second region 107 that is distal from ESL 109.
• implant damage layer 84 is created by implanting hydrogen into semiconductor bulk 104 using an implant dose of 5 x 10 16 cm "2 or more.
• handle wafer 94 is bonded, as indicated by reference numeral 92, to donor wafer 90 to form integrated circuit wafer 101.
• the depicted implementation of handle wafer 94 includes a dielectric layer 96 overlying a bulk portion 98.
• the dielectric layer 96 of handle wafer 94 is preferably of the same or a similar dielectric material as dielectric layer 86 of donor wafer 90.
• Bulk portion 98 of handle wafer 94 is preferably a semiconductor material such as crystalline silicon.
• Implant damage layer 84 facilitates a cleaving process 113, illustrated in FIG. 5, in which the second region 107 of semiconductor bulk 104 "below" implant damage layer 84 is severed from the remainder of donor wafer 90 and discarded.
• ion implantation 82 uses an energy and implant species that damage layer 84 is a relatively narrow band displaced from ESL 109 by approximately 50 nm. Suitable implant species include hydrogen.
• first region 105 of donor wafer 90 will serve as an active layer of integrated circuit 100 in which transistors and possibly other devices are formed. Accordingly, first region 105 is sometimes referred to herein as active layer 105.
• dielectric layer 86 of donor wafer 90 is bonded to dielectric layer 96 of handle wafer 94 to form a BOX layer 102 in integrated circuit wafer 101 using thermal bonding or another known bonding technique.
• integrated circuit wafer 101 as depicted in FIG. 6, may be described as an SOI wafer with an ESL 109 located between semiconductor active layer 105 and BOX layer 102.
• ESL 109 facilitates stressor formation processing (described in greater detail below) by enabling a robust etch of active layer 105 without etching to BOX layer 102.
• Isolation structures 106 define lateral boundaries of an active region or transistor region 103 in active layer 105.
• Gate electrode 110 includes a conductive gate electrode 112 overlying a gate dielectric 114 and spacer structures (spacers) 116 on sidewalls of gate electrode 112.
• the lateral boundaries of gate electrode 112 approximately define lateral boundaries of a transistor channel 115 and source/drain regions 117 disposed on either side of transistor channel 115 in active layer 105.
• Gate electrode 112 is an electrically conductive structure of doped polysilicon, a metal or metal suicide material, or a combination thereof.
• Gate dielectric 114 is preferably a thermally formed silicon dioxide or a high K dielectric such as hafnium oxide (HfO 2 ).
• Spacers 116 are preferably silicon nitride, silicon oxide, or a combination thereof. A source/drain extension type implantation may be conducted prior to the spacer formation.
• the source/drain regions 117 of active layer 105 have been substantially removed to create source/drain voids 120 that expose an upper surface of ESL 109.
• removal of source/drain regions 117 includes an etch process that is highly selective to ESL 109.
• a highly selective etch refers to an etch process having a relative etch rate in excess of 10:1 between the two materials of primary concern (i.e., the layer being etched and the ESL).
• the etch process that removes source/drain regions 117 may include a wet etch component using an NH 4 OHiH 2 O solution heated to approximately 75 C.
• source/drain stressors 130 have a lattice constant that differs from the lattice constant of the original active layer 105 that occupies the majority of transistor channel 115.
• Source/drain stressors 130 induce strain to the transistor channel 115 and, preferably, improve the mobility of the relevant carrier in the transistor channel.
• a source/drain stressor 130 that creates compressive stress in transistor channel 115 improves the hole mobility thereby improving the performance of PMOS transistors.
• source/drain stressors 130 preferably create tensile stress in transistor channel 115 improve the electron mobility and NMOS transistor performance.
• a suitable source/drain stressor material for PMOS transistors is silicon germanium while a source source/drain stressor material for NMOS transistors is silicon carbon.
• source/drain stressor 130 is a silicon germanium compound (Si ( i. ⁇ ) Ge ⁇ ) and ESL 109 is a silicon germanium compound (Si(i. ⁇ )Ge ⁇ ) where X and Y differ.
• Y is greater than X in this embodiment to enhance the compressive effects of source/drain stressor 130.
• the stressor film may be doped for proper conductivity type. The doping process can be done in situ during stressor film epitaxial growth by providing proper reactant sources, or it can be done after stressor film growth with implantation. An anneal process can be performed after the doping process.
• the illustrated embodiment include bonding a donor wafer having a Si/SiGe/Oxide stack to a handle wafer having an Oxide/Si stack to form the integrated circuit wafer
• other implementations may create the SiGe etch stop layer by starting with an ultra thin body (UTB) SiGe-on-insulator (SGOI) wafer and growing the Si active layer using epitaxy.
• UTB ultra thin body
• SGOI SiGe-on-insulator
• Still other processes may start with a conventional SGOI wafer having a SiGe layer on top of the isolation BOX, thin down the SiGe top layer to form the ESL and then grow a Si active layer using epitaxy. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention.

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Thin Film Transistor (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

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• 2006
  • 2006-03-30 US US11/393,340 patent/US7494856B2/en not_active Expired - Fee Related
• 2007
  • 2007-02-22 WO PCT/US2007/062559 patent/WO2007117775A2/en not_active Ceased
  • 2007-02-22 KR KR1020087023819A patent/KR20080108498A/ko not_active Withdrawn
  • 2007-02-22 EP EP07757316A patent/EP2005477A4/en not_active Withdrawn
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