TWI441190B - 三維晶片之差動感測及矽晶穿孔時序控制結構 - Google Patents

三維晶片之差動感測及矽晶穿孔時序控制結構 Download PDF

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TWI441190B
TWI441190B TW099136766A TW99136766A TWI441190B TW I441190 B TWI441190 B TW I441190B TW 099136766 A TW099136766 A TW 099136766A TW 99136766 A TW99136766 A TW 99136766A TW I441190 B TWI441190 B TW I441190B
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Wei Cheng Wu
Yen Huei Chen
Meng Fan Chang
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Nat Univ Tsing Hua
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Description

三維晶片之差動感測及矽晶穿孔時序控制結構
本發明係關於一種三維堆疊晶片元件，特別係有關於一種三維晶片之差動感測及矽晶穿孔時序控制結構。
進來可攜式電子設備，例如行動電話與非揮發性半導體記憶媒體(例如積體電路記憶卡)，已縮小尺寸來設計或製造，並且新增的需求欲減少用於設備與媒體中的零件數目並縮小其大小。因此，在半導體工業中，積體電路之封裝技術已經進展至符合小型化與接著可靠性的需求。舉例而言，小型化的需求而導致封裝技術的加速發展，使其具有與一半導體晶片的相似尺寸。再者，接著可靠性於封裝技術上的重要性在於可以提升接著製程的效率，以及於接著製程完成之後提高機械與電性的可靠度。因此，已有相當多的工作在於發展有效率地封裝半導體晶片。符合上述需求之封裝包括：具有約略等於半導體晶片的封裝大小之晶片尺寸封裝(CSP)，有多重半導體晶片納入一單一封裝之多重晶片封裝，以及多重封裝體堆疊及結合於一單片構裝之堆疊封裝。
隨著技術的發展，回應記憶體與其相關的所需儲存容量的增加，而提出堆疊型態的半導體元件(多重晶片元件)，其具有半導體積體電路晶片堆疊一起。換言之，其係提供至少二個半導體積體電路元件堆疊所形成之堆疊型態半導體元件，每一個具有規格並包括一半導體積體電路晶片，其中每一個半導體積體電路元件包括一導體穿過其中，且半導體積體電路元件藉由導體電性連接，而上述規格值包括最上層或最下層半導體積體電路元件的大小是最大的或最小的。因此，堆疊型態半導體元件具有複數個晶片堆疊於一垂直方向。在堆疊型態半導體元件中，晶片係透過例如穿過晶片的插塞(plugs)而電性連接在一起。因此，選擇適當的一個相同結構之堆疊記憶體晶片是一份重要的工作。若一個堆疊型態半導體元件完成製造，晶片可以個別地被操作測試，使得僅僅正常的晶片能夠被挑選出並堆疊。
一種提供垂直連接的技術稱為矽晶穿孔(TSV)，其已經成為三維堆疊元件的一個有前景的解決方案。上述技術中，垂直連接線係穿過晶圓而形成，而使堆疊晶片之間得以溝通。一個相關的論文可以參考標題為“利用矽晶穿孔技術之8十億位元三維DDR3動態隨機存取記憶體”(IEEE,JOURNAL OF SOLID-STATE CIRCUITS,VOL. 45,NO. 1,JANUARY 2010)。在此篇論文中，具有矽晶穿孔三維動態隨機存取記憶體之提出係為了克服傳統的模組方法的限制。其亦揭露如何設計該結構與資料路徑。其也揭露包括三維技術之矽晶穿孔連接性檢查與修復方法，以及功率雜訊降低方法。矽晶穿孔可以透過簡單的方式於出廠之後形成，因此無需於正常的製程期間另加特別的製程整合。晶片識別係通常地分配。
在資料溝通系統中，典型地係利用一於第一時脈下操作的傳輸元件以及一於第二時脈下操作的獨立接收元件。通常而言，傳輸元件與接收元件具有一時脈速度差。此時脈速度差導致接收者看到進來的資料比預期的更快或更慢，此處稱為“時序偏移”。對於封包基礎溝通系統而言，若封包期間的可能時序偏移最大量小於一符號期間，則時脈速度差可以被忽略。美國第7,003,056專利揭露一種符號時序追蹤及方法，其係利用時序追蹤以較正由於傳輸時脈與接收時脈之頻率差而來的時序偏移。藉由時序追蹤，三個連續取樣的相關值可以利用接收訊號與回復符號而計算，然後計算其總和。此外，靜態隨機存儲記憶體廣泛地用於速度具有重要性的應用中，例如快取記憶體典型地係置於最近於個人電腦中的處理器或中央處理器。然而，其內部電路的時序可能嚴重地影響了靜態隨機存儲記憶體的速度與效率。舉例而言，位元線充電期間包括相當可觀的讀/寫週期，並且感測放大器使用對於靜態隨機存儲記憶體的整體功率消耗貢獻是顯著的。在早期的靜態隨機存儲記憶體設計中，讀/寫週期係基於一外部產生的脈衝訊號。另一習知技術揭露於美國第7,003,056專利中，其包括自定時電路以降低一半導體記憶體的寫入週期。一虛擬記憶體晶胞具有相同時序需求以作為功能晶胞，且相關的寫入邏輯加至記憶體元件之標準電路。虛擬寫入晶胞接收相同控制訊號用以寫入資料至該記憶體的功能晶胞，且當寫入存取結束之後發出一完成訊號，致使寫入週期終結。此電路與方法允許寫入週期時間降低至最小有效值，獨立於讀取週期時間。這潛在增加了記憶體元件的整體操作速度。
本發明提供一種三維堆疊元件之差動感測及矽晶穿孔時序控制以改善負載問題，如圖一所示。由負載問題所導致的時間延遲於較多晶片層是更糟的。因此，本發明提供一新穎的三維晶片感測及時序控制之方法以解決該問題。
本發明之一觀點在於提供一種三維積體電路之差動感測及矽晶穿孔時序控制之方法與結構。
三維積體電路之差動感測及矽晶穿孔時序控制結構，包括一相對高能力驅動器(緩衝器)，一虛擬負載耦接相對高能力驅動器(緩衝器)以傳遞一時序閃控訊號，一檢測電路耦接虛擬負載。一差動訊號產生結構耦接一相對低能力驅動器(緩衝器)以產生一差動訊號。一感測電路耦接差動訊號產生結構。當一主動訊號達至一觸發點時，檢測電路啟動感測電路。
差動訊號產生結構包括一對高負載結構耦接一相對低能力驅動器，一反向器配置於該對相對高負載結構之一與相對低能力驅動器之間。該對相對高負載結構包括一對矽晶穿孔。虛擬負載包括一矽晶穿孔。
相對高能力驅動器之傳輸速度大於相對低能力驅動器之傳輸速度。在一實施例中，相對高能力驅動器之傳輸速度為x倍相對低能力驅動器之傳輸速度。感測電路包括一感測放大器、一比較器或一操作放大器。
在上述三維觀點之架構下，一種具有複數層之堆疊元件之差動感測及矽晶穿孔時序控制結構，包括：一堆疊元件之第一晶片層，包括一檢測電路與一相對高能力驅動器水平耦接檢測電路。一感測電路，藉由一水平導線耦接檢測電路。一第一差動訊號驅動器，於第一晶片層中水平耦接感測電路。一堆疊元件之第N晶片層，包括一第N相對高能力驅動器與一第N差動訊號驅動器形成於第N晶片層之上，N為大於1的自然數，其中第N相對高能力驅動器係透過一垂直相對低負載矽晶穿孔與(N-2)相對高負載矽晶穿孔作為虛擬負載而垂直耦接第一相對高能力驅動器，相對低負載矽晶穿孔與(N-2)相對高負載矽晶穿孔係從第N晶片層至第一晶片層而穿過堆疊元件，其中相對低負載矽晶穿孔與(N-2)相對高負載矽晶穿孔形成於一共享結構中，其中第N差動訊號驅動器係透過一對相對低負載矽晶穿孔與(N-2)對相對高負載矽晶穿孔而垂直耦接第一差動訊號驅動器，該對相對低負載矽晶穿孔與該(N-2)相對高負載矽晶穿孔係從第N層至第一層而穿過堆疊元件，每一相對低負載矽晶穿孔係形成於第一與第二晶片層之間，每一相對高負載矽晶穿孔係形成於堆疊元件之任一相鄰二晶片層之間，藉此當一主動訊號達至一觸發點時，檢測電路啟動感測電路。
本發明將配合其較佳實施例與隨附之圖示詳述於下。應可理解者為本發明中所有之較佳實施例僅為例示之用，並非用以限制。因此除文中之較佳實施例外，本發明亦可廣泛地應用在其他實施例中。且本發明並不受限於任何實施例，應以隨附之申請專利範圍及其同等領域而定。
本發明係有關於三維晶片之差動感測及矽晶穿孔時序控制結構，其可以引進於嵌入式揮發性或非揮發性記憶體。在一較佳實施例中，如第二圖所示，本發明揭露一差動感測結構，其包括一驅動器或緩衝器100，耦接一第一高負載結構101。一訊號輸入耦接驅動器或緩衝器100之另一端，一訊號輸出電性連接第一高負載結構，其可透過矽晶穿孔101而形成。本結構更包括一第二高負載結構(矽晶穿孔)210a與第三高負載結構(矽晶穿孔)210b，上述第二矽晶穿孔210a與第三矽晶穿孔210b二者依設計考量可以為平行配置結構。亦可以利用其他結構配置。訊號輸入耦接第二矽晶穿孔210a，而一反向器200配置於訊號輸入與第三矽晶穿孔210b之間。接下來，一感測電路220分別耦接第二矽晶穿孔210a與第三矽晶穿孔210b。訊號輸出耦接感測電路220之另一端。第二圖之差動感測結構中亦分別顯示VDD時序圖。對於第一矽晶穿孔101而言，其觸發點(trigger point)在於VDD的一半，若觸發點水平延伸以達到VDD時序圖的A點，則讀出時間即為時間軸與從A點垂直延伸線之交叉點。類似地，對於第二矽晶穿孔210a與第三矽晶穿孔210b而言，其感測界限較高於觸發點，亦即高於二分之一VDD。因此，讀出將於VDD時序線之上，其將於訊號線與VDD時序線之間。
參考第三圖，其顯示本發明之一較佳實施例。其顯示不同感測之矽晶穿孔時序控制，本結構包括一相對高位準驅動器或緩衝器300耦接一具有高負載之虛擬矽晶穿孔(虛擬負載)310。一時序閃控訊號(timing strobe signal)耦接驅動器或緩衝器300之另一端，一檢測電路315電性連接虛擬矽晶穿孔(虛擬負載)310。此差動訊號結構包括一對高負載結構，在一例子中，此對高負載結構可以由一對矽晶穿孔410a與矽晶穿孔410b所形成，該對矽晶穿孔410a與矽晶穿孔410b分別透過相對低位準驅動器(緩衝器)405a與405b而耦接訊號輸入。值得注意的是，一反向器400配置於訊號輸入與相對低位準驅動器(緩衝器)405b之間。接下來，一感測電路420分別耦接該對高負載結構二者。訊號輸出耦接感測電路420之另一端。前述檢測電路315耦接感測電路420。較佳的是，時序閃控訊號幾乎與訊號輸入相同。在一較佳實施例中，相對高位準驅動器(緩衝器)300具有數倍效能於相對低位準驅動器(緩衝器)405a或405b。
請參考第三圖，其接著圖示矽晶穿孔差動感測之時序控制。起始步驟在於輸入時序閃控訊號至相對高位準驅動器(緩衝器)。真實訊號輸入至相對低位準驅動器(緩衝器)405a與405b。經過反向器400之訊號將從初始輸入訊號反向並延遲，反向訊號波形可以從第三圖之右上部分看出來。因此，經由反向器400而到達高負載結構410b之訊號將被反向。相反地，沒有經過反向器400而到達另一高負載結構410a之訊號仍維持相同。此時感測電路420係正常關閉。由於負載是重的，因此由差動訊號傳遞。當差動訊號之差大於100mV(0.1伏特)，接下來開啟感測電路420，因此決定數位狀態為1或0。
100mV(0.1伏特)的差係藉由電路決定，其具有虛擬負載310耦接檢測電路315。VDD時序圖可以參考第二與第三圖之圖示。該圖示意謂著訊號穿過虛擬負載310。該對高負載結構410a與410b於VDD時序圖中的輸出顯示於第二圖與第三圖之右邊。一虛擬訊號由虛擬負載310所複製以傳遞一眾所周知的主動訊號，一數(x)倍能力的驅動器300引進至虛擬負載310。假定VDD為1.8伏特，則觸發點為VDD的一半，即0.9伏特。結果，當差動訊號之差大於100mV(0.1伏特)，虛擬負載的訊號達至觸發點，因此x的值為9。其意謂著虛擬負載310的傳輸速度比該對差動訊號結構更大。類似地，若VDD為1伏特，則x值為5。
當主動訊號，於圖三之步驟二中，達至觸發點，檢測電路315應盡可能早地打開感測電路420。在一較佳實施例中，檢測電路315係藉由至少一反向器形成，以檢測產生突波，於圖三之步驟三中。最重要之一者係反向器需符應此感測時序。感測電路420可以為一感測放大器或一比較器或一操作放大器。最後，訊號從感測電路輸出，於圖三之步驟四中。負載問題可以容易地藉由矽晶穿孔時序控制與差動感測結構而得到克服。
第四圖顯示本發明之三維結構，三維堆疊元件包括複數個堆疊晶片層，其包括一個別晶片(未圖示)位於每一晶片層。三維堆疊元件之第一晶片層(第一層)包括一檢測電路315位於一預定區域之內，一相對高能力驅動器300L1平行耦接檢測電路315。一感測電路420配置於第一晶片層之一預定區域，並藉由一水平導線C1耦接檢測電路315。一差動訊號驅動器422L1水平耦接感測電路420。堆疊元件之其他晶片層之結構，除了沒有檢測電路315與感測電路420之外，與第一晶片層類似。三維堆疊元件之第N晶片層(第N層)也包括一第N相對高能力驅動器300LN位於第N層晶片層之指定區域上，一第N差動訊號驅動器422LN亦配置於第N晶片層之上；N為大於1的自然數。第N相對高能力驅動器300LN係透過一垂直相對低負載矽晶穿孔與(N-2)相對高負載矽晶穿孔而垂直耦接第一相對高能力驅動器300L1，其由第四圖之TSV x(N-2)所示，所有的相對低負載矽晶穿孔與(N-2)相對高負載矽晶穿孔係從上至底而穿過堆疊元件，其中相對低負載矽晶穿孔與(N-2)相對高負載矽晶穿孔形成於一共享結構中。類似地，第N差動訊號驅動器422LN係透過一對相對低負載矽晶穿孔與(N-2)對相對高負載矽晶穿孔而垂直耦接第一差動訊號驅動器422L1，所有的相對低負載矽晶穿孔與(N-2)對相對高負載矽晶穿孔係從第n層至第一層而穿過堆疊元件。值得注意的是，每一相對低負載矽晶穿孔係形成於第一與第二晶片層之間。(N-2)相對高負載矽晶穿孔係形成於，除了第一與第二晶片層之間之外，堆疊元件之任一相鄰二晶片層之間。其機制與操作方法已經說明於第三與第四圖中。因此，省略其的多餘的敘述。
一實施例係為本發明之一實例或範例。敘述於說明書中之「一實施例」、「一些實施例」或「其他實施例」係指所描述聯結於此實施例中之一特殊特徵、結構或特性被包含最少一些實施例中，但並非對所有實施例而言皆為必需。「一實施例」或「一些實施例」等不同敘述係指並非必須提及這一些實施例。值得注意的是，於前文敘述關於本發明之特定實施例中，不同特徵有時可集合於一單一實施例、圖式或敘述中係用以簡化說明並助於對本發明一或多種不同方面之理解。然而，此揭露方法不應被用以反映所請求之發明範疇，因而將所述範例中之特徵加入每一請求項中。反之，於下述之申請專利範圍所反映本發明之觀點會少於上述所揭露之單一實施例中的所有特徵。因此，申請專利範圍係涵蓋所述之實施例，且每一請求項本身皆可視為本發明之一獨立實施例。
100、300．．．驅動器或緩衝器
101．．．第一高負載結構
200、400．．．反向器
210a．．．第二高負載結構(矽晶穿孔)
210b．．．第三高負載結構(矽晶穿孔)
220、420．．．感測電路
310．．．虛擬矽晶穿孔(虛擬負載)
315．．．檢測電路
405a、405b．．．相對低位準驅動器(緩衝器)
410a、410b．．．矽晶穿孔
300L1．．．相對高能力驅動器
C1．．．導線
300LN．．．第N相對高能力驅動器
422L1．．．第一差動訊號驅動器
422LN．．．第N差動訊號驅動器
上述元件，以及本發明其他特徵與優點，藉由閱讀實施方式之內容及其圖式後，將更為明顯：
第一圖顯示根據習知技術之負載問圖。
第二圖顯示根據本發明之三維晶片之差動感測及矽晶穿孔時序控制結構之功能方塊圖。
第三圖顯示根據本發明之三維晶片之差動感測及矽晶穿孔時序控制結構之功能方塊圖。
第四圖顯示根據本發明之三維晶片之差動感測及矽晶穿孔時序控制結構之三維圖示示意圖。
300‧‧‧驅動器或緩衝器
310‧‧‧虛擬矽晶穿孔(虛擬負載)
315‧‧‧檢測電路
400‧‧‧反向器
405a、405b‧‧‧相對低位準驅動器(緩衝器)
410a、410b‧‧‧矽晶穿孔
420‧‧‧感測電路

Claims (10)

  1. 一種具有複數層之堆疊元件之差動感測及矽晶穿孔時序控制結構，包括：一該堆疊元件之第一晶片層，包括一時序檢測電路與一相對高能力驅動器於相同晶片層水平耦接該時序檢測電路；一感測電路，藉由一水平導線於該第一晶片層中耦接該時序檢測電路；一第一差動訊號驅動器，於該第一晶片層中水平耦接該感測電路；以及一該堆疊元件之第N晶片層，包括一第N相對高能力驅動器與一第N差動訊號驅動器形成於該第N晶片層之上，該N為大於1的自然數，其中該第N相對高能力驅動器係透過一垂直相對低負載矽晶穿孔與(N-2)相對高負載矽晶穿孔作為虛擬負載而垂直耦接該第一相對高能力驅動器，該相對低負載矽晶穿孔與該(N-2)相對高負載矽晶穿孔係從該第N晶片層至該第一晶片層而穿過該堆疊元件，其中該相對低負載矽晶穿孔與該(N-2)相對高負載矽晶穿孔形成於一共享結構中，其中該第N差動訊號驅動器係透過一對相對低負載矽晶穿孔與(N-2)對相對高負載矽晶穿孔而垂直耦接該第一差動訊號驅動器，該對相對低負載矽晶穿孔與該(N-2)相對高負載矽晶穿孔係從第N層至第一層而穿過該堆疊元件，每一該相對低負載矽晶穿孔係形成於該第一與第二晶片層之間，每一該相對高負載矽晶穿孔係形成於該堆疊元件之任一相鄰二晶片層之間，藉此當一主動訊號達至一觸發點時，該時序檢測電路啟動該感測電路。
  2. 如請求項1所述之具有複數層之堆疊元件之差動感測及矽晶穿孔時序控制結構，更包括一相對低能力驅動器與一反向器，該反向器配置於該N對相對高負載矽晶穿孔之一與該相對低能力驅動器之間，該相對高能力驅動器之傳輸速度大於該相對低能力驅動器之傳輸速度，該相對高能力驅動器之傳輸速度為x倍相對低能力驅動器之傳輸速度，該x端視該感測電路的感測界限且x大於一。
  3. 如請求項1所述之具有複數層之堆疊元件之差動感測及矽晶穿孔時序控制結構，其中該時序檢測電路包括至少一反向器。
  4. 如請求項1所述之具有複數層之堆疊元件之差動感測及矽晶穿孔時序控制結構，其中該感測電路包括一感測放大器、一比較器或一操作放大器。
  5. 如請求項1所述之具有複數層之堆疊元件之差動感測及矽晶穿孔時序控制結構，其中該相對低負載矽晶穿孔之一與該(N-2)相對高負載矽晶穿孔耦接一時序閃控訊號，該對相對低負載矽晶穿孔與該(N-2)對相對高負載矽晶穿孔耦接一輸入訊號。
  6. 一種具有複數層之堆疊元件之差動感測及矽晶穿孔時序控制結構，包括：一該堆疊元件之第一晶片層，包括一時序檢測電路與一相對高能力緩衝器水平耦接該檢測電路；一感測電路，藉由一水平導線於該第一晶片層中耦接該檢測電路；一第一差動訊號緩衝器，水平耦接該感測電路；以及一該堆疊元件之第N晶片層，包括一第N相對高能力緩衝器與一第N差動訊號緩衝器形成於該第N晶片層之上，該N為大於1的自然數，其中該第N相對高能力緩衝器係透過一相對低負載矽晶穿孔與(N-2)相對高負載矽晶穿孔作為虛擬負載而垂直耦接該第一相對高能力緩衝器，該相對低負載矽晶穿孔與該(N-2)相對高負載矽晶穿孔係從該第N晶片層至該第一晶片層而穿過該堆疊元件，其中該相對低負載矽晶穿孔與該(N-2)相對高負載矽晶穿孔形成於一共享結構中，其中該第N差動訊號緩衝器係透過一對相對低負載矽晶穿孔與(N-2)對相對高負載矽晶穿孔而垂直耦接該第一差動訊號緩衝器，該對相對低負載矽晶穿孔與該(N-2)相對高負載矽晶穿孔係從第N層至該第一層而穿過該堆疊元件，每一該相對低負載矽晶穿孔係形成於該第一與第二晶片層之間，每一該相對高負載矽晶穿孔係形成於該堆疊元件之任一相鄰二晶片層之間，藉此當一主動訊號達至一觸發點時，該時序檢測電路啟動該感測電路。
  7. 如請求項6所述之具有複數層之堆疊元件之差動感測及矽晶穿孔時序控制結構，更包括一相對低能力緩衝器與一反向器，該反向器配置於該N對相對高負載矽晶穿孔之一與該相對低能力緩衝器之間，該相對高能力緩衝器之傳輸速度大於該相對低能力緩衝器之傳輸速度，該相對高能力緩衝器之傳輸速度為x倍該相對低能力緩衝器之傳輸速度。
  8. 如請求項6所述之具有複數層之堆疊元件之差動感測及矽晶穿孔時序控制結構，其中該檢測電路包括至少一反向器。
  9. 如請求項6所述之具有複數層之堆疊元件之差動感測及矽晶穿孔時序控制結構，其中該感測電路包括一感測放大器、一比較器或一操作放大器。
  10. 如請求項6所述之具有複數層之堆疊元件之差動感測及矽晶穿孔時序控制結構，其中該相對低負載矽晶穿孔之一與該(N-2)相對高負載矽晶穿孔耦接一時序閃控訊號，該對相對低負載矽晶穿孔與該(N-2)對相對高負載 矽晶穿孔耦接一輸入訊號。
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