TWI438875B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TWI438875B
TWI438875B TW100116105A TW100116105A TWI438875B TW I438875 B TWI438875 B TW I438875B TW 100116105 A TW100116105 A TW 100116105A TW 100116105 A TW100116105 A TW 100116105A TW I438875 B TWI438875 B TW I438875B
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Taiwan
Prior art keywords
substrate
mark
semiconductor substrate
semiconductor
covering
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TW100116105A
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English (en)
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TW201205735A (en
Inventor
yan fu Lin
Jing Cheng Lin
Wen Chih Chiou
Shin Puu Jeng
Chen Hua Yu
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Taiwan Semiconductor Mfg
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Publication of TW201205735A publication Critical patent/TW201205735A/zh
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Publication of TWI438875B publication Critical patent/TWI438875B/zh

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Description

半導體裝置及其製造方法
本發明係有關於一種半導體製造的系統及方法，特別是有關於一種提供遮覆標記(cover mark)於半導體晶片的系統及方法。
半導體裝置，例如半導體晶片，可利用覆晶技術而貼附於一基底上。在此製程中，一連串的連接器，例如焊球，形成於半導體晶片的一側，且接著將半導體晶翻轉(flipped)，使焊球與下方的基底接觸。接著進行回流(reflow)製程，以回流焊球而在半導體晶片與下方基底之間形成必需的電性連接。接著將底膠(underfill)材料填於半導體晶片與基底之間，以對回流的焊球施加機械性及化學性的保護。
在一些範例中，底膠材料不僅密封住半導體晶片與基底之間區域，且還從半導體晶片側向延伸而覆蓋大於半導體晶片本身的基底區域。當半導體晶片的尺寸越降越小，上述底膠延伸變得更為關鍵，因為過量的底膠材料會不當佔用了基底的有用區域。
再者，由於半導體晶片在放置於基底上之前進行翻轉，因此很難精確地將焊球對準於下方基底上對應的連接點。此問題在半導體晶片與基底之間造成誤對準，而誤對準造成未連接的電源線或失效的信號線，最糟的是會造成半導體晶片與基底之間的通信完全失效。
透過下述實施例，其在基底上提供遮覆標記，可解決或防止上述或其他的問題，且獲得技術上的利益。
在本發明一實施例中，一種半導體裝置，包括：一基底，具有一第一表面，基底包括一貼合區，貼合區具有至少一個接觸墊；以及至少一個遮覆標記順應著第一表面，遮覆標記為看的見得且包括自貼合區離開的一距離指標。
本發明另一實施例中，一種半導體裝置，包括：一基底，具有一第一表面，基底包括一第一遮覆標記，位於第一表面的一第一區周圍；以及一半導體基底，貼合至第一區，半導體基底包括一第二遮覆標記，對準第一遮覆標記且順應著一第二表面，背離第一表面。
本發明又一實施例中，一種半導體裝置製造方法，包括：提供一基底；在基底的一第一表面上形成一第一遮覆標記；在基底的第一表面上方放置一半導體基底；以及在該基底與該半導體基底之間放置一底膠材料，底膠材料自基底與半導體基底之間的區域朝向第一遮覆標記延伸。
以下說明本發明實施例之製作與使用。然而，可輕易了解本發明實施例提供許多合適的發明概念而可實施於廣泛的各種特定背景。所揭示的特定實施例僅僅用於說明以特定方法製作及使用本發明，並非用以侷限本發明的範圍。
以下根據一特定背景說明本實施例，亦即，用於具有覆晶配置的半導體晶片的遮覆標記。然而，這些實施例也可應用於其他類型的標記。
請參照第1A及1B圖，其分別繪示出具有覆晶配置的半導體基底101、基底103及接觸凸塊(bump)105剖面及平面示意圖，其中第1A圖係繪示出沿第1B圖中A-A’線的剖面示意圖。半導體基底101可為半導體晶片，其包含內部及/或上方具有電子裝置的半導體基底，且包含(但不一定必須包含)介電層及導電層，以提供電子裝置之間的連接及佈線。半導體基底101上方可具有任何數量的交替排列的導電及介電層，但通常為具有3至12層交替排列的導電及介電層。
基底103為半導體基底101結構上及電性上的支撐體。在一實施例中，基底103可為印刷電路板，其含有導電佈線，以規劃通往及來自半導體基底101的電子信號以及電源與接地的連接。舉例來說，電子信號可通往或來自位於基底103上的其他裝置(未繪示)，使半導體基底101及其他裝置可一同運作而執行所需的功能。然而，任何所屬技術領域中具有通常知識者可以理解基底103並非限定於以上所討論的印刷電路板，而印刷電路板也不是作為半導體基底101結構上及電性上的支撐的唯一方式，也可以採用任何其他適當的支撐基底，例如另一半導體基底101，其在適當位置上具有電性連接點以接收來自半導體基底101、轉接板(interposer)、高密度內連線或封裝基底等等的電性連接點。上述的這些基底也含括於本實施例的範圍之內。
接觸凸塊105形成於半導體基底101與基底103之間。接觸凸塊105的材質可包括錫或其他適當的材料，例如銀、銅、鋁、金或鎳。在一實施例中，接觸凸塊105為錫焊料凸塊。接觸凸塊105的製做為先透過一般的方法，例如蒸鍍、電鍍、印刷、焊料轉移(solder transfer)、植球等，在半導體基底101上形成一錫層，其厚度約在20至100微米(μm)的範圍。在半導體基底101上形成一錫層之後，進行回流，以將材塑形成所需的凸塊外形。
在半導體基底101上形成接觸凸塊105之後，可透過覆晶製程，將半導體基底101貼附於基底103上。在此製程中，半導體基底101被翻轉，使接觸凸塊105面向基底103。接觸凸塊105面向基底103之後，對準接觸凸塊105，使接觸凸塊105與接觸墊109作機械性及電性接觸，藉以提供基底103與半導體基底101之間的電性連接。在一實施例中，接觸凸塊105為焊料凸塊，在形成電性接觸之後，為了將半導體基底101貼附至基底103，可回流接觸凸塊105。
另外，任何所屬技術領域中具有通常知識者可以理解第1A及1B圖所繪示出的覆晶排置以及以上所述並非上述實施例中唯一可應用排置，而上述的排置並非用以限定本實施例。也可採用其他類型的排置，例如矽通孔電極(through silicon vias,TSVs)或是這些排置的組合(例如，TSV與覆晶排置)。上述的這些排置或是其他適當的排置類型也含括於本實施例的範圍之內。
如第1A及1B圖所示，遮覆標記107位於基底103上。遮覆標記107可供觀測者之用，作為底膠材料201(未繪示於第1A及1B圖，但繪示於第2A至2B圖，且後續有更完整的說明)要從半導體基底101下方延伸多遠的指標，從遮覆標記107的位置可輕易追蹤底膠材料201的位置，而不需要額外非必需底膠材料201來確保有足夠的封膠，進而減少任何非必需的底膠材料201的遮覆。
遮覆標記107可位於基底103內且鄰近於貼合區115(以虛線表示)，其用以容納半導體基底101。在一實施例中，在放置半導體基底101之後，從上方觀示半導體基底101及基底103時，遮覆標記107從半導體基底101延伸。另外，遮覆標記107包括一直線部113，具有條紋(hash)標記111沿著直線部113並以第一距離d1 (約在50至500微米的範圍，例如為100微米)的規律長度作為間隔。一旦將底膠材料201放至於半導體基底101與基底103之間，條紋標記111可容許底膠材料201進行精確的測量。遮覆標記107可透過相同於形成基底103上的其中一膜層(例如，含有接觸墊109的膜層)所使用的微影製程而形成於基底103內。在一實施例中，遮覆標記107由導體所形成，例如鋁，且與基底103的接觸墊109同時形成。在本實施例中，遮覆標記107的製做為使用一沉積製程(例如濺鍍(sputtering)、化學氣相沉積(chemical vapor deposition,CVD)、電鍍、鋼板印刷(stencil printing)或噴墨印刷(jetting printing))來形成一材料層(未繪示)，而部分的材料層可透過適當的製程(例如，微影及蝕刻製程)除去而同時形成遮覆標記107及接觸墊109。利用上述製程，遮覆標記107的製做無需分開的製程步驟。
然而，任何所屬技術領域中具有通常知識者可以理解上述的結構及製程並非唯一適當的結構及製程，且並非用於限定本實施例。也可採用任何適當的結構及製程來形成可與周遭材料區別的遮覆標記107。舉例來說，遮覆標記107也可由虛設凸塊(dummy bump)、重佈局線(redistribution line)、重佈局連接窗(redistribution via)、接觸墊、虛設矽通孔電極、開口溝槽/孔洞/圖案或其組合所構成。上述所有結構及其製程及其他適當的結構與製程都可用於遮覆標記107。
另外，儘管以上所述的遮覆標記107露出於基底103的最外層，然而本實施例並非局限於此。遮覆標記107可由基底103的任何膜層所構成且位於任何膜層上，只要遮覆標記107通過任何中介層仍為可視的。舉例來說，遮覆標記107可形成於基底103的最外層的下方膜層上方，接著覆蓋一透明鈍化保護(passivation)層(未繪示)。上述步驟可保護遮覆標記107，同時也保有指示底膠寬度的能力。
請參照第2A及2B圖，其分別繪示出填入底膠材料201之後，半導體基底101及基底103剖面及平面示意圖，其中第2A圖係繪示出沿第2B圖中B-B’線的剖面示意圖。底膠材料201可注入或形成於半導體基底101與基底103之間的空間。舉例來說，底膠材料201可包括液態環氧化物，其施加於半導體基底101與基底103之間，接著進行固化使其硬化。底膠材料201可用於防止形成於接觸凸塊105內的裂縫，其中裂縫通常會引起熱應力。
另外，底膠材料201可為形成於半導體基底101與基底103之間的可變形膠或矽橡膠，用以防止接觸凸塊105內發生裂縫。可透過將膠或橡膠注入或放置於半導體基底101與基底103之間而形成膠或橡膠。可變形膠或矽橡膠可在後續製程進行期間提供較大的應力釋放。
在施加底膠材料201期間或之後，底膠材料201可透過參照遮覆標記107而檢視底膠材料201的位置。透過觀測或測定遮覆標記107在視覺上有多少被底膠材料201遮蓋或隱藏，可決定出底膠材料201的總量及位置。舉例來說，可採用光學顯微鏡來進行檢視，然而也可採用其他適當方法來測定有多少遮覆標記107被底膠材料201遮蓋。
為了幫助測定，如第1A至2B圖所示，遮覆標記107可包括條紋標記111，其從遮覆標記107(如對照第1A至1B圖所述)向外延伸。當知道條紋標記111的間隔時，例如上述的第一距離d1 ，可從簡單的視覺檢測有多少條紋標記111被遮蓋就可輕易決定出底膠材料201的範圍，如第2A至2B圖所示的實施例，底膠材料201從基底103上的半導體基底101延伸出條紋標記111的一第一距離d1 。
第3A至3J圖係繪示出遮覆標記107的各種類型及外形。舉例來說，第3A至3B圖所繪示出的遮覆標記107為”L”形，且從半導體基底101(上視)的角落向外延伸。第3A圖係繪示出遮覆標記107為連續線的實施例，而第3B圖係繪示出相似的實施例，其中遮覆標記107為不連續線。在上述實施例中，遮覆標記107具有一長度為一第二距離d2 ，其在50至500微米的範圍，例如100微米，而彼此間隔為一第三距離d3 ，其在50至500微米的範圍，例如100微米。
第3C至3D圖所繪示出的遮覆標記107為同軸方形，且從半導體基底101(上視)的徑向向外延伸。第3C圖係繪示出遮覆標記107為連續線的實施例，而第3D圖係繪示出相似的實施例，其中遮覆標記107為不連續線。在上述實施例中，遮覆標記107彼此間隔為一第四距離d4 ，其在50至500微米的範圍，例如100微米，然而遮覆標記107的間隔也可大於或小於上述數量。另外，在不同的遮覆標記107之間也可具有不同的間隔。
第3E至3F圖所繪示出的實施例相似於第3A圖的實施例(遮覆標記107為”L”形，且位於半導體基底101的角落)，但額外包含刻度301。刻度301位於基底103上且沿著半導體基底101(上視)的一側，以提供遮覆標記107的觀測者參照之用。在一實施例中，刻度301可從一遮覆標記107沿著平行半導體基底101的路徑延伸，並終止於位在半導體基底101的相對角落的另一遮覆標記107。另外，刻度301可額外包含條紋標記111，其具有規律的間距(在50至500微米的範圍，例如100微米)，使其有助於距離的測定或估算。
第3F圖所繪示出的實施例相似於第3E圖的實施例，但額外增加數值303。數值303指示出一指標數值或是指示出沿著刻度301的各個距離。在第3F圖所繪示的實施例中(僅為範例說明)，沿著遮覆標記107的第一個條紋標記111為數值100，其表示從遮覆標記107的角落沿著刻度301的距離為100微米處為第一個條紋標記111。另外，如圖所示，每一條紋標記111與前一條紋標記111的距離為100微米，進而提供一觀測者一參照刻度301或線索，以容許觀測者對於放至於半導體基底101與基底103之間的底膠材料201的總量有較佳的估算。
第3G圖係繪示出用於遮覆標記107的另一類型及外形。在本實施例中，遮覆標記107為一組刻度301(請參照第3E至3F圖)，其彼此隔開，且刻度301自半導體基底101向外延伸。刻度301可包括或不包括數值303，其指示出刻度301的每一條紋標記111所在的距離。
第3H圖係繪示出具有三角外形的遮覆標記107。為了減化圖式，僅繪示出沿著半導體基底101兩側邊形成的三角外形標記，然而其可沿著半導體基底101的任何側邊數而形成。三角外形標記的高為第五距離d5 ，其在50至500微米的範圍，例如100微米。而三角外形標記的底寬為第六距離d6 ，其在50至500微米的範圍，例如100微米。
第3I圖係繪示出利用虛設接觸凸塊305形成遮覆凸塊107的實施例。虛設接觸凸塊305可相似於第1A圖中接觸凸塊105的方式而形成於基底103上，除了虛設接觸凸塊305是不作電性連接之外。其本身可連接或不連接至任何的接觸墊109。如圖所示，虛設接觸凸塊305可排成列，平行半導體基底101的側邊(上視)，且這些列以一第七距離d7 彼此隔開，其在50至500微米的範圍，例如100微米。另外，也可將數值303額外形成於虛設接觸凸塊305，以供觀測者參照之用。
第3J圖使用虛設接墊307作為遮覆標記107的實施例。虛設接墊307可於第1A圖中所述的接觸墊109同時形成。然而，由於虛設接墊307為虛設的，因此虛設接墊307無需電性連接至基底103內的其他裝置(未繪示)。虛設接墊307可形成方塊外形，每一側邊具有一第八距離d8 ，其在50至500微米的範圍，例如100微米。另外，虛設接墊307可排列成任何形式，如圖所示，其排成列且平行半導體基底101的一側，其中各個虛設接墊307依一第九距離d9 而彼此隔開，其在50至500微米的範圍，例如100微米。而這些列依一第十距離d10 而彼此隔開，其在50至500微米的範圍，例如100微米。
另外，第3J圖繪示出一第二組遮覆標記107，其形成直連續線309的外形，直連續線309可排置於半導體基底101的一側邊，但不同於排置虛設接墊307的側邊，且與相鄰的半導體基底101的側邊平行。直連續線309具有一長度為一第十一距離d11 ，其在50至500微米的範圍，例如100微米，而其間距P1 在50至500微米的範圍，例如100微米。另外，也可形成數值303以供觀測者參照之用。
任何所屬技術領域中具有通常知識者可以理解上述類型及外形僅為結構及外形的範例，其使用於遮覆標記107，且並非用以侷限於上述結構及外形的實施例。而任何適當的結構及外形都可使用於遮覆標記107，且所有這些結構及外形也含括於本實施例的範圍之內。另外，也可使用不同類型及外形的組合，以提供最好的遮覆標記107，其容易辨認及製造。
第4A至4B圖係分別繪示出根據另一實施例之剖面及平面示意圖，其中第4A圖係為第4B圖中C-C’線的剖面示意圖。在本實施例中，形成於基底103上的遮覆標記107可用於與半導體基底遮覆標記401對合，以輔助半導體基底101與基底103之間的對準。半導體基底遮覆標記401可利用形成第1A至1B圖中遮覆標記107的相似製程而形成於半導體基底101上。然而，形成半導體基底遮覆標記401，使接觸凸塊105對準於接觸墊109時，半導體基底遮覆標記401也對準基底103上的遮覆標記107。即使在對準期間，無法看見接觸凸塊105及接觸墊109，上述排置可提供了觀測者查看適當對準的能力，進而降低因半導體基底101與基底103之間誤對準而發生的錯誤。
另外，在半導體基底遮覆標記401位於半導體基底101的上表面的實施例中，可進行額外製程，以沿著半導體基底101的一或多個側邊延伸(未繪示於第4A至4B圖)。在半導體基底101為半導體晶片的實施例中，半導體晶片可從半導體晶圓分割下來，而額外製程，例如適當的電沉積(electrodeposition)、濺鍍、CVD、雷射蝕刻、蝕刻鋼板印刷、或噴墨印刷或蝕刻，可用於沿著半導體基底101的側邊延伸半導體基底遮覆標記401。透過在半導體基底101的側邊形成半導體基底遮覆標記401，對準製程可更為容易，因為除了正上方觀看外的任何角度觀看，對準標記更為接近在一起。
透過在基底103上形成遮覆標記107，觀測者可更適當地作出底膠材料201的精確定位，進而能更精確地放置底膠材料201。上述精確定位有助於防止底膠材料201佔用比所需的基底103面積更多的面積，且有助於將半導體裝置的尺寸越縮越小。另外，透過使用遮覆標記107作為半導體基底101與基底103之間的對準標記，即使在對準期間，無法看見接觸凸塊105及接觸墊109，操作者進行目視對準時也可降低誤對準的情形。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。舉例來說，遮覆標記可形成各種不同的外形，且遮覆標記的不同組合用於適應任何特定情況。
再者，本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此，本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。
101‧‧‧半導體基底
103‧‧‧基底
105‧‧‧接觸凸塊
107‧‧‧遮覆標記
109‧‧‧接觸墊
111‧‧‧條紋標記
113‧‧‧直線部
115‧‧‧貼合區
201‧‧‧底膠材料
301‧‧‧刻度
303‧‧‧數值
305‧‧‧虛設接觸凸塊
307‧‧‧虛設接墊
309‧‧‧直連續線
401‧‧‧半導體基底遮覆標記
d1 ‧‧‧第一距離
d2 ‧‧‧第二距離
d3 ‧‧‧第三距離
d4 ‧‧‧第四距離
d5 ‧‧‧第五距離
d6 ‧‧‧第六距離
d7 ‧‧‧第七距離
d8 ‧‧‧第八距離
d9 ‧‧‧第九距離
d10 ‧‧‧第十距離
d11 ‧‧‧第十一距離
P1 ‧‧‧間距
第1A至1B圖係分別繪示出根據一實施例之具有覆晶排置的半導體基底及基底剖面及平面示意圖。
第2A至2B圖係分別繪示出根據一實施例之填入底膠之後，半導體基底及基底剖面及平面示意圖。
第3A至3J圖係繪示出根據一實施例之遮覆標記的各種類型及外形。
第4A至4B圖係分別繪示出根據一實施例之以遮覆標記作為對準標記的剖面及平面示意圖。
不同圖式中對應的標號及符號通常對應相同的部件，除非有特別表明。這些圖式清楚繪示出相關的實施例形態但不必然依照比例繪示。
101．．．半導體基底
103．．．基底
107．．．遮覆標記
111．．．條紋標記
113．．．直線部
d1 ．．．第一距離

Claims (10)

  1. 一種半導體裝置，包括：一基底，具有一第一表面，該基底包括一貼合區，該貼合區具有至少一個接觸墊；以及至少一個遮覆標記順應著該第一表面，該遮覆標記包括自該貼合區離開且沿著離開的方向彼此間隔的複數距離指標。
  2. 如申請專利範圍第1項所述之半導體裝置，更包括：一半導體基底，包括至少一接觸凸塊，該接觸凸塊與該接觸墊接觸；一底膠材料，位於該半導體基底與該基底之間，該底膠材料延伸到至少一部分的該遮覆標記的上方；以及至少一個半導體基底遮覆標記，位於該半導體基底上，該半導體基底遮覆標記與對應的該遮覆標記對準。
  3. 如申請專利範圍第1項所述之半導體裝置，其中該遮覆標記更包括：一直線，自該貼合區的一側邊垂直延伸離開；以及多個條紋標記，自該直線延伸離開且平行該貼合區的該側邊，以作為該等距離指標。
  4. 如申請專利範圍第1項所述之半導體裝置，其中該等距離指標具有L外形且鄰近於該貼合區的一角落。
  5. 如申請專利範圍第1項所述之半導體裝置，其中該等距離指標為具有數值的刻度或環繞該貼合區的矩形標記。
  6. 如申請專利範圍第1項所述之半導體裝置，其中該遮覆標記為虛設接觸凸塊。
  7. 一種半導體裝置，包括：一基底，具有一第一表面，該基底包括一第一遮覆標記，位於該第一表面的一第一區周圍，且該第一遮覆標記包括自該第一區離開且沿著離開的方向彼此間隔的複數距離指標；以及一半導體基底，貼合至該第一區，該半導體基底包括一第二遮覆標記，對準該第一遮覆標記且順應著該半導體基底的一第二表面，其背離該第一表面。
  8. 如申請專利範圍第7項所述之半導體裝置，更包括第三、第四及第五遮覆標記，位於該基底的該第一表面，該第一、該第三、該第四及該第五遮覆標記分別位於鄰近該第一表面的不同側邊之處，其中該第三、該第四及該第五遮覆標記分別對準於該半導體基底上多個遮覆標記的其中一個。
  9. 一種半導體裝置製造方法，包括：提供一基底；在該基底的一第一表面上形成一第一遮覆標記；在該基底的該第一表面上方放置一半導體基底；以及在該基底與該半導體基底之間放置一底膠材料，該底膠材料自該基底與該半導體基底之間的區域朝向該第一遮覆標記延伸，且該第一遮覆標記包括順應著該第一表面離開該半導體基底且沿著離開的方向彼此間隔的複 數距離指標。
  10. 如申請專利範圍第9項所述之半導體裝置製造方法，更包括：利用該第一遮覆標記來測定該底膠材料自該半導體基底延伸的一距離；在該半導體基底的一第二表面上形成一第二遮覆標記；以及對準該半導體基底，使該第二表面背離該第一表面，且該第二表面上的該第二遮覆標記對準該第一表面上的該第一遮覆標記。
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TW201205735A (en) 2012-02-01

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