CN102347312A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

Info

Publication number
CN102347312A
CN102347312A CN2011101399034A CN201110139903A CN102347312A CN 102347312 A CN102347312 A CN 102347312A CN 2011101399034 A CN2011101399034 A CN 2011101399034A CN 201110139903 A CN201110139903 A CN 201110139903A CN 102347312 A CN102347312 A CN 102347312A
Authority
CN
China
Prior art keywords
mark
semiconductor
substrate
covers
based end
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2011101399034A
Other languages
English (en)
Other versions
CN102347312B (zh
Inventor
林彦甫
林俊成
邱文智
郑心圃
余振华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN102347312A publication Critical patent/CN102347312A/zh
Application granted granted Critical
Publication of CN102347312B publication Critical patent/CN102347312B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54413—Marks applied to semiconductor devices or parts comprising digital information, e.g. bar codes, data matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/5448—Located on chip prior to dicing and remaining on chip after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
    • H01L2224/1145—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/8113—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/81132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

本发明公开了一种半导体装置及其制造方法，具体是一种测定底胶扩展的系统和方法。该方法包括顺应着一基底的一上表面形成遮覆标记；将一半导体基底贴合至基底的上表面；将底胶材料置入半导体基底与基底之间；以及利用遮覆标记来测定基底的上表面上方的底胶扩展。另外，也可在半导体基底的上表面形成遮覆标记，且位于基底上与半导体基底上的对准标记可在基底与半导体基底的对准期间，一同作为对准标记。本发明通过在基底上形成遮覆标记，有助于防止底胶材料占用比所需的基底面积更多的面积，且有助于将半导体装置的尺寸越缩越小；另外，通过使用遮覆标记作为半导体基底与基底之间的对准标记，也可让操作者在进行目视对准时降低误对准。

Description

半导体装置及其制造方法
技术领域
本发明涉及一种半导体制造的系统及方法，尤其涉及一种提供遮覆标记(cover mark)于半导体芯片的系统及方法。
背景技术
半导体装置，例如半导体芯片，可利用倒装芯片技术而贴附于一基底上。在此工艺中，一连串的连接器，例如焊球，形成于半导体芯片的一侧，且接着将半导体芯片翻转(flipped)，使焊球与下方的基底接触。接着进行回流(reflow)工艺，以回流焊球而在半导体芯片与下方基底之间形成必需的电性连接。接着将底胶(underfill)材料填于半导体芯片与基底之间，以对回流的焊球施加机械性及化学性的保护。
在一些范例中，底胶材料不仅密封住半导体芯片与基底之间区域，且还从半导体芯片侧向延伸而覆盖大于半导体芯片本身的基底区域。当半导体芯片的尺寸越降越小，上述底胶延伸变得更为关键，因为过量的底胶材料会不当占用了基底的有用区域。
再者，由于半导体芯片在放置于基底上之前进行翻转，因此很难精确地将焊球对准于下方基底上对应的连接点。此问题在半导体芯片与基底之间造成误对准，而误对准造成未连接的电源线或失效的信号线，最糟的是会造成半导体芯片与基底之间的通信完全失效。
发明内容
为克服现有技术的缺陷，通过下述实施例，其在基底上提供遮覆标记，可解决或防止上述或其他的问题，且获得技术上的利益。
在本发明一实施例中，一种半导体装置，包括：一基底，具有一第一表面，基底包括一贴合区，贴合区具有至少一个接触垫；以及至少一个遮覆标记顺应着第一表面，遮覆标记为看得见的且包括自贴合区离开的一距离指标。
本发明另一实施例中，一种半导体装置，包括：一基底，具有一第一表面，基底包括一第一遮覆标记，位于第一表面的一第一区周围；以及一半导体基底，贴合至第一区，半导体基底包括一第二遮覆标记，对准第一遮覆标记且顺应着一第二表面，背离第一表面。
本发明又一实施例中，一种半导体装置制造方法，包括：提供一基底；在基底的一第一表面上形成一第一遮覆标记；在基底的第一表面上方放置一半导体基底；以及在该基底与该半导体基底之间放置一底胶材料，底胶材料自基底与半导体基底之间的区域朝向第一遮覆标记延伸。
本发明通过在基底上形成遮覆标记，有助于防止底胶材料占用比所需的基底面积更多的面积，且有助于将半导体装置的尺寸越缩越小；另外，通过使用遮覆标记作为半导体基底与基底之间的对准标记，让操作者即使在对准期间无法看见接触凸块及接触垫，也可在进行目视对准时降低误对准。
附图说明
图1A至图1B是分别示出根据一实施例的具有倒装芯片排置的半导体基底及基底剖面及平面示意图。
图2A至图2B是分别示出根据一实施例的填入底胶之后，半导体基底及基底剖面及平面示意图。
图3A至图3J是示出根据一实施例的遮覆标记的各种类型及外形。
图4A至图4B分别示出根据一实施例的以遮覆标记作为对准标记的剖面及平面示意图。
不同附图中对应的附图标记及符号通常对应相同的部件，除非有特别说明。这些附图清楚示出相关的实施例形态但不必然依照比例示出。
其中，附图标记说明如下：
101～半导体基底；
103～基底；
105～接触凸块；
107～遮覆标记；
109～接触垫；
111～条纹标记；
113～直线部；
115～贴合区；
201～底雕材料；
301～刻度；
303～数值；
305～虚设接触凸块；
307～虚设接垫；
309～直连续线；
401～半导体基底遮覆标记；
d1～第一距离；
d2～第二距离；
d3～第三距离；
d4～第四距离；
d5～第五距离；
d6～第六距离；
d7～第七距离；
d8～第八距离；
d9～第九距离；
d10～第十距离；
d11～第十一距离；
P1～间距。
具体实施方式
以下说明本发明实施例的制作与使用。然而，可轻易了解本发明实施例提供许多合适的发明概念而可实施于广泛的各种特定背景。所公开的特定实施例仅用于说明以特定方法制作及使用本发明，并非用以局限本发明的范围。
以下根据一特定背景说明本实施例，也就是，用于具有倒装芯片配置的半导体芯片的遮覆标记。然而，这些实施例也可应用于其他类型的标记。
请参照图1A及图1B，其分别示出具有倒装芯片配置的半导体基底101、基底103及接触凸块(bump)105剖面及平面示意图，其中图1A是示出沿图1B中A-A’线的剖面示意图。半导体基底101可为半导体芯片，其包含内部及/或上方具有电子装置的半导体基底，且包含(但不一定必须包含)介电层及导电层，以提供电子装置之间的连接及布线。半导体基底101上方可具有任何数量的交替排列的导电及介电层，但通常为具有3至12层交替排列的导电及介电层。
基底103为半导体基底101结构上及电性上的支撑体。在一实施例中，基底103可为印刷电路板，其含有导电布线，以规划通往及来自半导体基底101的电子信号以及电源与接地的连接。举例来说，电子信号可通往或来自位于基底103上的其他装置(未示出)，使半导体基底101及其他装置可一同运作而执行所需的功能。然而，任何所属技术领域中普通技术人员可以理解基底103并非限定于以上所讨论的印刷电路板，而印刷电路板也不是作为半导体基底101结构上及电性上的支撑的唯一方式，也可以采用任何其他适当的支撑基底，例如另一半导体基底101，其在适当位置上具有电性连接点以接收来自半导体基底101、转接板(interposer)、高密度内连线或封装基底等等的电性连接点。上述的这些基底也包括在本实施例的范围之内。
接触凸块105形成于半导体基底101与基底103之间。接触凸块105的材质可包括锡或其他适当的材料，例如银、铜、铝、金或镍。在一实施例中，接触凸块105为锡焊料凸块。接触凸块105的制作为先通过一般的方法，例如蒸镀、电镀、印刷、焊料转移(solder transfer)、植球等，在半导体基底101上形成一锡层，其厚度约在20至100微米(μm)的范围。在半导体基底101上形成一锡层之后，进行回流，以将其塑形成所需的凸块外形。
在半导体基底101上形成接触凸块105之后，可通过倒装芯片工艺，将半导体基底101贴附于基底103上。在此工艺中，半导体基底101被翻转，使接触凸块105面向基底103。接触凸块105面向基底103之后，对准接触凸块105，使接触凸块105与接触垫109作机械性及电性接触，通过提供基底103与半导体基底101之间的电性连接。在一实施例中，接触凸块105为焊料凸块，在形成电性接触之后，为了将半导体基底101贴附至基底103，可回流接触凸块105。
另外，任何所属技术领域中普通技术人员可以理解图1A及图1B所示出的倒装芯片排置以及以上所述并非上述实施例中唯一可应用排置，而上述的排置并非用以限定本实施例。也可采用其他类型的排置，例如硅通孔电极(through silicon vias，TSVs)或是这些排置的组合(例如，TSV与倒装芯片排置)。上述的这些排置或是其他适当的排置类型也包括在本实施例的范围之内。
如图1A及图1B所示，遮覆标记107位于基底103上。遮覆标记107可供观测者之用，作为底胶材料201(未示出在图1A及图1B，但示出在图2A至图2B，且后续有更完整的说明)要从半导体基底101下方延伸多远的指标，从遮覆标记107的位置可轻易追踪底胶材料201的位置，而不需要额外非必需底胶材料201来确保有足够的封胶，进而减少任何非必需的底胶材料201的遮覆。
遮覆标记107可位于基底103内且邻近于贴合区115(以虚线表示)，其用以容纳半导体基底101。在一实施例中，在放置半导体基底101之后，从上方观看半导体基底101及基底103时，遮覆标记107从半导体基底101延伸。另外，遮覆标记107包括一直线部113，具有条纹(hash)标记111沿着直线部113并以第一距离d1(约在50至500微米的范围，例如为100微米)的规律长度作为间隔。一旦将底胶材料201放至于半导体基底101与基底103之间，条纹标记111可容许底胶材料201进行精确的测量。遮覆标记107可通过相同于形成基底103上的其中一膜层(例如，含有接触垫109的膜层)所使用的光刻工艺而形成于基底103内。在一实施例中，遮覆标记107由导体所形成，例如铝，且与基底103的接触垫109同时形成。在本实施例中，遮覆标记107的制作为使用一沉积工艺(例如溅镀(sputtering)、化学气相沉积(chemical vapor deposition，CVD)、电镀、钢板印刷(stencilprinting)或喷墨印刷(jetting printing))来形成一材料层(未示出)，而部分的材料层可通过适当的工艺(例如，光刻及蚀刻工艺)除去而同时形成遮覆标记107及接触垫109。利用上述工艺，遮覆标记107的制作无需分开的工艺步骤。
然而，任何所属技术领域中普通技术人员可以理解上述的结构及工艺并非唯一适当的结构及工艺，且并非用于限定本实施例。也可采用任何适当的结构及工艺来形成可与周遭材料区别的遮覆标记107。举例来说，遮覆标记107也可由虚设凸块(dummy bump)、重布局线(redistribution line)、重布局连接窗(redistribution via)、接触垫、虚设硅通孔电极、开口沟槽/孔洞/图案或其组合所构成。上述所有结构及其工艺及其他适当的结构与工艺都可用于遮覆标记107。
另外，尽管以上所述的遮覆标记107露出于基底103的最外层，然而本实施例并非局限于此。遮覆标记107可由基底103的任何膜层所构成且位于任何膜层上，只要遮覆标记107通过任何中介层仍为可视的。举例来说，遮覆标记107可形成于基底103的最外层的下方膜层上方，接着覆盖一透明钝化保护(passivation)层(未示出)。上述步骤可保护遮覆标记107，同时也保有指示底胶宽度的能力。
请参照图2A及图2B，其分别示出出填入底胶材料201之后，半导体基底101及基底103剖面及平面示意图，其中图2A是示出沿图2B中B-B’线的剖面示意图。底胶材料201可注入或形成于半导体基底101与基底103之间的空间。举例来说，底胶材料201可包括液态环氧化物，其施加于半导体基底101与基底103之间，接着进行固化使其硬化。底胶材料201可用于防止形成于接触凸块105内的裂缝，其中裂缝通常会引起热应力。
另外，底胶材料201可为形成于半导体基底101与基底103之间的可变形胶或硅橡胶，用以防止接触凸块105内发生裂缝。可通过将胶或橡胶注入或放置于半导体基底101与基底103之间而形成胶或橡胶。可变形胶或硅橡胶可在后续工艺进行期间提供较大的应力释放。
在施加底胶材料201期间或之后，底胶材料201可通过参照遮覆标记107而检视底胶材料201的位置。通过观测或测定遮覆标记107在视觉上有多少被底胶材料201遮盖或隐藏，可决定出底胶材料201的总量及位置。举例来说，可采用光学显微镜来进行检视，然而也可采用其他适当方法来测定有多少遮覆标记107被底胶材料201遮盖。
为了帮助测定，如图1A至图2B所示，遮覆标记107可包括条纹标记111，其从遮覆标记107(如对照图1A至图1B所述)向外延伸。当知道条纹标记111的间隔时，例如上述的第一距离d1，可从简单的视觉检测有多少条纹标记111被遮盖就可轻易决定出底胶材料201的范围，如图2A至图2B所示的实施例，底胶材料201从基底103上的半导体基底101延伸出条纹标记111的一第一距离d1。
图3A至图3J示出遮覆标记107的各种类型及外形。举例来说，图3A至图3B所示出的遮覆标记107为“L”形，且从半导体基底101(俯视)的角落向外延伸。图3A是示出遮覆标记107为连续线的实施例，而图3B是示出相似的实施例，其中遮覆标记107为不连续线。在上述实施例中，遮覆标记107具有一长度为一第二距离d2，其在50至500微米的范围，例如100微米，而彼此间隔为一第三距离d3，其在50至500微米的范围，例如100微米。
图3C至图3D所示出的遮覆标记107为同轴方形，且从半导体基底101(俯视)的径向向外延伸。图3C是示出遮覆标记107为连续线的实施例，而图3D是示出相似的实施例，其中遮覆标记107为不连续线。在上述实施例中，遮覆标记107彼此间隔为一第四距离d4，其在50至500微米的范围，例如100微米，然而遮覆标记107的间隔也可大于或小于上述数量。另外，在不同的遮覆标记107之间也可具有不同的间隔。
图3E至图3F所示出的实施例相似于图3A的实施例(遮覆标记107为“L”形，且位于半导体基底101的角落)，但额外包含刻度301。刻度301位于基底103上且沿着半导体基底101(俯视)的一侧，以提供遮覆标记107的观测者参照之用。在一实施例中，刻度301可从一遮覆标记107沿着平行半导体基底101的路径延伸，并终止于位在半导体基底101的相对角落的另一遮覆标记107。另外，刻度301可额外包含条纹标记111，其具有规律的间距(在50至500微米的范围，例如100微米)，使其有助于距离的测定或估算。
图3F所示出的实施例相似于图3E的实施例，但额外增加数值303。数值303指示出一指标数值或是指示出沿着刻度301的各个距离。在图3F所示出的实施例中(仅为范例说明)，沿着遮覆标记107的第一个条纹标记111为数值100，其表示从遮覆标记107的角落沿着刻度301的距离为100微米处为第一个条纹标记111。另外，如图所示，每一条纹标记111与前一条纹标记111的距离为100微米，进而提供一观测者一参照刻度301或线索，以容许观测者对于放至于半导体基底101与基底103之间的底胶材料201的总量有较佳的估算。
图3G示出用于遮覆标记107的另一类型及外形。在本实施例中，遮覆标记107为一组刻度301(请参照图3E至图3F)，其彼此隔开，且刻度301自半导体基底101向外延伸。刻度301可包括或不包括数值303，其指示出刻度301的每一条纹标记111所在的距离。
图3H示出具有三角外形的遮覆标记107。为了减化附图，仅示出沿着半导体基底101两侧边形成的三角外形标记，然而其可沿着半导体基底101的任何侧边数而形成。三角外形标记的高为第五距离d5，其在50至500微米的范围，例如100微米。而三角外形标记的底宽为第六距离d6，其在50至500微米的范围，例如100微米。
图3I是示出利用虚设接触凸块305形成遮覆凸块107的实施例。虚设接触凸块305可相似于图1A中接触凸块105的方式而形成于基底103上，除了虚设接触凸块305是不作电性连接之外。其本身可连接或不连接至任何的接触垫109。如图所示，虚设接触凸块305可排成列，平行半导体基底101的侧边(俯视)，且这些列以一第七距离d7彼此隔开，其在50至500微米的范围，例如100微米。另外，也可将数值303额外形成于虚设接触凸块305，以供观测者参照之用。
图3J使用虚设接垫307作为遮覆标记107的实施例。虚设接垫307可于图1A中所述的接触垫109同时形成。然而，由于虚设接垫307为虚设的，因此虚设接垫307无需电性连接至基底103内的其他装置(未示出)。虚设接垫307可形成方块外形，每一侧边具有一第八距离d8，其在50至500微米的范围，例如100微米。另外，虚设接垫307可排列成任何形式，如图所示，其排成行且平行半导体基底101的一侧，其中各个虚设接垫307依一第九距离d9而彼此隔开，其在50至500微米的范围，例如100微米。而这些行依一第十距离d10而彼此隔开，其在50至500微米的范围，例如100微米。
另外，图3J示出一第二组遮覆标记107，其形成直连续线309的外形，直连续线309可排置于半导体基底101的一侧边，但不同于排置虚设接垫307的侧边，且与相邻的半导体基底101的侧边平行。直连续线309具有一长度为一第十一距离d11，其在50至500微米的范围，例如100微米，而其间距P1在50至500微米的范围，例如100微米。另外，也可形成数值303以供观测者参照之用。
任何所属技术领域中普通技术人员可以理解上述类型及外形仅为结构及外形的范例，其使用遮覆标记107，且并非用以局限于上述结构及外形的实施例。而任何适当的结构及外形都可使用遮覆标记107，且所有这些结构及外形也包括在本实施例的范围之内。另外，也可使用不同类型及外形的组合，以提供最好的遮覆标记107，其容易辨认及制造。
图4A至图4B分别示出根据另一实施例的剖面及平面示意图，其中图4A为图4B中C-C′’线的剖面示意图。在本实施例中，形成于基底103上的遮覆标记107可用于与半导体基底遮覆标记401对合，以辅助半导体基底101与基底103之间的对准。半导体基底遮覆标记401可利用形成图1A至图1B中遮覆标记107的相似工艺而形成于半导体基底101上。然而，形成半导体基底遮覆标记401，使接触凸块105对准于接触垫109时，半导体基底遮覆标记401也对准基底103上的遮覆标记107。即使在对准期间，无法看见接触凸块105及接触垫109，上述排置可提供了观测者查看适当对准的能力，进而降低因半导体基底101与基底103之间误对准而发生的错误。
另外，在半导体基底遮覆标记401位于半导体基底101的上表面的实施例中，可进行额外工艺，以沿着半导体基底101的一个或多个侧边延伸(未示出在图4A至图4B)。在半导体基底101为半导体芯片的实施例中，半导体芯片可从半导体晶片分割下来，而额外工艺，例如适当的电沉积(electrodeposition)、溅镀、CVD、激光蚀刻、蚀刻钢板印刷、或喷墨印刷或蚀刻，可用于沿着半导体基底101的侧边延伸半导体基底遮覆标记401。通过在半导体基底101的侧边形成半导体基底遮覆标记401，对准工艺可更为容易，因为除了正上方观看外的任何角度观看，对准标记更为接近在一起。
通过在基底103上形成遮覆标记107，观测者可更适当地做出底胶材料201的精确定位，进而能更精确地放置底胶材料201。上述精确定位有助于防止底胶材料201占用比所需的基底103面积更多的面积，且有助于将半导体装置的尺寸越缩越小。另外，通过使用遮覆标记107作为半导体基底101与基底103之间的对准标记，即使在对准期间，无法看见接触凸块105及接触垫109，操作者进行目视对准时也可降低误对准的情形。
虽然本发明已以较佳实施例揭示如上，然其并非用以限定本发明，任何所属技术领域中普通技术人员，在不脱离本发明的精神和范围内，当可作更动、替代与润饰。举例来说，遮覆标记可形成各种不同的外形，且遮覆标记的不同组合用于适应任何特定情况。
再者，本发明的保护范围并未局限于说明书内所述特定实施例中的工艺、机器、制造、物质组成、装置、方法及步骤，任何所属技术领域中普通技术人员可从本发明揭示内容中理解现行或未来所发展出的工艺、机器、制造、物质组成、装置、方法及步骤，只要可以在此处所述实施例中实施大体相同功能或获得大体相同结果皆可使用在本发明中。因此，本发明的保护范围包括上述工艺、机器、制造、物质组成、装置、方法及步骤。

Claims (10)

1.一种半导体装置，包括：
一基底，具有一第一表面，该基底包括一贴合区，该贴合区具有至少一个接触垫；以及
至少一个遮覆标记顺应着该第一表面，该遮覆标记包括自该贴合区离开的一距离指标。
2.如权利要求1所述的半导体装置，还包括：
一半导体基底，包括至少一接触凸块，该接触凸块与该接处垫接触；
一底胶材料，位于该半导体基底与该基底之间，该底胶材料延伸到至少一部分的该遮覆标记的上方；以及
至少一个半导体基底遮覆标记，位于该半导体基底上，该半导体基底遮覆标记与对应的该遮覆标记对准。
3.如权利要求1所述的半导体装置，其中该遮覆标记还包括：
一直线，自该贴合区的一侧边垂直延伸离开；以及
多个条纹标记，自该直线延伸离开且平行该贴合区的该侧边。
4.如权利要求1所述的半导体装置，其中该遮覆标记具有L外形且邻近于该贴合区的一角落。
5.如权利要求1所述的半导体装置，其中该遮覆标记具有刻度及数值，且该遮覆标记为矩形标记并环绕该贴合区。
6.如权利要求1所述的半导体装置，其中该遮覆标记为虚设接触凸块。
7.一种半导体装置，包括：
一基底，具有一第一表面，该基底包括一第一遮覆标记，位于该第一表面的一第一区周围；以及
一半导体基底，贴合至该第一区，该半导体基底包括一第二遮覆标记，对准该第一遮覆标记且顺应着一第二表面，其背离该第一表面。
8.如权利要求7所述的半导体装置，还包括第三、第四及第五遮覆标记，位于该基底的该第一表面，该第一、该第三、该第四及该第五遮覆标记分别位于邻近该第一表面的不同侧边之处，其中该第三、该第四及该第五遮覆标记分别对准于该基底上多个遮覆标记中所对应的其中一个。
9.一种半导体装置制造方法，包括：
提供一基底；
在该基底的一第一表面上形成一第一遮覆标记；
在该基底的该第一表面上方放置一半导体基底；以及
在该基底与该半导体基底之间放置一底胶材料，该底胶材料自该基底与该半导体基底之间的区域朝向该第一遮覆标记延伸。
10.如权利要求9所述的半导体装置制造方法，还包括：
利用该第一遮覆标记来测定该底胶材料自该半导体基底延伸的一距离；
在该半导体基底的一第二表面上形成一第二遮覆标记；以及
对准该半导体基底，使该第二表面背离该第一表面，且该第二表面上的该第二遮覆标记对准该第一表面上的该第一遮覆标记。
CN201110139903.4A 2010-07-30 2011-05-24 半导体装置及其制造方法 Active CN102347312B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/847,802 US8629568B2 (en) 2010-07-30 2010-07-30 Semiconductor device cover mark
US12/847,802 2010-07-30

Publications (2)

Publication Number Publication Date
CN102347312A true CN102347312A (zh) 2012-02-08
CN102347312B CN102347312B (zh) 2014-10-01

Family

ID=45525897

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110139903.4A Active CN102347312B (zh) 2010-07-30 2011-05-24 半导体装置及其制造方法

Country Status (3)

Country Link
US (1) US8629568B2 (zh)
CN (1) CN102347312B (zh)
TW (1) TWI438875B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104637395A (zh) * 2013-11-13 2015-05-20 上海和辉光电有限公司 用于基板上的标识结构、基板以及形成基板的标识结构的方法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9204542B1 (en) * 2013-01-07 2015-12-01 Xilinx, Inc. Multi-use package substrate
US9343386B2 (en) * 2013-06-19 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Alignment in the packaging of integrated circuits
US9239397B2 (en) * 2013-10-14 2016-01-19 Hunt Energy Enterprises Llc Electroseismic surveying in exploration and production environments
US9691686B2 (en) 2014-05-28 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Contact pad for semiconductor device
DE102015205402B4 (de) * 2015-03-25 2023-06-22 Bayerische Motoren Werke Aktiengesellschaft Karosseriestruktur mit einstückigen und als bogenförmige Rohre ausgebildeten B-Säulenverstärkungen, sowie entsprechend ausgebildete B-Säulenverstärkung
US9391028B1 (en) 2015-07-31 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit dies having alignment marks and methods of forming same
US9685411B2 (en) 2015-09-18 2017-06-20 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit dies having alignment marks and methods of forming same
TWI685987B (zh) * 2017-10-19 2020-02-21 泰谷光電科技股份有限公司 微晶粒模組轉移方法
CN107749395B (zh) * 2017-10-30 2020-06-26 武汉新芯集成电路制造有限公司 一种晶圆打标的方法
KR20210030774A (ko) 2019-09-10 2021-03-18 삼성전자주식회사 Pop 형태의 반도체 패키지

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030090006A1 (en) * 2000-08-08 2003-05-15 Farnworth Warren M. Underfill and encapsulation of carrier substrate-mounted flip-chip components using stereolithography
US6593168B1 (en) * 2000-02-03 2003-07-15 Advanced Micro Devices, Inc. Method and apparatus for accurate alignment of integrated circuit in flip-chip configuration
US6636313B2 (en) * 2002-01-12 2003-10-21 Taiwan Semiconductor Manufacturing Co. Ltd Method of measuring photoresist and bump misalignment

Family Cites Families (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4811082A (en) 1986-11-12 1989-03-07 International Business Machines Corporation High performance integrated circuit packaging structure
US5075253A (en) 1989-04-12 1991-12-24 Advanced Micro Devices, Inc. Method of coplanar integration of semiconductor IC devices
US4990462A (en) 1989-04-12 1991-02-05 Advanced Micro Devices, Inc. Method for coplanar integration of semiconductor ic devices
EP0568312A3 (en) 1992-04-27 1993-12-29 Seiko Instr Inc Semiconductor device with driver chip and methods of manufacture
US5380681A (en) 1994-03-21 1995-01-10 United Microelectronics Corporation Three-dimensional multichip package and methods of fabricating
US6002177A (en) 1995-12-27 1999-12-14 International Business Machines Corporation High density integrated circuit packaging with chip stacking and via interconnections
US6213376B1 (en) 1998-06-17 2001-04-10 International Business Machines Corp. Stacked chip process carrier
US6281042B1 (en) 1998-08-31 2001-08-28 Micron Technology, Inc. Structure and method for a high performance electronic packaging assembly
US6271059B1 (en) 1999-01-04 2001-08-07 International Business Machines Corporation Chip interconnection structure using stub terminals
US6461895B1 (en) 1999-01-05 2002-10-08 Intel Corporation Process for making active interposer for high performance packaging applications
US6229216B1 (en) 1999-01-11 2001-05-08 Intel Corporation Silicon interposer and multi-chip-module (MCM) with through substrate vias
US6243272B1 (en) 1999-06-18 2001-06-05 Intel Corporation Method and apparatus for interconnecting multiple devices on a circuit board
US6355501B1 (en) * 2000-09-21 2002-03-12 International Business Machines Corporation Three-dimensional chip stacking assembly
KR100364635B1 (ko) 2001-02-09 2002-12-16 삼성전자 주식회사 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법
KR100394808B1 (ko) 2001-07-19 2003-08-14 삼성전자주식회사 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법
KR100435813B1 (ko) 2001-12-06 2004-06-12 삼성전자주식회사 금속 바를 이용하는 멀티 칩 패키지와 그 제조 방법
DE10200399B4 (de) 2002-01-08 2008-03-27 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Erzeugung einer dreidimensional integrierten Halbleitervorrichtung und dreidimensional integrierte Halbleitervorrichtung
US6975016B2 (en) 2002-02-06 2005-12-13 Intel Corporation Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof
US6887769B2 (en) 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
US6661085B2 (en) 2002-02-06 2003-12-09 Intel Corporation Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
US6600222B1 (en) 2002-07-17 2003-07-29 Intel Corporation Stacked microelectronic packages
US6790748B2 (en) 2002-12-19 2004-09-14 Intel Corporation Thinning techniques for wafer-to-wafer vertical stacks
US6908565B2 (en) 2002-12-24 2005-06-21 Intel Corporation Etch thinning techniques for wafer-to-wafer vertical stacks
US6924551B2 (en) 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package
US6946384B2 (en) 2003-06-06 2005-09-20 Intel Corporation Stacked device underfill and a method of fabrication
US7320928B2 (en) 2003-06-20 2008-01-22 Intel Corporation Method of forming a stacked device filler
KR100537892B1 (ko) 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
US7345350B2 (en) 2003-09-23 2008-03-18 Micron Technology, Inc. Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias
KR100621992B1 (ko) 2003-11-19 2006-09-13 삼성전자주식회사 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지
KR100570514B1 (ko) 2004-06-18 2006-04-13 삼성전자주식회사 웨이퍼 레벨 칩 스택 패키지 제조 방법
KR100618837B1 (ko) 2004-06-22 2006-09-01 삼성전자주식회사 웨이퍼 레벨 패키지를 위한 얇은 웨이퍼들의 스택을형성하는 방법
US7307005B2 (en) 2004-06-30 2007-12-11 Intel Corporation Wafer bonding with highly compliant plate having filler material enclosed hollow core
US7087538B2 (en) 2004-08-16 2006-08-08 Intel Corporation Method to fill the gap between coupled wafers
US7317256B2 (en) 2005-06-01 2008-01-08 Intel Corporation Electronic packaging including die with through silicon via
US7557597B2 (en) 2005-06-03 2009-07-07 International Business Machines Corporation Stacked chip security
US7402515B2 (en) 2005-06-28 2008-07-22 Intel Corporation Method of forming through-silicon vias with stress buffer collars and resulting devices
US7432592B2 (en) 2005-10-13 2008-10-07 Intel Corporation Integrated micro-channels for 3D through silicon architectures
US7528494B2 (en) 2005-11-03 2009-05-05 International Business Machines Corporation Accessible chip stack and process of manufacturing thereof
US7410884B2 (en) 2005-11-21 2008-08-12 Intel Corporation 3D integrated circuits using thick metal for backside connections and offset bumps
US7402442B2 (en) 2005-12-21 2008-07-22 International Business Machines Corporation Physically highly secure multi-chip assembly
US7279795B2 (en) 2005-12-29 2007-10-09 Intel Corporation Stacked die semiconductor package
KR100809704B1 (ko) * 2006-09-22 2008-03-06 삼성전자주식회사 조립 정확도가 개선된 반도체 패키지
US7576435B2 (en) 2007-04-27 2009-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Low-cost and ultra-fine integrated circuit packaging technique
KR101213175B1 (ko) 2007-08-20 2012-12-18 삼성전자주식회사 로직 칩에 층층이 쌓인 메모리장치들을 구비하는반도체패키지
US7884472B2 (en) * 2008-03-20 2011-02-08 Powertech Technology Inc. Semiconductor package having substrate ID code and its fabricating method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6593168B1 (en) * 2000-02-03 2003-07-15 Advanced Micro Devices, Inc. Method and apparatus for accurate alignment of integrated circuit in flip-chip configuration
US20030090006A1 (en) * 2000-08-08 2003-05-15 Farnworth Warren M. Underfill and encapsulation of carrier substrate-mounted flip-chip components using stereolithography
US6636313B2 (en) * 2002-01-12 2003-10-21 Taiwan Semiconductor Manufacturing Co. Ltd Method of measuring photoresist and bump misalignment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104637395A (zh) * 2013-11-13 2015-05-20 上海和辉光电有限公司 用于基板上的标识结构、基板以及形成基板的标识结构的方法

Also Published As

Publication number Publication date
CN102347312B (zh) 2014-10-01
US8629568B2 (en) 2014-01-14
TWI438875B (zh) 2014-05-21
TW201205735A (en) 2012-02-01
US20120025368A1 (en) 2012-02-02

Similar Documents

Publication Publication Date Title
CN102347312B (zh) 半导体装置及其制造方法
US10361170B2 (en) Semiconductor package
CN102148210B (zh) 半导体器件及其制造方法
EP3800664B1 (en) Semiconductor package and method for fabricating base for semiconductor package
CN104332452B (zh) 芯片封装模组
CN204632759U (zh) 一种芯片尺寸等级的感测芯片封装体
TWI606767B (zh) 於如回流錫焊之製程期間精確定位及對齊一組件
KR20190018986A (ko) 플렉서블 표시 장치
US20150008575A1 (en) Semiconductor device and manufacturing method thereof
CN101188218A (zh) 具有不同高度的凸点的半导体芯片和包括其的半导体封装
CN105810600B (zh) 晶片模组及其制造方法
CN104916623A (zh) 半导体封装和制造半导体封装基底的方法
US6403401B1 (en) Heat spreader hole pin 1 identifier
CN104094401B (zh) 用于半导体装置的尾线连接器
CN103545277B (zh) 半导体封装件及其制法
CN103545286A (zh) 线路基板、半导体封装结构及线路基板制作工艺
US9437490B2 (en) Semiconductor device and manufacturing method thereof
US7560805B2 (en) Semiconductor package and method of manufacturing the same
US10991649B2 (en) Semiconductor device and method of manufacturing semiconductor device
US11211319B2 (en) Device structure
CN103208484B (zh) 半导体封装及其制造方法
WO2009028538A1 (ja) 半導体素子及びその製造方法
US9041229B1 (en) Merged fiducial for semiconductor chip packages
CN115084069A (zh) 半导体装置及其制造方法
US20180254257A1 (en) Package structure and method of manufacturing package structure

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant