TWI437662B - Ｓｏｉ基板的製作方法 - Google Patents

Ｓｏｉ基板的製作方法 Download PDF

Info

Publication number
TWI437662B
TWI437662B TW097146666A TW97146666A TWI437662B TW I437662 B TWI437662 B TW I437662B TW 097146666 A TW097146666 A TW 097146666A TW 97146666 A TW97146666 A TW 97146666A TW I437662 B TWI437662 B TW I437662B
Authority
TW
Taiwan
Prior art keywords
substrate
semiconductor film
single crystal
crystal semiconductor
soi substrate
Prior art date
Application number
TW097146666A
Other languages
English (en)
Chinese (zh)
Other versions
TW200947610A (en
Inventor
井坂史人
加藤翔
小松立
根井孝征
下村明久
Original Assignee
半導體能源研究所股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 半導體能源研究所股份有限公司 filed Critical 半導體能源研究所股份有限公司
Publication of TW200947610A publication Critical patent/TW200947610A/zh
Application granted granted Critical
Publication of TWI437662B publication Critical patent/TWI437662B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/04—Planarisation of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon

Landscapes

  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
TW097146666A 2007-12-03 2008-12-01 Ｓｏｉ基板的製作方法 TWI437662B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007312668 2007-12-03

Publications (2)

Publication Number Publication Date
TW200947610A TW200947610A (en) 2009-11-16
TWI437662B true TWI437662B (zh) 2014-05-11

Family

ID=40676162

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097146666A TWI437662B (zh) 2007-12-03 2008-12-01 Ｓｏｉ基板的製作方法

Country Status (4)

Country Link
US (1) US7781308B2 (https=)
JP (1) JP5503866B2 (https=)
KR (1) KR101521832B1 (https=)
TW (1) TWI437662B (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI616927B (zh) * 2014-06-13 2018-03-01 英特爾股份有限公司 晶圓接合的表面封裝

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5459900B2 (ja) * 2007-12-25 2014-04-02 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP5654206B2 (ja) * 2008-03-26 2015-01-14 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法及び該ｓｏｉ基板を用いた半導体装置
US8048754B2 (en) * 2008-09-29 2011-11-01 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate and method for manufacturing single crystal semiconductor layer
JP5611571B2 (ja) * 2008-11-27 2014-10-22 株式会社半導体エネルギー研究所 半導体基板の作製方法及び半導体装置の作製方法
JP5607399B2 (ja) * 2009-03-24 2014-10-15 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
SG178179A1 (en) * 2009-10-09 2012-03-29 Semiconductor Energy Lab Reprocessing method of semiconductor substrate, manufacturing method of reprocessed semiconductor substrate, and manufacturing method of soi substrate
JP5706670B2 (ja) * 2009-11-24 2015-04-22 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
JP5755931B2 (ja) 2010-04-28 2015-07-29 株式会社半導体エネルギー研究所 半導体膜の作製方法、電極の作製方法、２次電池の作製方法、および太陽電池の作製方法
JP5901913B2 (ja) * 2010-08-30 2016-04-13 株式会社半導体エネルギー研究所 半導体基板の作製方法、及び半導体装置の作製方法
JP5688709B2 (ja) * 2010-09-24 2015-03-25 国立大学法人東京農工大学 薄膜半導体基板の製造方法
US9123529B2 (en) 2011-06-21 2015-09-01 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate
CN109244260B (zh) * 2018-09-19 2021-01-29 京东方科技集团股份有限公司 一种显示面板的制备方法
JP7688550B2 (ja) 2021-09-17 2025-06-04 キオクシア株式会社 半導体装置、半導体装置の製造方法、および基板の再利用方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0747935B1 (en) * 1990-08-03 2004-02-04 Canon Kabushiki Kaisha Process for preparing an SOI-member
FR2681472B1 (fr) 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
US6251754B1 (en) 1997-05-09 2001-06-26 Denso Corporation Semiconductor substrate manufacturing method
JPH1174209A (ja) 1997-08-27 1999-03-16 Denso Corp 半導体基板の製造方法
JPH11163363A (ja) 1997-11-22 1999-06-18 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP2000124092A (ja) 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
JP4379943B2 (ja) * 1999-04-07 2009-12-09 株式会社デンソー 半導体基板の製造方法および半導体基板製造装置
WO2001006546A2 (en) * 1999-07-16 2001-01-25 Massachusetts Institute Of Technology Silicon on iii-v semiconductor bonding for monolithic optoelectronic integration
EP1939932A1 (en) * 1999-08-10 2008-07-02 Silicon Genesis Corporation A substrate comprising a stressed silicon germanium cleave layer
JP4182323B2 (ja) 2002-02-27 2008-11-19 ソニー株式会社 複合基板、基板製造方法
FR2855909B1 (fr) * 2003-06-06 2005-08-26 Soitec Silicon On Insulator Procede d'obtention concomitante d'au moins une paire de structures comprenant au moins une couche utile reportee sur un substrat
FR2856192B1 (fr) * 2003-06-11 2005-07-29 Soitec Silicon On Insulator Procede de realisation de structure heterogene et structure obtenue par un tel procede
JP4037803B2 (ja) * 2003-07-24 2008-01-23 株式会社東芝 Ｓｇｏｉ基板の製造方法
JP4617820B2 (ja) * 2004-10-20 2011-01-26 信越半導体株式会社 半導体ウェーハの製造方法
JP4654710B2 (ja) * 2005-02-24 2011-03-23 信越半導体株式会社 半導体ウェーハの製造方法
EP1835533B1 (en) 2006-03-14 2020-06-03 Soitec Method for manufacturing compound material wafers and method for recycling a used donor substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI616927B (zh) * 2014-06-13 2018-03-01 英特爾股份有限公司 晶圓接合的表面封裝

Also Published As

Publication number Publication date
US20090142904A1 (en) 2009-06-04
US7781308B2 (en) 2010-08-24
JP2009158943A (ja) 2009-07-16
TW200947610A (en) 2009-11-16
JP5503866B2 (ja) 2014-05-28
KR20090057934A (ko) 2009-06-08
KR101521832B1 (ko) 2015-05-20

Similar Documents

Publication Publication Date Title
TWI437662B (zh) Ｓｏｉ基板的製作方法
US7767547B2 (en) Manufacturing method of SOI substrate
KR101434934B1 (ko) Ｓｏｉ 기판의 제작 방법, 및 반도체 장치의 제작 방법
US7795111B2 (en) Manufacturing method of SOI substrate and manufacturing method of semiconductor device
US8093135B2 (en) Method of manufacturing semiconductor device
JP5577027B2 (ja) 半導体装置の作製方法並びに半導体装置及び電子機器
US8247307B2 (en) Manufacturing method of substrate provided with semiconductor films
KR101561855B1 (ko) Ｓｏｉ기판의 제작방법
KR20080101653A (ko) 반도체 기판 및 반도체 장치 및 그 제조 방법
JP5500798B2 (ja) Ｓｏｉ基板の作製方法及び半導体装置の作製方法
US8138063B2 (en) Manufacturing method of a semiconductor device including a single crystal semiconductor film, and a semiconductor film including impurity
KR20090096353A (ko) 복합 기판의 제조 장치 및 상기 복합 기판의 제조 장치를 사용한 복합 기판의 제조 방법
JP2010147313A (ja) Ｓｏｉ基板の作製方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees