TWI419276B - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
- Publication number
- TWI419276B TWI419276B TW099111380A TW99111380A TWI419276B TW I419276 B TWI419276 B TW I419276B TW 099111380 A TW099111380 A TW 099111380A TW 99111380 A TW99111380 A TW 99111380A TW I419276 B TWI419276 B TW I419276B
- Authority
- TW
- Taiwan
- Prior art keywords
- metal layer
- layer
- hole
- main surface
- semiconductor device
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/62—Electrodes ohmically coupled to a semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009191093A JP5532743B2 (ja) | 2009-08-20 | 2009-08-20 | 半導体装置及びその製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201108362A TW201108362A (en) | 2011-03-01 |
| TWI419276B true TWI419276B (zh) | 2013-12-11 |
Family
ID=43604671
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW099111380A TWI419276B (zh) | 2009-08-20 | 2010-04-13 | Semiconductor device and manufacturing method thereof |
Country Status (3)
| Country | Link |
|---|---|
| US (2) | US8581411B2 (enExample) |
| JP (1) | JP5532743B2 (enExample) |
| TW (1) | TWI419276B (enExample) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9616379B2 (en) * | 2013-07-25 | 2017-04-11 | Korea Institute Of Energy Research | Method for preparing hydrogen separation membrane and device for preparing hydrogen separation membrane |
| WO2015145815A1 (ja) * | 2014-03-27 | 2015-10-01 | 三菱電機株式会社 | 半導体装置、半導体装置の製造方法 |
| WO2023079631A1 (ja) | 2021-11-04 | 2023-05-11 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
| JPWO2024189685A1 (enExample) * | 2023-03-10 | 2024-09-19 |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4179533A (en) * | 1978-04-25 | 1979-12-18 | The United States Of America As Represented By The Secretary Of The Navy | Multi-refractory films for gallium arsenide devices |
| US6268619B1 (en) * | 1997-04-24 | 2001-07-31 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with high aspect ratio via hole including solder repelling coating |
| US20040213895A1 (en) * | 2003-04-24 | 2004-10-28 | Semiconductor Technology Academic Research Center | Method of manufacturing multilevel interconnection |
| US20080012134A1 (en) * | 2006-06-28 | 2008-01-17 | Samsung Electronics Co., Ltd. | Metal interconnection structures and methods of forming the same |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3642528A (en) * | 1968-06-05 | 1972-02-15 | Matsushita Electronics Corp | Semiconductor device and method of making same |
| US5075763A (en) * | 1988-09-28 | 1991-12-24 | Kopin Corporation | High temperature metallization system for contacting semiconductor materials |
| JPH03109725A (ja) * | 1989-09-25 | 1991-05-09 | Fujitsu Ltd | 半導体装置の製造方法 |
| JP2679320B2 (ja) * | 1989-12-20 | 1997-11-19 | 富士電機株式会社 | ショットキバリアダイオード |
| US5027189A (en) * | 1990-01-10 | 1991-06-25 | Hughes Aircraft Company | Integrated circuit solder die-attach design and method |
| JPH07193214A (ja) | 1993-12-27 | 1995-07-28 | Mitsubishi Electric Corp | バイアホール及びその形成方法 |
| US5956362A (en) * | 1996-02-27 | 1999-09-21 | Matsushita Electric Industrial Co., Ltd. | Semiconductor light emitting device and method of etching |
| JP4865130B2 (ja) * | 1999-02-18 | 2012-02-01 | 古河電気工業株式会社 | 半導体素子用電極とその製造方法 |
| JP3462166B2 (ja) * | 2000-09-08 | 2003-11-05 | 富士通カンタムデバイス株式会社 | 化合物半導体装置 |
| US6787910B2 (en) * | 2002-07-23 | 2004-09-07 | National Chiao Tung University | Schottky structure in GaAs semiconductor device |
| JP2005109058A (ja) * | 2003-09-30 | 2005-04-21 | Sanyo Electric Co Ltd | 半導体素子およびその製造方法 |
| JP4637009B2 (ja) | 2005-12-02 | 2011-02-23 | 三菱電機株式会社 | 半導体装置の製造方法 |
| JP2008251562A (ja) * | 2007-03-29 | 2008-10-16 | Sharp Corp | 半導体レーザ素子およびその形成方法 |
| JP2009064961A (ja) * | 2007-09-06 | 2009-03-26 | Sharp Corp | 半導体レーザ装置およびその製造方法 |
-
2009
- 2009-08-20 JP JP2009191093A patent/JP5532743B2/ja not_active Expired - Fee Related
-
2010
- 2010-04-13 TW TW099111380A patent/TWI419276B/zh not_active IP Right Cessation
- 2010-04-26 US US12/766,966 patent/US8581411B2/en not_active Expired - Fee Related
-
2013
- 2013-10-10 US US14/050,412 patent/US20140035145A1/en not_active Abandoned
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4179533A (en) * | 1978-04-25 | 1979-12-18 | The United States Of America As Represented By The Secretary Of The Navy | Multi-refractory films for gallium arsenide devices |
| US6268619B1 (en) * | 1997-04-24 | 2001-07-31 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with high aspect ratio via hole including solder repelling coating |
| US20040213895A1 (en) * | 2003-04-24 | 2004-10-28 | Semiconductor Technology Academic Research Center | Method of manufacturing multilevel interconnection |
| US20080012134A1 (en) * | 2006-06-28 | 2008-01-17 | Samsung Electronics Co., Ltd. | Metal interconnection structures and methods of forming the same |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201108362A (en) | 2011-03-01 |
| JP2011044546A (ja) | 2011-03-03 |
| US20110042822A1 (en) | 2011-02-24 |
| US20140035145A1 (en) | 2014-02-06 |
| JP5532743B2 (ja) | 2014-06-25 |
| US8581411B2 (en) | 2013-11-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |