TWI415198B - 半導體裝置之製造方法 - Google Patents

半導體裝置之製造方法 Download PDF

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Publication number
TWI415198B
TWI415198B TW096130285A TW96130285A TWI415198B TW I415198 B TWI415198 B TW I415198B TW 096130285 A TW096130285 A TW 096130285A TW 96130285 A TW96130285 A TW 96130285A TW I415198 B TWI415198 B TW I415198B
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Taiwan
Prior art keywords
adhesive layer
wafer
semiconductor device
adhesive
wiring substrate
Prior art date
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TW096130285A
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English (en)
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TW200818347A (en
Inventor
Osamu Yamazaki
Isao Ichikawa
Naoya Saiki
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Lintec Corp
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Application filed by Lintec Corp filed Critical Lintec Corp
Publication of TW200818347A publication Critical patent/TW200818347A/zh
Application granted granted Critical
Publication of TWI415198B publication Critical patent/TWI415198B/zh

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Description

半導體裝置之製造方法
本發明係關於一種製造半導體裝置的方法。更詳而言之，本發明係關於一種將晶片與未硬化的接著劑層予以層疊的配線基板進行加熱，使上述未硬化的接著劑層硬化，以製造半導體裝置的方法。
以往，半導體裝置係藉由液狀或膜狀熱硬化性接著劑將晶片與配線基板予以黏晶(黏晶(die bonding)步驟)，接著經由打線接合(wire bonding)步驟、模塑(molding)步驟來進行製造(第4圖，V至VII)。當透過未硬化的接著劑層3將晶片2與配線基板4予以層疊時，會在接著劑中存在空洞(void)5，或者在接著劑的晶片側或配線基板側的界面存在空洞6的情形(第4圖)。該等空洞即使在黏晶步驟之後亦存在而不會消滅(第4圖)。尤其在使用液狀接著劑時，大多會在接著劑中看到空洞，此外，在使用膜狀接著劑時，由於接著力不足或對被著面的凹凸追隨性不足，所以大多會在上述界面存在空洞。
然而，如上所示之空洞係在半導體裝置的可靠性評估中成為封裝破裂(package crack)的起點，因此必須使空洞消失。
對於此，專利文獻1嘗試提出一種若為液狀接著劑，係藉由塗佈時的低黏度，若為膜狀接著劑，則藉由黏晶時之彈性率的減低化，或者藉由黏晶條件的最適化，使其追隨配線基板的凹凸之技術。
專利文獻1：國際公開第2005/004216號文件
當使用液狀或膜狀接著劑時，雖利用上述方法使空洞減少，但若進行低黏度或低彈性率化時，在黏晶時會發生接著劑朝晶片端面溢出的不良情形。尤其在近年來經薄型化的晶片中，該溢出的接著劑會在晶片電路面捲曲，而會有污染導線墊(wire pad)，而使導線接合強度降低的問題。
此外，尤其在使用膜狀接著劑時，關於存在於上述界面之空洞的發生，亦取決於基板設計。因此，每當基板設計變更時，即必須配合變更而控制黏度或降低彈性率，或者重新檢視黏晶條件使之最適化，其處理亦較為困難。尤其在近年來的高密度配線基板中，凹凸的段差變大，為了填埋該段差而進行黏晶係相當困難的。
因此，本發明之目的在提供一種不取決於基板設計，而可簡單製造沒有空洞之半導體裝置的方法，此外提供一種可製造在此時亦不會見到接著劑捲曲之半導體裝置的方法。
本發明人等經精心研究結果，發現藉由特定的靜壓加壓步驟，即可解決上述課題，以致完成本發明。
亦即，本發明之半導體裝置之製造方法係將晶片與未硬化之接著劑層相疊層的配線基板(透過未硬化之接著劑層將晶片予以層疊的配線基板)進行加熱，使上述未硬化之接著劑層硬化，以製造半導體裝置的方法，其特徵為：包含靜壓加壓步驟，其在上述硬化前(上述硬化結束之前)，藉由相對於常壓為0.05MPa以上的靜壓，對上述晶片與未硬化之接著劑層相疊層的配線基板進行加壓。
此外，最好復包含熱硬化步驟，其在藉由上述靜壓加壓步驟所進行的加壓狀態的原狀態下，直接將上述晶片與未硬化之接著劑層相疊層的配線基板進行加熱，而將上述未硬化之接著劑層予以硬化。
根據本發明之半導體裝置之製造方法，當藉由未硬化的接著劑層將晶片與配線基板予以層疊時，可按一般條件進行，且藉由之後的靜壓加壓步驟，可不取決於基板設計，即簡單地消滅空洞。此外，在該靜壓加壓步驟中，係藉由靜壓進行加壓，因此亦不會發生接著劑捲曲。
以下具體說明本發明。
在本發明之半導體裝置之製造方法中，係將晶片2與未硬化之接著劑層3相疊層(黏晶)的配線基板1(透過未硬化的接著劑層3將晶片2予以層疊的配線基板1。以下相同)進行加熱，使上述未硬化之接著劑層3硬化，以製造半導體裝置(第1圖)。另外，在最後，該接著劑層係經充分硬化。
以晶片2而言，係使用按每一電路個別切斷半導體晶圓所得的晶片。此外，以配線基板4而言，係使用例如由金屬構成的引線架(lead frame)、由有機材料或無機材料構成的基板、或者由金屬及有機材料或無機材料構成的層疊基板等。此外，於本發明中，當製造多層型(multi－stack type)半導體裝置時，相對位於下側的晶片亦視為配線基板。
未硬化之接著劑層3係由膜狀或液狀接著劑所形成。最好係由膜狀接著劑所形成。本發明中所使用的接著劑係熱硬化性接著劑，只要含有熱硬化性樹脂即可。熱硬化性樹脂例如為環氧樹脂、酚樹脂、間苯二酚(resorcinol)樹脂、脲甲醛樹脂(urea formaldehyde resin)、三聚氫胺樹脂(melamine resin)、呋喃樹脂(furan resin)、不飽和聚酯樹脂、矽酮樹脂(silicone resin)等，與適當的硬化劑及視需要所添加的硬化促進劑相組合使用。如上所示之熱硬化性樹脂已知有很多種，於本發明中，係使用公知之各種熱硬化性樹脂，而未特別限制。此外，以熱硬化性接著劑而言，亦可為在常溫下具有黏著性的黏接著劑。所謂黏接著劑係指於初始狀態中以常溫呈現黏著性，藉由如加熱之類的觸發(trigger)進行硬化而呈現強固接著性的接著劑。以在常溫下具有黏著性的黏接著劑而言，係可列舉如在常溫下具有感壓接著性的黏結劑樹脂(binder resin)與如上所述之熱硬化性樹脂的混合物。以在常溫下具有感壓接著性的黏結劑樹脂而言，係列舉如丙烯酸樹脂、聚酯樹脂、聚乙烯醚樹脂、聚胺酯樹脂(urethane resin)、聚醯胺樹脂等。
於本發明中，當使用膜狀接著劑作為接著劑層3時，例如係可使用設有膜狀接著劑層的切割/黏晶片(dicing/die bonding sheet)。切割/黏晶片係具有在基材膜上以可剝離的方式將前述組成之膜狀接著劑層予以層疊的構成。為了控制切割/黏晶片之基材膜與膜狀接著劑層的剝離性，最好在形成膜狀接著劑層之接著劑的組成中另外調配聚胺酯系丙烯酸酯寡聚物(urethane acrylate oligomer)等的能量線硬化性樹脂。當調配能量線硬化性樹脂時，可帶來在能量線照射前與基板良好密接，在能量線照射後易於自基材剝離的效果。
在切割/黏晶片所形成之膜狀接著劑層的厚度雖然係依所接著之配線基板之凹凸的高度形狀等而異，但一般為3至100μm，以10至50μm為佳。
此外，於本發明中當使用液狀接著劑作為接著劑層3時，係使用例如由前述之膜狀接著劑層的組成中去除黏結劑樹脂所得之熱硬化性樹脂、與由該硬化劑所構成之調配的液狀(膏狀)接著劑。
接著，關於本發明之半導體裝置之製造方法，係就使用切割/黏晶片(膜狀接著劑)時之具體例加以說明。
於本發明中，當使用切割/黏晶片時，例如係經由(1)切割步驟、(2)黏晶步驟、(3)靜壓加壓步驟、(4)熱硬化步驟、(5)組裝步驟等各步驟來製造半導體裝置。
(1)切割步驟係在由矽等所構成的晶圓黏接切割/黏晶片，而將晶圓與未硬化之接著劑層同時進行切割的步驟。藉由該步驟，可得在單面具有未硬化之接著劑層的晶片。當切割/黏晶片具有能量線硬化性時，係在切割步驟前或切割步驟後照射能量線，而使其與基材膜的密接性降低。有時會因切割/黏晶片之黏接條件，而在晶片與未硬化之接著劑層的界面形成有空洞的情形。
(2)黏晶步驟係在切割/黏晶片之基材膜與未硬化之接著劑層3的界面進行剝離(拾起(pickup))，將具有所分離之未硬化之接著劑層的晶片疊層(黏晶)在配線基板之晶片裝載部的步驟。藉由該步驟，可得晶片2與未硬化之接著劑層3相疊層的配線基板1。有時會因黏晶的條件(壓力、溫度、時間等)，而在未硬化之接著劑層3與配線基板4的界面形成有空洞6的情形(第1圖)。
(3)靜壓加壓步驟係在未硬化之接著劑層充分硬化之前，由經黏晶之配線基板的所有方位均等進行加壓(靜壓加壓)的步驟(第1圖，I)。本發明中之加壓條件係相對於常壓為0.05MPa，較佳為相對於常壓為0.1至1.0MPa。亦即，與常壓相比較，施加0.05MPa以上之較大壓力，較佳為施加0.1至1.0MPa之較大壓力。
具體而言，在靜壓加壓步驟中係列舉如下所示之態樣。首先，藉由上述靜壓對已將未硬化狀態之接著劑層3予以黏晶之配線基板1進行加壓(第1圖，I)。藉由該靜壓所進行的加壓，來消滅發生在接著劑層3與晶片2之間的空洞(未圖示)、或者發生在接著劑層3與配線基板4之間的空洞6。即使為配線基板4微細且高低差較大的電路設計，若進行該靜壓加壓步驟，則發生在接著劑層3與配線基板4之界面的空洞6亦會消滅。如上所示，無須特別控制當藉由未硬化之接著劑層3將晶片2與配線基板4予以疊層時的條件，即可簡單地消滅空洞6。此外，於該靜壓加壓步驟中，由於藉由靜壓進行加壓，因此僅接著劑層未受到加壓，亦不會發生接著劑捲曲。
當所施加的壓力在上述範圍內時，可有效促進消滅空洞，並且可使用汎用的加壓裝置、耐壓防爆設備，而可將生產線精簡化。此外，幾乎不需要至設定壓力為止的時間，故較為理想。
此外，施加壓力的時間以1至120分鐘為佳，以5至90分鐘為更佳。
以靜壓加壓裝置而言，若可將靜壓施加至所黏晶之配線基板1，即無特別限制，但是最好藉由熱壓器(autoclave)(附壓縮機的耐壓容器)等來進行。但是，若在熱壓器等一定容積內施加壓力時，會引起環境溫度上升。為了進行半導體裝置的穩定生產，最好將溫度保持為一定，因而亦可控制在未硬化之接著劑層3未硬化程度的溫度。此外，藉由提高溫度，亦可期待因接著劑層流動化所發生的空洞變得容易移動，而變得較易消滅。以如上所示的溫度而言，雖然係依形成接著劑層3之接著劑的組成來適當設定，但是例如為30至120℃左右。
(4)熱硬化步驟係將予以黏晶之配線基板1的接著劑層3進行加熱而由未硬化狀態形成為充分硬化狀態的步驟(第1圖，II)。另外，於本說明書中，所謂未硬化狀態係指處於未進行接著劑之硬化反應的狀態。所謂充分硬化狀態，亦即所謂硬化已完成的狀態係指反應進行中，而接著劑無法變形的狀態。在(3)靜壓加壓步驟中，將空洞已消滅之予以黏晶的配線基板1由加壓裝置開放，且投入至在大氣壓下所使用的加熱裝置。藉此使未硬化之接著劑層3硬化而形成硬化的接著劑層8，而賦予作為半導體裝置之黏晶用接著劑所需的接著性能。在該狀態中予以黏晶的配線基板係維持(3)靜壓加壓步驟的狀態，在接著劑層8之兩側的界面並不存在空洞，而將晶片2與配線基板4強固接著。
關於加熱溫度及加熱時間，若接著劑層可充分硬化，即無特別限制，但取決於接著劑組成。加熱溫度以100至200℃為佳，以120至160℃為更佳，加熱時間係以15至300分鐘為佳，以30至180分鐘為更佳。
用以進行熱硬化的加熱裝置並無特別限制，可直接使用以往所使用的熱硬化裝置(烘箱)。
(5)組裝步驟係將已進行接著劑層之熱硬化且予以黏晶的配線基板組裝加工在半導體裝置的步驟。例如，如第1圖之步驟所示，進行將導線9連結的打線接合步驟、使用密封樹脂11的模塑步驟等(第1圖，III、IV)。如上所示來製造半導體裝置10。藉由本發明之製造方法所得之半導體裝置10由於在接著劑層的界面不存在空洞，因此於可靠性評估中不會發生封裝破裂。
以上雖然係就在(3)靜壓加壓步驟之後，在恢復成常壓之後進行(4)熱硬化步驟之半導體裝置之製造方法加以說明，但本發明之半導體裝置之製造方法亦可為在(3)靜壓加壓步驟中，進行在靜壓加壓狀態下直接將上述未硬化之接著劑層3加熱而予以硬化的熱硬化步驟的製造方法。
具體而言，亦可為在進行靜壓加壓步驟以使空洞消滅，並且一面置放在加壓下，一面進行熱硬化步驟而使接著劑層3充分硬化之後，同時結束靜壓加壓步驟與熱硬化步驟的態樣。此時，因係將在如進行熱硬化之類的高溫下所發生的接著劑中的空洞，在發生的同時，藉由靜壓加壓使其消滅，故較為理想。最後，半導體裝置係在接著劑層中或在界面中均不會存在空洞，而成為接著劑已充分硬化的狀態，且將晶片與配線基板予以強固接著。
本態樣中的加壓條件係相對於常壓為0.05MPa以上，較佳為0.1至1.0MPa，關於加熱溫度，若接著劑層可充分硬化，即無特別限制，但以100至200℃為佳，以120至160℃為更佳。
此外，關於加壓及加熱時間，若可消滅空洞，且接著劑層可充分硬化，即無特別限制，但以15至300分鐘為佳，以30至180分鐘為更佳。
此外，亦可為將熱硬化步驟分為2階段，將第1階段形成為使接著劑層不會硬化的加熱條件，將第2階段形成為使接著劑層硬化的加熱條件的態樣。此時，關於第1階段的加熱條件，例如加熱溫度為30至120℃左右，加熱時間以1至120分鐘為佳，以5至90分鐘為更佳。此外，關於第2階段的加熱條件，例如加熱溫度為120至200℃，加熱時間以15至300分鐘為佳，以30至180分鐘為更佳。
此外，於本發明之半導體裝置之製造方法中，亦可使用液狀(膏狀)接著劑作為接著劑層3。當使用液狀接著劑時，於前述之(1)切割步驟中，使用不具黏晶功能的一般切割片來取代切割/黏晶片，並將晶圓予以晶片化。在(2)黏晶步驟中將晶片拾起後，在已塗佈液狀接著劑的配線基板進行黏晶。(3)靜壓加壓步驟、(4)熱硬化步驟及(5)組裝步驟係可利用與前述態樣相同的方法進行。為了易於處理予以黏晶的配線基板，亦可在(3)靜壓加壓步驟之前，加上使液狀接著劑半硬化(B階段化)的加熱步驟。另外，當使用液狀接著劑時，即使在黏晶步驟中在接著劑層3中存在空洞5，亦可藉由靜壓加壓步驟來消滅空洞5(參照第4圖)。
藉由本發明之製造方法所得之半導體裝置的構成係可適用於各種構成之製造方法的製造，而非限定為前述態樣。
例如，本發明之半導體裝置之製造方法亦可適用在多層型半導體裝置的製造。亦即，亦可用在透過未硬化之接著劑層23將構成相對為上部的晶片22、及亦可連結導線之構成相對為下部的晶片25(配線基板)予以疊層的晶片彼此的黏晶步驟(第2圖)。如上所示之半導體裝置可為如第2圖所示之上部與下部的尺寸相同的相同尺寸堆疊型半導體裝置，亦可為尺寸不同之階梯狀多層型半導體裝置。更且，亦可為接著劑層23以嵌埋所結線之導線的形式予以疊層的相同尺寸堆疊型半導體裝置，此時，根據本發明，由於可消滅發生在導線周邊的空洞，故較為理想。
如上所示之多層型半導體裝置之製造方法係可藉由於前述態樣中將下部的晶片25取代配線基板1而達成。
此外，如第3圖所示，本發明之半導體裝置之製造方法亦可用在覆晶型(flip chip type)半導體裝置。此時，用在覆晶黏晶的底部填充材料(underfill material)係相當於未硬化之接著劑層。以底部填充材料而言，亦可使用液狀(膏狀)的底部填充材料，亦可使用片狀底部填充材料。以熱硬化性片狀底部填充材料而言，例如可使用本案申請人等之日本專利特願2005－129502號所記載者。
使用片狀底部填充材料時的製造方法係如下所示。首先，備妥在電路面形成有凸塊(bump)的半導體晶圓。以使上述片狀底部填充層(接著劑層23)貫穿凸塊的方式黏貼在半導體晶圓的電路面。接著，在半導體晶圓的背面黏接一般的切割帶(dicing tape)，且透過該切割帶固定在環形框架(ring frame)，使用切割裝置將半導體晶圓切斷分離，而得晶片。接著，僅將上述薄片(sheet)基材剝離，而使凸塊頂部露出。藉此方式獲得利用未硬化之接著劑層33覆蓋電路面，而且凸塊35頂部由接著劑層33突出的晶片。接著，該凸塊35係以與配線基板34的電極部相對的方式進行對位，且以確保晶片32與配線基板34之導通的方式，將晶片32載置於配線基板34。如上所示獲得晶片與未硬化之接著劑層33(底部填充材料)相疊層(覆晶黏晶)的配線基板31。
於本態樣中，係將如上所示所得之經覆晶黏晶的配線基板進行與前述態樣相同的(3)靜壓加壓步驟、(4)熱硬化步驟及(5)組裝步驟來製造半導體裝置。於本態樣中，由於並不需要(5)組裝步驟中的打線接合步驟，因此在使未硬化之接著劑層33(底部填充材料)硬化後，經由模塑步驟來製造半導體裝置。
(實施例)
以下根據實施例，更進一步具體說明本發明，但本發明並非限定為該等實施例者。
〔實施例1〕
(1)切割步驟使用貼片機(tape mounter)(日本琳得科(LINTEC)公司製，Adwill RAD2500 m/8)將切割/黏晶片(日本琳得科(LINTEC)公司製，Adwill LE－5003)黏貼在空白(dummy)的矽晶圓(200mm直徑、厚度150μm)，同時固定在環形框架(ring frame)。之後，使用UV照射裝置(日本琳得科(LINTEC)公司製，Adwill RAD2000 m/8)而由基材面照射紫外線。接著，使用切割裝置(日本迪思科(DISCO)公司製，DFD651)，切割成大小為8mm×8mm的晶片。切割時的切入深度係對切割/黏晶片的基材膜切入20μm。
(2)黏晶步驟以將晶片進行黏晶的配線基板而言，使用在銅箔疊層板(日本三菱氣體化學公司製，CCL－HL830)的銅箔形成有電路圖案，且在圖案上具有阻焊劑(solder resist)(日本太陽油墨公司製，PSR－4000 AUS5)的基板(日本茅野(chino)技研公司製)。按每一黏接著劑層(未硬化之接著劑層)拾取由(1)所得的矽晶片，且透過黏接著劑層載置在該配線基板上之後，以100℃、300gf、1秒鐘的條件予以壓接(黏晶)。
(3)靜壓加壓步驟接著，在加熱加壓裝置(日本栗原製作所製熱壓器)中投入將在(2)所得晶片予以黏晶的配線基板，且在比常壓大0.5MPa的靜壓下，以100℃，加熱30分鐘，而將在黏接著劑層出現的空洞去除。
(4)熱硬化步驟當由加熱加壓裝置中取出予以黏晶的配線基板之後，利用常壓的烘箱，以120℃、1小時，接著140℃、1小時的條件進行加熱，而使黏接著劑層硬化。
(5)組裝步驟藉由密封裝置(日本山田尖端科技公司(APIC YAMADA)製、MPC－06M Trial Press)，利用模塑樹脂(日本京瓷化成(Kyocera Chemical)公司製，KE－1100AS3)將(3)所得之予以黏晶的配線基板以成為密封厚度400 μm的方式進行密封。接著，以175℃、5小時使密封樹脂硬化。更且，將所密封的配線基板黏貼在切割帶(日本琳得科(LINTEC)公司製，Adwill D－510T)，藉由切割裝置(日本迪思科(DISCO)公司製，DFD651)切割成12mm×12mm大小，而獲得空白晶片(dummy chip)之無纜線的模擬式半導體裝置。
〔實施例2〕至〔實施例6〕
除了將實施例1中之(3)靜壓加壓步驟中的處理條件變更為表1的條件來進行以外，其餘與實施例1相同而獲得模擬式半導體裝置。其中，於表1中，壓力的值係以比常壓大多少予以表示。
〔實施例7〕
將(3)靜壓加壓步驟與(4)熱硬化步驟同時開始且同時結束。亦即，在比常壓大0.5MPa的靜壓下，以120℃進行1小時，接著以140℃進行1小時，而使黏接著劑層充分硬化。除此以外係與實施例1相同，而得模擬式半導體裝置。
〔實施例8〕
除了將切割/黏晶片變更為Adwill LE－5006(日本琳得科(LINTEC)公司製)以外，其餘與實施例1相同，而得模擬式半導體裝置。
〔實施例9〕
(1)切割步驟使用貼片機(tape mounter)(日本琳得科(LINTEC)公司製，Adwill RAD2500 m/8)將UV硬化型切割帶(日本琳得科(LINTEC)公司製，Adwill D－628)黏貼在空白(dummy)的矽晶圓(200mm直徑、厚度150μm)，同時固定在環形框架(ring frame)。接著，使用切割裝置(日本迪思科(DISCO)公司製，DFD651)，切割成大小為8mm×8mm的晶片。在切割時的切入深度係對基材膜切入20μm。之後，使用UV照射裝置(日本琳得科(LINTEC)公司製，Adwill RAD2000m/8)而由基材面照射紫外線。
(2)黏晶步驟以將晶片進行黏晶的配線基板而言，使用在銅箔疊層板(日本三菱氣體化學公司製，CCL－HL830)的銅箔形成有電路圖案，且在圖案上具有阻焊劑(solder resist)(日本太陽油墨公司製，PSR－4000 AUS5)的基板(日本茅野(chino)技研公司製)。將由以下調配所構成之膏狀接著劑塗佈在該配線基板上，拾起在(1)所得之矽晶片，且載置於該配線基板上之膏狀接著劑之上之後，再以23℃、100gf、1秒鐘的條件予以壓接(黏晶)。
(膏狀接著劑的調配)液狀雙酚A型骨架環氧樹脂(日本環氧樹脂(股)公司製、Epikote828(商品名))：30重量份、縮水甘油胺型環氧樹脂(日本環氧樹脂(股)公司製、Epikote630(商品名))：15重量份、酚醛型環氧樹脂(Novolac type epoxy resins)(日本化藥(股)公司製、EOCN－102S)：5重量份、將硬化劑(日本旭電化公司製、ADEKA硬化劑3636AS(商品名))分散在有機溶劑(甲基乙基酮)所得溶液(固形濃度為15%)：5重量份、將硬化促進劑(日本四國化成工業公司製、Curezol2PHZ(商品名))分散在有機溶劑(甲基乙基酮)所得溶液(固形濃度為15％)：10重量份
(3)靜壓加壓步驟及(4)熱硬化步驟接著，將(3)靜壓加壓步驟及(4)熱硬化步驟同時開始且同時結束。亦即，在加熱加壓裝置(日本栗原製作所製熱壓器)中投入將晶片予以黏晶的配線基板，且在0.5MPa的靜壓下，以120℃，1小時，接著以140℃，1小時進行，而在加壓條件下使黏接著劑層硬化。
(5)密封步驟藉由密封裝置(日本山田尖端科技公司(APIC YAMADA)製、MPC－06M Trial Press)，利用模塑樹脂(日本京瓷化成(Kyocera Chemical)公司製，KE－1100AS3)將(3)所得之予以黏晶的配線基板以成為密封厚度400 μm的方式進行密封。接著，以175℃、5小時使密封樹脂硬化。接著，將所密封的配線基板黏貼在切割帶(日本琳得科(LINTEC)公司製，Adwill D－510T)，藉由切割裝置(日本迪思科(DISCO)公司製，DFD651)切割成12mm×12mm大小，而獲得模擬式半導體裝置。
〔比較例1〕
在靜壓加壓步驟至熱硬化步驟中，將予以黏晶的配線基板投入至加熱加壓裝置，但是不進行加壓，而在大氣壓下，以120℃，加熱1小時，接著以140℃，加熱1小時，使黏接著劑層硬化。除此以外係與實施例1相同而獲得模擬式半導體裝置。亦即，除了不進行靜壓加壓步驟以外，其餘與實施例1相同，而得模擬式半導體裝置。
〔比較例2〕
在實施例9之(2)黏晶步驟中，除了將晶片的壓接條件設為23℃、500gf、1秒鐘以外，其餘進行與實施例9相同的評估。另外，由於在黏晶步驟後之接著劑的捲曲情形過多，因此之後的步驟並未進行。
〔評估方法〕
試驗1：確認有無空洞在實施例、比較例之半導體裝置之製造方法中，使用透明的圓板玻璃(NSG精密(NSG Precision)公司製，直徑8吋、厚度100 μm)取代矽晶圓而進行相同的操作。關於將所得玻璃晶片予以黏晶的配線基板，係可由玻璃晶片側透視接著劑層，且藉由數位顯微鏡觀察有無空洞。結果顯示於表2。
試驗2：確認接著劑朝晶片表面捲曲的情形在實施例、比較例之半導體裝置之製造方法中，在(3)靜壓加壓步驟及(4)熱硬化步驟結束階段，藉由數位顯微鏡觀察予以黏晶之配線基板的剖面及晶片表面，且確認接著劑有無在晶片表面捲曲。結果顯示於表2。
試驗3：半導體封裝的可靠性評估在實施例、比較例之半導體裝置之製造方法中，將已結束(5)密封步驟的半導體裝置(半導體封裝)在85℃、60%RH條件下放置168小時而使其吸濕之後，進行3次最高溫度260℃、加熱時間1分鐘的IR回焊(回焊爐：日本相模理工製，WL－15－20DNX型)。之後，利用掃描型超音波探傷裝置(日本日立建機精技(Hitachi Kenki FineTech)公司製，Hye－Focus)所進行的剖面觀察，來評估晶片與配線基板的接合部有無鬆動或剝離、有無發生封裝破裂。將在接合部觀察到0.5mm以上之剝離的情形判斷為「已發生剝離」。針對半導體封裝25個進行上述試驗，且計數「未發生剝離」的個數。該評估結果顯示於表2。
1．．．晶片與未硬化之接著劑層相疊層之配線基板
2．．．晶片
3．．．未硬化之接著劑層
4．．．配線基板
5．．．存在於接著劑層中的空洞
6．．．存在於配線基板與接著劑層之界面的空洞
8．．．已硬化的接著劑層
9．．．導線
10．．．半導體裝置
11．．．密封樹脂
21．．．密封前之多層型半導體裝置
22．．．構成相對為上部(第2層)的晶片
23．．．未硬化之接著劑層
25．．．構成相對為下部(第1層)的晶片(配線基板)
26．．．接著劑層
27．．．晶片裝載用配線基板
31．．．晶片與未硬化之接著劑層(底部填充材料)相疊層(覆晶黏晶)之配線基板
32．．．晶片
33．．．未硬化之接著劑層
34．．．配線基板
35．．．凸塊
41．．．具有已充分硬化之接著劑層的配線基板
42．．．已硬化的接著劑層
43．．．導線
44．．．半導體裝置
45．．．密封樹脂
I．．．靜壓加壓步驟
II．．．熱硬化步驟
III．．．打線接合步驟
IV．．．模塑步驟
V．．．黏晶步驟
VI．．．打線接合步驟
VII．．．模塑步驟
第1圖係用以說明本發明之半導體裝置之製造方法的說明圖。
第2圖係顯示在本發明中所使用之晶片與未硬化之接著劑層相疊層之配線基板之例。
第3圖係顯示在本發明中所使用之晶片與未硬化之接著劑層相疊層之配線基板之例。
第4圖係用以說明習知之半導體裝置之製造方法的說明圖。
1．．．晶片與未硬化之接著劑層相疊層之配線基板
2．．．晶片
3．．．未硬化之接著劑層
4．．．配線基板
6．．．存在於配線基板與接著劑層之界面的空洞
8．．．已硬化的接著劑層
9．．．導線
10．．．半導體裝置
11．．．密封樹脂
I．．．靜壓加壓步驟
II．．．熱硬化步驟
III．．．打線接合步驟
IV．．．模塑步驟

Claims (2)

  1. 一種半導體裝置之製造方法，係將晶片與未硬化之接著劑層相疊層的配線基板進行加熱，使前述未硬化之接著劑層硬化，以製造半導體裝置的方法，其特徵為：包含靜壓加壓步驟，其在前述硬化前，藉由相對於常壓為0.05MPa以上的靜壓，對前述晶片與未硬化之接著劑層相疊層的配線基板進行加壓。
  2. 如申請專利範圍第1項之半導體裝置之製造方法，其中，復包含熱硬化步驟，其在藉由前述靜壓加壓步驟所進行的加壓狀態的原狀態下，直接將前述晶片與未硬化之接著劑層相疊層的配線基板進行加熱，而將前述未硬化之接著劑層予以硬化。
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Families Citing this family (5)

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Publication number Priority date Publication date Assignee Title
JP2010245412A (ja) * 2009-04-09 2010-10-28 Renesas Electronics Corp 半導体集積回路装置の製造方法
US9079351B2 (en) * 2012-06-22 2015-07-14 Wisconsin Alumni Research Foundation System for transfer of nanomembrane elements with improved preservation of spatial integrity
KR101696539B1 (ko) * 2015-03-09 2017-01-16 한양대학교 산학협력단 박막, 그 제조 방법, 및 그 제조 장치
CN111971166B (zh) * 2018-03-29 2022-05-31 琳得科株式会社 接合2个被粘物的方法、以及接合结构体的制造方法
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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030027371A1 (en) * 2001-08-03 2003-02-06 Yoshitaka Sunagawa Method for fabricating semiconductor-mounting body and apparatus for fabricating semiconductor-mounting body

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03169029A (ja) 1989-11-28 1991-07-22 Mitsubishi Electric Corp 半導体装置の実装方法
US5853651A (en) * 1995-09-07 1998-12-29 Simula, Inc. High pressure hollow process for manufacturing composite structures
JP4032317B2 (ja) * 1996-08-06 2008-01-16 日立化成工業株式会社 チップ実装法
JP3928753B2 (ja) * 1996-08-06 2007-06-13 日立化成工業株式会社 マルチチップ実装法、および接着剤付チップの製造方法
JP3053839U (ja) 1998-05-07 1998-11-17 中央電子株式会社 スライド式機器設置台
JP2000114204A (ja) 1998-10-01 2000-04-21 Mitsubishi Electric Corp ウエハシート及びこれを用いた半導体装置の製造方法並びに半導体製造装置
JP2001230528A (ja) * 2000-02-15 2001-08-24 Sony Corp 実装装置及び実装方法
US6513236B2 (en) * 2000-02-18 2003-02-04 Matsushita Electric Industrial Co., Ltd. Method of manufacturing bump-component mounted body and device for manufacturing the same
US6524891B1 (en) * 2000-02-29 2003-02-25 Micron Technology, Inc. Method of pressure curing for reducing voids in a die attach bondline and applications thereof
DE10019443A1 (de) * 2000-04-19 2001-10-31 Texas Instruments Deutschland Vorrichtung zum Befestigen eines Halbleiter-Chips auf einem Chip-Träger
JP3906962B2 (ja) * 2000-08-31 2007-04-18 リンテック株式会社 半導体装置の製造方法
JP4513235B2 (ja) * 2001-05-31 2010-07-28 ソニー株式会社 フリップチップ実装装置
JP4710205B2 (ja) * 2001-09-06 2011-06-29 ソニー株式会社 フリップチップ実装方法
DE60235821D1 (de) * 2001-09-12 2010-05-12 Nikkiso Co Ltd Verfahren und presse zur montage einer schaltung
JP2004311709A (ja) * 2003-04-07 2004-11-04 Renesas Technology Corp 半導体装置の製造方法および半導体製造装置
EP1650790B1 (en) 2003-07-08 2010-04-28 LINTEC Corporation Hardenable pressure sensitive adhesive sheet for dicing/die-bonding and method for manufacturing semiconductor device
JP3921459B2 (ja) * 2003-07-11 2007-05-30 ソニーケミカル＆インフォメーションデバイス株式会社 電気部品の実装方法及び実装装置
JP2004031975A (ja) * 2003-07-22 2004-01-29 Hitachi Chem Co Ltd 接続装置
JP2005129502A (ja) 2003-09-29 2005-05-19 Pioneer Plasma Display Corp プラズマディスプレイパネル及びプラズマ表示装置
US20050208700A1 (en) * 2004-03-19 2005-09-22 Chippac, Inc. Die to substrate attach using printed adhesive
US20060252234A1 (en) 2004-07-07 2006-11-09 Lintec Corporation Hardenable pressure sensitive adhesive sheet for dicing/die-bonding and method for manufacturing semiconductor device
JP2008159820A (ja) * 2006-12-22 2008-07-10 Tdk Corp 電子部品の一括実装方法、及び電子部品内蔵基板の製造方法
JP2008159819A (ja) 2006-12-22 2008-07-10 Tdk Corp 電子部品の実装方法、電子部品内蔵基板の製造方法、及び電子部品内蔵基板

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030027371A1 (en) * 2001-08-03 2003-02-06 Yoshitaka Sunagawa Method for fabricating semiconductor-mounting body and apparatus for fabricating semiconductor-mounting body

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