TWI413194B - 使用預鑄模載體之嵌入式晶粒封裝及處理流程 - Google Patents

使用預鑄模載體之嵌入式晶粒封裝及處理流程 Download PDF

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TWI413194B
TWI413194B TW098119563A TW98119563A TWI413194B TW I413194 B TWI413194 B TW I413194B TW 098119563 A TW098119563 A TW 098119563A TW 98119563 A TW98119563 A TW 98119563A TW I413194 B TWI413194 B TW I413194B
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forming
metal conductors
dielectric layer
carrier
electrical
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TW098119563A
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TW201005838A (en
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Luke England
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Fairchild Semiconductor
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Description

使用預鑄模載體之嵌入式晶粒封裝及處理流程
本發明係關於用於鑄模電裝置或多個電裝置之封裝。
過去，如半導體晶粒之電裝置通常藉由首先將該裝置安裝在一引線架上及隨後連接至外部引線，並隨後被封裝。然而，隨著電裝置之微型化持續進展，新的封裝技術已被發展且仍在被發展用於該或該等被封裝半導體裝置之縮小，此乃藉由此等方法，如將多個晶粒放如一封裝內及利用與薄鑄模覆蓋的焊塊互連。
雖然焊塊與薄鑄模可提供一小的封裝，但是該半導體晶粒較脆弱且必須以足夠的剛度被封裝以保護該晶粒及密封該晶粒。另一約束為，用於貿易市場之經濟可行的封裝方法需為通用的使得它可被用於不同的裝置尺寸與幾何形狀及仍可提供一具有匹配工業實際標準之足印之封裝。
本發明包括(以其一形式)形成一嵌入式封裝之方法。該方法包括以下步驟：形成一載體，其具有第一複數個空穴；將一電裝置置於該第一複數個空穴之每一個中；形成一第一介電層，其圍繞並位於每一個電裝置之上且位於該等載體之上表面之上；形成通孔，其貫穿該介電層至每一個電裝置上之選定焊墊；及形成第二複數個金屬導體，其每一個與一個通孔接觸並延伸一段距離遠離此等通孔。該方法也包含：形成一個或多個額外的介電層，其位於該第二複數個金屬導體之每一個與該第一介電層之暴露部分之上；在該一個或多個額外的介電層之一者內形成開口於一金屬導體之上；形成第三複數個焊塊，其每一個耦合於該第二複數個金屬導體之一個；及單一化該第一複數個空穴。
在另一形式中，本發明包括：一嵌入式晶粒封裝，其包含一具有一第一電裝置於載體之第一空穴中之預鑄模載體；一第一介電層，其覆蓋除位於該電裝置之選定焊墊之上的通孔之外的該電裝置之側面與頂部；第一複數個金屬導體，其每一個連接至該等通孔之至少一個；一個或多個額外的介電層，其位於該等金屬導體與該第一介電層之上，其中該一個或多個介電層之一頂層於每一個金屬導體之一部分之上具有開口；及第二複數個焊塊，其從每一個開口突出。
在又另一形式中，本發明包括如上述形式之一嵌入式晶粒封裝，除了該預鑄模載體為一平坦水平表面而非具有空穴之一預鑄模載體。
藉由以下連同附圖之更詳細的描述，前述與其他特徵、特性、優點、及本發明可被更容易地理解。
應瞭解，由於清晰之目的及於認為合適之處，在圖中參考數字被重複以指示相應的特徵。同樣地，在圖中各個物體之相對尺寸被歪曲以更清晰地顯示本發明。
圖1A為一預鑄模載體20之一示意截面圖，該載體由如環氧樹脂鑄模化合物之囊封材料而形成。圖1所示之該載體20具有二個空穴22與24，其具有一外部側壁26用於空穴22及一外部側壁28用於空穴24。一較厚的中央壁30分開該二個空穴22、24，其代表於該預鑄模載體之二個鄰近的封裝點。該等空穴22、24具有一基座32。
圖1B顯示二個半導體晶粒34與36分別被晶粒附接於該等空穴22與24內之後的該預鑄模載體20。在圖1B中，該等半導體晶粒34與36延伸至該預鑄模載體20之該等側壁26、28與該中央壁30之上。該等半導體晶粒34與36之每一者具有焊墊38。該晶粒附接可藉由標準的晶粒附接方法而被製成，例如(但非僅限於)環氧樹脂或一晶粒附接膜40。在圖1C中，介電材料42填充半導體晶粒34與36、側壁26與28、及中央壁30之間的空隙，並延伸至該等半導體晶粒34與36之上及其頂部上。通孔44貫穿該介電材料42至該等焊墊38。
該介電材料42可藉由幾種已知方法之任一種形成，該等方法包含利用具有一如味素積聚膜(Ajinomoto Build-Up FILM，ABF)之材料之真空膜層合程序，其後接續有該等通孔44之雷射鑽孔。該等通孔44也可藉由聚醯亞胺或光阻劑之旋塗或噴塗而被形成，其後接續有微影蝕刻。
如圖1D所示，金屬化被沈積、圖案化及蝕刻以從焊墊38至非直接位於該等半導體晶粒34與36之上之位置形成金屬互連48。在本發明之一實施例中，金屬化係藉由以下方式形成：首先透過無電Cu電鍍或Cu噴濺沈積以薄金屬種子層塗布該介電層42之表面與該等暴露焊墊38，設下一圖案化光阻劑層，及在該薄金屬層之暴露區域電鍍額外金屬。然後移除光阻劑並使用酸蝕刻移除金屬種子層。在本發明之另一實施例中，該等金屬互連藉由Al噴濺沈積而被形成至理想的最終互連厚度。一光阻劑層隨後被沈積及圖案化以匹配該互連線路。該Al金屬被蝕刻，隨後接續有光阻劑去除，其留下該最終互連圖案。
參照圖1E，在該等金屬互連48形成之後，一第二介電層52隨後被塗敷及圖案化於第一層級的介電材料42與金屬互連48之上。介電層52塗敷之程序可匹配該第一介電層42塗敷之程序。
在圖1F中，焊塊56藉由幾種已知程序之一種而形成，例如(但非僅限於)模板印刷或落球，其後接有一回焊循環。視乎該互連金屬組合物，可能需要一可焊接凸塊下金屬化(UBM)層。此可藉由無電電鍍方法而完成。該等嵌入式晶粒封裝58之形成可藉由該二個封裝之單一化而完成。
圖2A與2B依照本發明之一實施例，分別顯示一封裝半導體晶粒64之頂部60與底部62立體圖。此等圖中所示之封裝具有一預鑄模載體66，一第二介電層68具有突出之焊塊56。
圖3A-3F依照本發明之一實施例，顯示形成嵌入式晶粒封裝70之各個階段。圖3A顯示一預鑄模載體72，其具有九個空穴74之一矩陣。半導體晶粒76被置於圖3B所示之九個孔穴74之每一者中。
圖3C顯示該嵌入式晶粒封裝，其中一第一介電層80已形成於該等晶粒76之上，通孔已形成於該第一介電層80，及金屬導體82已形成於該等焊墊78與定點84(該等焊塊56將被置於此)之間。如圖3D所示，隨後一第二介電層86形成於該第一介電層80與該金屬導體82之上，及開口88製成於該第二介電層86內以暴露用於該等焊塊56之定點84。
圖3E顯示於該定點84上適當位置之焊塊56，圖3F則顯示在一單一化程序之後的該等個別的晶粒封裝70。
圖4、5、與6顯示在實行本發明中某些可能的實施例。在圖4中，該半導體晶粒34在一空穴22中，其緊鄰於一更深許多的空穴90，該空穴90包含如電感器、電阻器、或電容器之一被動電元件92。該半導體晶粒34可具有一約20 μm之高度及該電元件92可具有一約1 mm之高度，但是每一個之高度可隨應用要求而變化。此外，如圖4所示，該半導體晶粒34與該電元件92之寬度可為不同的。從而該預鑄模載體94形成以容納該半導體晶粒34與該電元件92之高度與寬度。
圖5為一依照本發明之另一實施例之預鑄模載體之一示意截面圖，其中互連金屬化製成於二個半導體晶粒34與36之間。利用一般的PC板或再分配層技術，互連可製成於不同的垂直層級。在圖5中，一金屬互連96位於一第一介電層42與一第二介電層94(其可比圖1E所示之該第二介電層52厚)之間。該金屬互連96將半導體晶粒34與36之焊墊38連接在一起作為一嵌入式晶粒封裝98(其為一多晶片封裝)之一部分。一金屬互連100形成一連接，其從一焊墊102至位於該第二介電層94上之一金屬互連104，其延伸至該金屬互連96。另一金屬互連106形成一連接，其從焊墊108至位於該第二介電層94之上之一第二金屬互連110。一第三介電層112覆蓋該金屬互連104與110及該第二介電層94之暴露區域。若干焊塊56也顯示於圖5，其延伸通過該第三介電層112之開口至該等金屬互連104與110。
在圖6中，該預鑄模載體114不具有側壁26、28或中央壁30，但是具有一平坦水平表面。關於圖1A-F之上述程序仍可適用以形成圖6所示之實施例。在未使用焊墊38之應用中，不存在至該嵌入式晶粒封裝之焊墊之金屬互連，其一實例顯示於圖6。
雖然本發明參照特定的實施例而被描述，熟習此項技術者應瞭解，在不偏離本發明之範圍的前提下，可作出多種變化且其中的元件可被等效物替代。此外，可作許多修改以適應本發明教示的一特定情況或材料而不偏離本發明之範圍。
因此，本發明並非僅限於該等被揭示作為實行本發明之最佳預期模式之特定實施例，而是本發明將包含符合該申請專利範圍之範圍與精神之所有實施例。
20．．．預鑄模載體
22．．．空穴
24．．．空穴
26．．．側壁
28．．．側壁
30．．．中央壁
32．．．基座
34．．．半導體晶粒
36．．．半導體晶粒
38．．．焊墊
40．．．晶粒附接膜
42．．．第一介電層
44．．．通孔
48．．．金屬互連
52．．．第二介電層
56．．．焊塊
58．．．嵌入式晶粒封裝
60．．．頂部
62．．．底部
64．．．封裝半導體晶粒
66．．．預鑄模載體
68．．．第二介電層
70．．．嵌入式晶粒封裝
72．．．預鑄模載體
74．．．空穴
76．．．半導體晶粒
78．．．焊墊
80．．．第一介電層
82．．．金屬導體
84．．．定點
86．．．第二介電層
88．．．開口
90．．．空穴
92．．．被動電元件
94．．．第二介電層
96．．．金屬互連
98．．．嵌入式晶粒封裝
100．．．金屬互連
102．．．焊墊
104．．．金屬互連
106．．．金屬互連
108．．．焊墊
110．．．金屬互連
112．．．第三介電層
114．．．預鑄模載體
圖1A依照本發明之一實施例，為一預鑄模載體之一示意截面圖；圖1B為圖1A所示之該預鑄模載體之一示意截面圖，其中二個半導體晶粒已被晶粒附接於該預鑄模載體之二個空穴內；圖1C為圖1B所示之該預鑄模載體之一示意截面圖，其中一第一介電層已被形成；圖1D為圖1C所示之該預鑄模載體之一示意截面圖，其中金屬互連已被形成；圖1E為圖1D所示之該預鑄模載體之一示意截面圖，其中一第二介電層已被形成；圖1F為圖1E所示之該預鑄模載體之一示意截面圖，其中焊塊已被形成；圖2A與2B依照本發明之一實施例，分別顯示一封裝半導體晶粒頂部與底部立體圖；圖3A、3B、3C、3D、3E、與3F依照本發明之一實施例，顯示形成嵌入式晶粒封裝之各個階段；及圖4、5、與6為示意截面圖，其顯示在實行本發明中某些可能的實施例。
32．．．基座
34．．．半導體晶粒
36．．．半導體晶粒
56．．．焊塊
58．．．嵌入式晶粒封裝

Claims (21)

  1. 一種用於形成一嵌入式多晶片封裝之方法，其包括以下步驟：形成一載體，其具有複數個空穴；於該等空穴之每一者中置入一電裝置；形成一第一介電層，其圍繞並位於每一個該等電裝置之上且位於該載體之諸上表面之上；形成若干第一層級通孔，其貫穿該第一介電層至每一個該等電裝置上之諸選定焊墊；形成複數個第一金屬導體，其每一個與一選定焊墊接觸並延伸一段距離遠離該等第一層級通孔中之一者；形成一第二介電層，其位於該複數個第一金屬導體之上；在該第二介電層中形成若干第二層級通孔，其位於該複數個第一金屬導體之上；在該等第二層級通孔中形成複數個第二金屬導體，該等第二金屬導體之每一者接觸該等第一金屬導體中之一者；及形成複數個焊塊，其每一者耦合於該複數個第二金屬導體之一者。
  2. 如請求項1之方法，其中該載體藉由一鑄模程序而形成。
  3. 如請求項1之方法，其包含將該電裝置附接於該載體之 額外的步驟。
  4. 如請求項1之方法，其中該電裝置為一主動裝置。
  5. 如請求項1之方法，其中該電裝置為一被動裝置。
  6. 如請求項1之方法，其中該第一介電層藉由一層合程序而形成。
  7. 如請求項6之方法，其中該等通孔藉由雷射鑽孔而形成。
  8. 如請求項6之方法，其中該等通孔藉由微影蝕刻而形成。
  9. 如請求項1之方法，其中該等電裝置之至少一者為一主動裝置且該等電裝置之至少另一者為一被動裝置。
  10. 如請求項1之方法，其中預鑄模該載體以提供若干空穴以用於固持具有高度和不同寬度的多個電裝置。
  11. 一種用於形成一嵌入式多晶片封裝之方法，其包括以下步驟：形成一預鑄模載體，其具有複數個空穴；於該等空穴之每一者中置入一電裝置；形成一第一介電層，其圍繞並位於每一個該等電裝置之上且位於該載體之諸上表面之上；形成若干第一層級通孔，其貫穿該第一介電層至每一個該等電裝置上之諸選定焊墊；形成複數個第一金屬導體，其每一個填充一第一層級通孔且接觸一焊墊且延伸一段距離遠離該等第一層級通孔中之一者，且一或多個第一金屬導體接觸二個焊墊； 形成一第二介電層，其位於該複數個第一金屬導體之上；在該第二介電層中形成若干第二層級通孔，其位於該等第一金屬導體之上；在該第二介電層上以及於該等第二層級通孔中形成若干第二金屬導體以接觸在該等第二層級通孔中之該等第一金屬導體中之一者；及形成複數個焊塊，其每一個耦合於該等第二金屬導體中之一者。
  12. 如請求項11之方法，其中該預鑄模載體提供若干空穴以用於固持多個不同高度或不同寬度或高度及寬度皆不同之電裝置。
  13. 一種嵌入式晶粒封裝，其包括：一預鑄模載體，其具有一第一電裝置於該載體之一第一空穴內及一第二電裝置於該載體之一第二空穴內；一第一介電層，其覆蓋除位於該第一和該第二電裝置之選定焊墊之上的諸通孔之外的該等電裝置之側面與頂部；在該第一介電層上，複數個第一金屬導體，其每一者與該等通孔中之該等焊墊之至少一者接觸且至少一第一金屬導體與每一晶粒之至少一焊墊接觸；額外的一個或多個介電層，其位於該等第一金屬導體與該第一介電層之上，其中該一個或多個介電層之一頂層具有若干開口，其具有電連接至該複數個第一金屬導 體之至少一者之金屬化；及複數個焊塊，其從每一個該等開口突出。
  14. 如請求項13之封裝，其中該第一和該第二電裝置皆為主動裝置。
  15. 如請求項13之封裝，其中該等電裝置中之一者為一主動裝置而該等電裝置中之另一者為一被動裝置。
  16. 如請求項13之封裝，其進一步包含複數個第二金屬導體，其每一個耦合於該複數個第一金屬導體之至少一者。
  17. 如請求項13之封裝，其中該等焊塊之至少一者被形成為電連接至該複數個第一金屬導體中之一者。
  18. 一種嵌入式晶粒封裝，其包括：一預鑄模載體，其具有一第一電裝置於該載體之一第一空穴內及一第二電裝置於一第二空穴內；一第一介電層，其覆蓋除位於該第一及該第二電裝置之諸選定焊墊之上的通孔之外的該等電裝置之側面與頂部；複數個第一金屬導體，其每一者藉由延伸貫穿該等通孔與該等焊墊之至少一者接觸且至少一第一金屬導體與每一晶粒之至少一焊墊接觸；額外的一個或多個介電層，其位於該複數個第一金屬導體與該第一介電層之上；其中該一個或多個介電層之一頂層具有若干開口，其具有耦合於該複數個第一金屬導體之至少一者之複數個 第二金屬導體下部；及第二複數個焊塊，其從每一個該等開口突出；其中該等焊塊之至少一者被置於該電裝置之側周界之內，且該等焊塊之至少一者形成至該第二複數個金屬導體之一者之一直接電連接。
  19. 如請求項18之封裝，其中該第一和該第二電裝置皆為主動裝置。
  20. 如請求項18之封裝，其中該等電裝置中之一者為一主動裝置而該等電裝置中之另一者為一被動裝置。
  21. 如請求項18之封裝，其中該等焊塊之至少一者被形成為電連接至該複數個第一金屬導體中之一者。
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