TWI402951B - 無鉛半導體封裝件 - Google Patents

無鉛半導體封裝件 Download PDF

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TWI402951B
TWI402951B TW095119967A TW95119967A TWI402951B TW I402951 B TWI402951 B TW I402951B TW 095119967 A TW095119967 A TW 095119967A TW 95119967 A TW95119967 A TW 95119967A TW I402951 B TWI402951 B TW I402951B
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Taiwan
Prior art keywords
pin
lead
package substrate
free
die
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TW095119967A
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English (en)
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TW200707686A (en
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Raj N Master
Srinivasan Ashok Anand
Srinivasan Parthasarathy
Yew Cheong Mui
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Advanced Micro Devices Inc
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Publication of TWI402951B publication Critical patent/TWI402951B/zh

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    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C13/00—Alloys based on tin
    • C22C13/02—Alloys based on tin with antimony or bismuth as the next major constituent
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
    • B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
    • B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
    • B23K35/262—Sn as the principal constituent
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
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    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
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    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
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    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
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    • H05K2201/10674—Flip chip
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    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/047—Soldering with different solders, e.g. two different solders on two sides of the PCB

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Description

無鉛半導體封裝件
本發明大致係有關半導體裝置封裝，且詳而言之，係有關具有有機基板之半導體封裝件。
有關極大規模整合技術之高密度與性能之逐步提升的需求創造了在電路元件與外部的電性電路之間電性連接設計與實作的重大挑戰。積體電路(IC)裝置，不論是單獨的主動(active)裝置、單獨的被動裝置、在單一晶片內的多個主動裝置、或在單一晶片內的多個被動與主動裝置，在該些裝置與其他電路元件或結構之間需要適當的輸入/輸出(I/O)連接。
半導體裝置的裝置小型化與總是增加的密度需要總是增加的I/O端數目與電性連接的改良。支持增加裝置密度的一種技術包含從周邊引線接合(wire bonding)至區域陣列晶片互連的移動。區域陣列互連封裝技術的一例子是覆晶(flip chip)技術。在覆晶技術中，在晶粒(die)之表面上之銲錫凸塊(solder bump)的大區域陣列直接地將”覆接的”晶粒(“flipped”die)耦合至在封裝件基板之表面上之各自的銲墊(solder pad)。在一個實作中，銲接大量的插針導腳(pin lead)至在封裝件基板之相對表面上之各自的填錫(solder fillet)，導致了插針柵格陣列(pin grid array)封裝件。該插針柵格陣列封裝件容納了增加的I/O端數目並在晶片下直接提供電信號。
目前，使用鉛(Pb)當作銲錫(solder)的主要成分，例如高達95wt%的銲錫可能是鉛(Pb)。因此，在銲錫凸塊中的銲錫、在封裝件基板之晶粒面上的銲墊、與在封裝件基板之插針面上的填錫的使用，轉變成鉛(Pb)之普遍與廣泛的使用。然而，鉛(Pb)之替換物是高度所希望的，因為例如在電子電路中，有關環境保護的規定需要排除鉛(Pb)。這樣的需求創造了在銲錫材料中取代鉛(Pb)的重大挑戰。如上述討論之插針柵格陣列之例子所顯示，在半導體封裝技術中，包含鉛(Pb)的銲錫係最廣泛使用的互連材料。
然而，將在銲錫中長期建立使用的鉛(Pb)以其他材料取代意味著重大的挑戰。例如，必須維持處理”溫度階層(temperature hierarchy)”而須製作可靠的電接點與機械連接。例如，在覆晶技術中，處理溫度階層要求使用用於插針銲錫的填錫，該等填錫具有低於有機基板分解溫度之回銲(reflow)溫度，亦即使銲錫的流動足以形成電性連接的溫度。此外，在封裝件基板的晶粒面上的銲墊中使用的銲錫應該具有低於使用在插針銲錫中之填錫中的銲錫之回銲溫度。
因此，在本技術領域中有需要將在銲錫中長期確立使用的鉛(Pb)以其他材料取代，而維持可靠的電接點與所需的機械強度，並也符合在組合半導體封裝件所需的處理溫度階層，例如在具有機基板之插針柵格陣列封裝件中組合覆晶。
本發明係插針對無鉛(lead－free)半導體封裝件。本發明針對並解決本技術領域中以其他材料取代在銲錫中的鉛(Pb)的需求，而維持可靠的電接點(electrical contact)與所需的機械強度，並也符合在組合半導體封裝件中所需的處理溫度階層(hierarchy)。
在一個實施例中，本發明包含封裝件基板，該封裝件基板具有一些在封裝件基板之晶粒面上之晶粒銲墊(die solder pad)，以及一些在封裝件基板之插針面上之插針填錫(pin solder fillet)。該等晶粒銲墊具有低於該插針填錫之回銲(reflow)溫度的回銲溫度，而該等插針填錫則具有低於該封裝件基板之分解溫度的回銲溫度。在本實施例的一個實作中，該等插針填錫可包括約90wt%至約99wt%之間的錫以及約10wt%至1wt%的銻。在此實作中，該插針填錫回銲溫度係在約235℃與約247℃之間，其低於該封裝件基板的分解溫度，亦即低於約275℃。
在一個實作中，該等晶粒銲墊可包括約4wt%至約8wt%之間的鉍、約2wt%至約4 wt%的銀、約0 wt %至約0.7 wt %的銅、以及約87wt%至約92wt%的錫。在另一個實作中，該等晶粒銲墊可包括約7%至約20%之間的銦、約2 wt %至約4.5 wt %之間的銀、約0wt%至約0.7wt%之間的銅、約0wt%至約0.5wt%之間的銻、以及約74.3wt%至約90 wt %之間的錫。在這些實作中，該晶粒銲墊回銲溫度係在約170℃與約225℃之間。在本發明之所有實施例中，該插針填錫回銲溫度與該晶粒銲墊回銲溫度皆低於該封裝件基板的分解溫度，亦即低於約275℃。在反覆閱讀下列之詳細描述與伴隨之圖式後，對於熟知本技術領域之人而言，本發明之其他特徵與優點將會變得更加容易而明顯。
本發明係插針對無鉛半導體封裝件。下列描述包含有關於本發明實作之特定的資訊。熟知本技術領域的人士將會了解本發明可以不同於在本文中特別討論的方式實行。此外，並不會討論本發明的一些特定細節以免模糊了本發明。
本發明之圖式與伴隨的詳細描述係僅有關本發明之示範的實施例。為了保持簡潔，本發明的其他實施例並不會特別描述於本文中也不會特別藉由本發明之圖式說明。應牢記，除非有用別的方式提及，不然在圖式中相似或對應的元件可以相似或對應的元件符號表示。
為了提供特定範例的目的與簡化說明本發明的概念，本文涉及具有有機封裝件基板的覆晶封裝件。然而，應了解本發明並不限制於覆晶封裝件或具有有機基板之封裝件。如第1圖所示，覆晶承載件(carrier)封裝件10包含IC半導體裝置或IC晶粒1，其藉由一些銲錫凸塊2機械地與電性地附著在封裝件基板4的晶粒面，該等銲錫凸塊2則連接至在封裝件基板4上對應的晶粒銲墊3。藉由遍佈封裝件基板4之內部引線(沒有顯示於圖中)，使晶粒銲墊3電性地連接至I/O插針導腳6。藉由插針填錫5，使插針導腳6銲接至封裝件基板4的插針面。使用插針導腳6以提供電性連接至外部電路。使用”被動銲墊8”(對用於附著被動元件7至封裝件基板4之銲墊8的簡略說明)使被動元件7附著至封裝件基板4。
在沒有本發明的情況下，銲錫凸塊2、晶粒銲墊3、插針填錫5、與被動銲墊8在銲錫材料中包含大約30%至97wt%的鉛(Pb)。本發明針對並解決在這些銲錫點中取代鉛(Pb)或減少銲錫的鉛(Pb)含量至不超過約0.1wt%的需求。本發明也針對與解決在尋找與使用合適的銲錫材料的挑戰，該等銲錫材料可以形成電性地與機械地可靠的銲錫接合點(joint)並具有熔化溫度(melting temperature)其適合於例如在覆晶組合製程中之製程溫度階層(process temperature hierarchy)。
在覆晶組合製程中製程溫度階層需要在溫度階層鏈(chain)的頂部上組合插針導腳6。用於經由插針填錫5附著插針導腳6至有機封裝件基板4的處理溫度應該高於在覆晶組合中之任何其他的銲錫接合點，但應該低於有機封裝件基板4之分解溫度，該分解溫度可例如約275℃。對插針填錫5之高回銲處理溫度的需求係起因於在後續牽涉到溫度的組合步驟期間插針導腳6不應移動的需求。
用於IC晶粒組合製程之晶粒銲墊3的處理溫度應該低於用於插針填錫5的溫度以避免在回銲製程期間插針導腳6的移動。用於被動組合之被動銲墊8應該也具有低於用於插針填錫5之處理溫度以防止插針移動，並低於或相等於用於晶粒組合製程的晶粒銲墊3。為了防止銲錫凸塊2的熔化，其熔化溫度應該相等於或大於晶粒銲墊3與被動銲墊8。
接置插針導腳6在有機封裝件基板4的插針面表面上的一種技術，包括使用適當的銲錫合金以塗覆金屬化墊(metallized pad)，該等金屬化墊當作插針導腳6的登陸部位(landing site)。這些插針然後定位於被塗覆之金屬化墊上，在本發明中稱其為插針填錫5，且使銲錫回銲以連結該等插針至封裝件基板4。
如上所述，用於附著插針導腳6至有機封裝件基板4上的金屬化銲(亦即插針填錫5)一個需求，係銲接溫度不能高於有機封裝件基板4的分解溫度，而不會不利地危及有機基板的機械完整性。根據本發明的各種實施例，用於連結插針導腳6至有機封裝件基板4的無鉛銲錫形成強的機械接合能夠抵抗拉、放置(placement)、或測試(亦即插拔(socketing)組合的封裝件)，而保持好的電信號。
依照本發明的一個實施例，有機基板，如第1圖之有機封裝件基板4，包含藉由無鉛插針填錫5連結至各自的導電墊之一些插針導腳6，因此完成沒有鉛(Pb)或有探測不到的低量的鉛(Pb)(例如不大於約0.1wt%的鉛(Pb))之銲錫系統。在一個實作中，本發明合適的銲錫成分可以被配製，例如包括約90wt%至約99wt%的錫(Sn)以及約10wt%至約1wt%的銻(Sb)。
在本發明的實施例中，在有機封裝件基板4上的插針填錫5具有大於約230℃的回銲溫度，亦即使銲錫之流動足以形成電性連接的溫度，例如從約235℃至約247℃。因此，藉由在從約250℃至約270℃之溫度回銲插針填錫5，可使插針導腳6機械地與電性地連結至金屬化。第2圖之表1係依照本發明的一個實施例，說明示範之無鉛銲錫合金的成分與其熔化特性，以用於在封裝件基板4上形成插針填錫5。
如第2圖之表1所示，各種用於插針填錫5的銲錫合金成分包括約90wt%至約99wt%的錫(Sn)以及約10wt%至約1wt%的銻(Sb)，並具有固相溫度(solidus temperature)範圍從241℃至235℃與液相溫度(liquidus temperature)範圍從247℃至235℃。所有這些銲錫合金成分具有低於有機基板封裝件4之分解溫度的液相溫度，亦即低於275℃。此外，所有這些用於插針填錫5之銲錫合金成分之回銲溫度高於晶粒銲墊3與被動銲墊8的回銲溫度。在一個實施例中，插針填錫5與晶粒銲墊3之各自的回銲溫度之差異係至少10℃至15℃。在另一個實施例中，此差異為至少5℃。
在本發明之另一個實施例中，用於附著IC晶粒1至封裝件基板4的晶粒銲墊3也是無鉛的，且進一步該無鉛晶粒銲墊3具有低於插針填錫5的回銲溫度，因此避免插針導腳6的移動。在這個實施例中，位在有機封裝件基板4上的晶粒銲墊3不包括鉛(Pb)或包括探測不到的低量的鉛(Pb)，例如低於約0.1wt%的鉛(Pb)。
根據本實施例，本發明的各種實作包含合適的晶粒銲墊3，其包括約4wt%至8wt%之間的鉍、約2wt%至4wt%之間的銀、約0wt%至0.7wt%之間的銅、以及約87wt%至92wt%之間的錫。在本實施例之其他實作中，晶粒銲墊3包括約7wt%至20wt%之間的銦、約2wt%至4.5wt%之間的銀、約0wt%至0.7wt%之間的銅、約0wt%至0.5wt%之間的銻、以及約74.3wt%至90wt%之間的錫。
根據本發明之上述實施例，位在有機封裝件基板4上的晶粒銲墊不包括鉛(Pb)或包括探測不到的低量的鉛(Pb)，例如低於約0.1wt%的鉛(Pb)。第3圖之表2說明使用在晶粒銲墊3中的各種示範銲錫合金成分以完成本實施例之優點。如上述所討論，依照本發明的此實施例與顯示於第3圖之表2的特定示範實作，利用新與新穎的銲錫合金當作晶粒銲墊3以用於互連IC晶粒1至有機封裝件基板4。在本實施例的各種實作中，用於晶粒銲墊3的銲錫具有不低於170℃且不高於225℃的回銲溫度，亦即使銲錫的流動足以形成電性連接的溫度。
更具體地，如第3圖之表2所示，用於晶粒銲墊3的各種銲錫合金成分具有固相溫度範圍從175℃至204℃與液相溫度範圍從185℃至216℃。所有這些銲錫合金成分具有低於有機基板封裝件4的分解溫度之液相溫度，亦即低於275℃。此外，所有這些用於晶粒銲墊3的銲錫合金成分之回銲溫度低於在插針填錫5的回銲溫度，亦即低於230℃。
因此，在本技術領域有需要將在銲錫中長期確立使用的鉛(Pb)以其他材料取代，而維持可靠的電接點與所需的機械強度，並也符合在組合半導體封裝件所需的處理溫度階層，例如在具有機基板的插針柵格陣列封裝件中組合覆晶。從本發明示範實施例的上述描述，明顯可知各種可用於實行本發明的概念而不脫離其範圍的技術。例如，雖已揭露特定無鉛銲錫材料的成分與其對應之回銲溫度，惟該揭露成分的其他變化顯然地落在本發明的範圍內。此外，雖已利用特定參考一些實施例而描述本發明，惟熟知本技術領域之人士會了解可以在形式與細節上作改變而不脫離本發明的精神與範圍。所描述的示範實施例是在各方面視為說明性的而不是限制性的。也應當了解本發明不限制描述於本文中特定的示範實施例，而能在不脫離本發明之範圍下，具有許多重新配置、修改、與替換。
因此，已描述了無鉛半導體封裝件。
1．．．IC晶粒
2．．．銲錫凸塊
3．．．晶粒銲墊
4．．．封裝件基板
5．．．插針填錫
6．．．插針導腳
7．．．被動元件
8．．．被動銲墊
10．．．覆晶承載件封裝件
第1圖係顯示依照本發明的一個實施例之示範的覆晶承載件封裝件，包括封裝件基板；第2圖係說明依照本發明的一個實施例之示範的無鉛銲錫合金的成分與其熔化特性，以用於在封裝件基板上形成插針填錫；以及第3圖係說明依照本發明的一個實施例之示範的無鉛銲錫合金的成分與其熔化特性，以用於在封裝件基板上形成晶粒銲墊。
1．．．IC晶粒
2．．．銲錫凸塊
3．．．晶粒銲墊
4．．．封裝件基板
5．．．插針填錫
6．．．插針導腳
7．．．被動元件
8．．．被動銲墊
10．．．覆晶承載件封裝件

Claims (20)

  1. 一種封裝件基板，具有晶粒面與插針面、位在該晶粒面上的複數個無鉛晶粒銲墊、以及位在該插針面上的複數個無鉛插針填錫；該複數個無鉛晶粒銲墊具有晶粒銲墊回銲溫度以及該複數個無鉛插針填錫具有插針填錫回銲溫度，其中該晶粒銲墊回銲溫度係小於該插針填錫回銲溫度，且其中該插針填錫回銲溫度係小於該封裝件基板之分解溫度；該複數個無鉛晶粒銲墊包括約4wt%至約8wt%之間的鉍、約2wt%至約4wt%的銀、約0wt%至約0.7wt%的銅、以及約87wt%至約92wt%的錫。
  2. 如申請專利範圍第1項之封裝件基板，其中，該晶粒銲墊回銲溫度係在約170℃與約225℃之間。
  3. 如申請專利範圍第1項之封裝件基板，其中，該封裝件基板之該分解溫度係至少275℃。
  4. 如申請專利範圍第1項之封裝件基板，其中，該插針填錫回銲溫度係至少230℃。
  5. 如申請專利範圍第4項之封裝件基板，其中，該複數個無鉛插針填錫包括約90wt%至約99wt%之間的錫以及約10wt%至1wt%的銻。
  6. 一種封裝件基板，具有晶粒面與插針面、位在該晶粒面上的複數個無鉛晶粒銲墊、以及位在該插針面上的複數個無鉛插針填錫；該複數個無鉛晶粒銲墊具有晶粒銲墊回銲溫度以及 該複數個無鉛插針填錫具有插針填錫回銲溫度，其中該晶粒銲墊回銲溫度係小於該插針填錫回銲溫度，且其中該插針填錫回銲溫度係小於該封裝件基板之分解溫度；該複數個無鉛晶粒銲墊包括約7wt%至約20wt%之間的銦、約2wt%至約4.5wt%之間的銀、約0wt%至約0.7wt%之間的銅、約0wt%至0.5wt%之間的銻、以及約74.3wt%至約90wt%之間的錫。
  7. 如申請專利範圍第6項之封裝件基板，其中，該晶粒銲墊回銲溫度係在約170℃與約225℃之間。
  8. 如申請專利範圍第6項之封裝件基板，其中，該封裝件基板之該分解溫度係至少275℃。
  9. 如申請專利範圍第6項之封裝件基板，其中，該插針填錫回銲溫度係至少230℃。
  10. 如申請專利範圍第9項之封裝件基板，其中，該複數個無鉛插針填錫包括約90wt%至約99wt%之間的錫以及約10wt%至1wt%的銻。
  11. 一種封裝件基板，具有晶粒面與插針面、位在該晶粒面上的複數個無鉛晶粒銲墊、以及位在該插針面上的複數個無鉛插針填錫；該複數個無鉛晶粒銲墊具有晶粒銲墊回銲溫度以及該複數個無鉛插針填錫具有插針填錫回銲溫度，其中該晶粒銲墊回銲溫度係小於該插針填錫回銲溫度，且其中該插針填錫回銲溫度係小於該封裝件基板之分解溫度；該複數個無鉛插針填錫包括約90wt%至約99wt% 之間的錫以及約10wt%至1wt%的銻。
  12. 如申請專利範圍第11項之封裝件基板，其中，該插針填錫回銲溫度係至少230℃。
  13. 如申請專利範圍第11項之封裝件基板，其中，該插針錫回銲溫度係在約235℃與約247℃之間。
  14. 如申請專利範圍第11項之封裝件基板，其中，該封裝件基板之該分解溫度係至少275℃。
  15. 如申請專利範圍第11項之封裝件基板，其中，該晶粒銲墊回銲溫度係在約170℃與約225℃之間。
  16. 如申請專利範圍第15項之封裝件基板，其中，該複數個無鉛晶粒銲墊包括約4wt%至約8wt%之間的鉍、約2wt%至約4wt%的銀、約0wt%至約0.7wt%的銅、以及約87wt%至約92wt%的錫。
  17. 如申請專利範圍第15項之封裝件基板，其中，該複數個無鉛晶粒銲墊包括約7wt%至約20wt%之間的銦、約2wt%至約4.5wt%之間的銀、約0wt%至約0.7wt%之間的銅、約0wt%至約0.5wt%之間的銻、以及約74.3wt%至約90wt%之間的錫。
  18. 如申請專利範圍第11項之封裝件基板，其中，覆晶係位在該晶粒面上。
  19. 如申請專利範圍第18項之封裝件基板，其中，該覆晶包含複數個無鉛銲錫凸塊，其中該複數個無鉛銲錫凸塊的每一個附著在該複數個無鉛晶粒銲墊的對應的其中一個。
  20. 如申請專利範圍第11項之封裝件基板，其中，插針柵格陣列係位在該插針面上，該插針柵格陣列包含複數個插針導腳，該複數個插針導腳的每一個係附著在該複數個無鉛插針填錫的對應的其中一個。
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KR20080024217A (ko) 2008-03-17
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GB2442391A (en) 2008-04-02

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