TWI398938B - 可堆疊式積體電路封裝 - Google Patents

可堆疊式積體電路封裝 Download PDF

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TWI398938B
TWI398938B TW097138327A TW97138327A TWI398938B TW I398938 B TWI398938 B TW I398938B TW 097138327 A TW097138327 A TW 097138327A TW 97138327 A TW97138327 A TW 97138327A TW I398938 B TWI398938 B TW I398938B
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die
integrated circuit
lead fingers
packaged integrated
sealing material
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TW200924147A (en
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David J Corisis
Chin Hui Chong
Choon Kuan Lee
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Micron Technology Inc
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Description

可堆疊式積體電路封裝
本發明大體而言係針對封裝積體電路裝置之領域，且更特定言之，係針對一種可堆疊式積體電路封裝。
積體電路技術使用電氣裝置(例如，電晶體、電阻器、電容器等)來規劃功能電路之大量陣列。此等電路之複雜性要求使用數目不斷增加之鏈接電氣裝置，以使得電路可執行其預期功能。隨著電晶體之數目增加，積體電路尺寸縮小。半導體工業中之一挑戰在於開發用於電連接及封裝在同一及/或不同晶圓或晶片上製造之電路裝置的改良方法。一般而言，需要在半導體工業中建構在矽晶片/晶粒上佔據較少表面積之電晶體。
在半導體裝置總成之製造中，最通常將單一半導體晶粒併入於每一密封式封裝中。使用許多不同封裝式樣，包括雙列式封裝(dual inline packages；DIP)、鋸齒型單列式封裝(zig-zag inline packages；ZIP)、小外形J形彎頭(small outline J-bends；SOJ)、薄小外形封裝(thin small outline packages；TSOP)、塑膠有引線晶片載體(plastic leaded chip carriers；PLCC)、小外形積體電路(small outline integrated circuits；SOIC)、塑膠四方扁平封裝(plastic quad flat packs；PQFP)及互相交叉引線框(interdigitated leadframe；IDF)。一些半導體裝置總成在密封之前被連接至諸如電路板之基板。在一些應用中，積體電路晶粒被封裝在堆疊組態中以減小積體電路產品所佔據之地塊空間。製造商面臨著持續壓力來減小經封裝之積體電路裝置之尺寸且在封裝積體電路裝置時增大封裝密度。
參考結合隨附圖式所作出之以下描述可理解本發明，其中相似參考數字識別相似元件。
本發明之說明性實施例如下所述。為清楚起見，本說明書中並未描述實際實施之所有特徵。當然，應瞭解，在任何此實際實施例之開發中，必須做出眾多特定實施決策以達成開發者之特定目標，諸如，順應系統相關及商業相關之約束，其將自一實施至另一實施而變化。此外，應了解，此開發努力可能為複雜且耗時的，但對於受益於本揭示案之一般熟習此項技術者而言將不過為常規任務。
儘管將圖式所示之各種區域及結構描繪為具有極精確之明顯組態及輪廓，但熟習此項技術者認識到，實際上，此等區域及結構不如圖式中所指示的一樣精確。另外，與經製造之裝置上之該等特徵或區域的尺寸相比，圖式中所描繪之各種特徵及摻雜區域的相對尺寸可被誇大或減小。然而，包括所附圖式以描述及解釋本文所揭示之發明之說明性實例。
如圖1及圖2所示，在一說明性實施例中，兩個說明性可堆疊式封裝10A、10B堆疊在一起。封裝10A、10B之每一者包含複數個積體電路晶粒12，該複數個積體電路晶粒12藉由黏著或環氧樹脂材料13而彼此耦接。晶粒12被安置於傳統引線框之腳座20之上，該傳統引線框包含複數個引線或引線指狀物16。藉由說明性線接合件18將積體電路晶粒12電耦接至引線指狀物16。例如封膠之密封材料14形成於上述各種組件之周圍。如圖式中所觀察，引線指狀物16為彎曲的或摺疊的，使得引線指狀物16之部分16A安置於例如封膠之密封材料14之頂面14A之上。
亦應注意到，封裝10A、10B之每一者具有大體上平坦之底面17。藉由使用導電黏著劑或導電膏(未圖示)將封裝10A、10B電耦接至彼此，該導電黏著劑或導電膏安置於在每一封裝10A及10B上之引線指狀物16的嚙合部分之間。實務上，如圖3所示，藉由各種已知技術可將例如封裝10A之此封裝之底面電耦接至諸如印刷電路板50之另一結構。舉例而言，導電膏或黏著劑(未圖示)可塗覆至印刷電路板50上之襯墊52。若需要，亦可向腳座20提供接點54。
亦應注意到，在封裝10A、10B之每一封裝中的四個說明性晶粒12的描述僅以實例方式提供。因為熟習此項技術者在完整地閱讀本申請案後將意識到，本文所揭示之發明可用於在封裝10A或10B之一封裝內封裝任何數目的此晶粒。此外，在每一封裝10A、10B中之晶粒12的數目不必相同。另外，在例如封裝10A之每一封裝中之晶粒12可具有相同或不同的實體尺寸。最後，儘管圖1及圖2描繪了兩個說明性堆疊封裝10A、10B，但本發明可用於將任何所要數目之此等封裝堆疊在一起，例如，如3至5個此等封裝。因此，本文所揭示之發明具有廣泛應用且不應被視作限於本文所揭示之特定細節。
在圖1所展示之實施例中，在封裝10A與10B之間提供有氣隙23。若需要，如圖2所示，可形成或安置導熱材料24來填充氣隙23，藉此為堆疊封裝10A、10B提供增強的熱傳遞能力。在一說明性實施例中，導熱材料24可包含導熱膏或導熱帶，且該導熱材料可具有大約100μm至200μm之厚度。此等導熱材料為熟習此項技術者所熟知。
圖4係圖1中封裝10B之頂部之平面圖。如其中所示，五個說明性引線指狀物16僅沿積體電路晶粒12之邊延伸。實務上，實際產品可具有大量此等引線指狀物16，然而，為清楚起見，僅十個此等引線指狀物16展示於圖4中。當然，在其他應用中，引線指狀物16可圍繞封裝10B之整個周邊延伸或僅沿封裝10B之末端延伸。因此，本文所描述之說明性排列不應被視作本發明之限制。
圖5A至圖5G描繪一用於形成本文所描述之可堆疊式封裝之說明性製程流程。如圖5A所示，引線框30被安置於犧牲支撐結構26之上。引線框30包含說明性晶粒腳座20及複數個引線指狀物16。應注意到，出於說明之目的而示意性地描繪圖中所描繪之引線框30，圖式並不按比例繪製。在實際裝置中，本文所描述之各個組件及結構之相對尺寸可能不同於本文所描述之相對尺寸。引線框30可具有傳統構造且引線框可由各種導電材料(例如，銅、合金42等)製成。藉由黏著材料(未圖示)或使用其他類似技術可將引線框30初始地緊固於犧牲結構26。
如圖5B所示，藉由黏合材料(未圖示)將第一晶粒12A緊固於腳座20之上。若需要，藉由晶粒12A之底面15上之接觸襯墊(未圖示)，可將晶粒12A電耦接至腳座20。藉由塗覆導電膏或其他類似材料(未圖示)可建立電氣連接。另外，在一些應用中，晶粒12A可以一方式耦接至腳座20，以提高晶粒12A與腳座20間之熱傳遞。舉例而言，可提供設計用來提供增強之熱傳遞能力之黏著劑來增強晶粒12A與腳座20間之熱傳遞的效果。晶粒12A亦可電耦接至引線指狀物16之一或多者。在一說明性實施例中，線接合件18可用於此目的。藉由使用已知技術，線接合件18可導電地耦接至在晶粒12A上之接合襯墊(未圖示)，且導電地耦接至引線指狀物16。其後，黏著材料層13被塗覆至晶粒12A之頂面19來附接另一晶粒12B，如圖5C所示。該過程基本上重複用於附接說明性晶粒12C(圖5D)及說明性晶粒12D(圖5E)。
接下來，如圖5F所示，密封材料14形成於圖5E中所描繪之結構之周圍。藉由各種已知成型技術(例如轉移成型)及材料(例如封膠)可形成密封材料14。側面14B之釋放角可視特定應用而改變。在一說明性實施例中，釋放角可為大約8度至20度。
接下來，如圖5G所示，引線指狀物16係彎曲或摺疊的，使得引線指狀物16之部分16A被安置於密封材料14之頂面14A之部分之上。注意，摺疊之引線指狀物16的角度不必與密封材料14之側面14B的角度相匹配。
在圖5G中所描述之裝置可其後經受各種不同的測試，以證實裝置之用以執行其預期功能之性能及/或能力。事實上，若需要，可在製造裝置時的各階段來執行此測試。最終，目標僅為"已知良好"之堆疊封裝(例如，封裝10A、10B)，亦即，已通過一套所要的電氣及/或機械完整性測試之封裝。
上文中揭示之特定實施例僅為說明性的，因為獲得本文中教示的益處之熟習此項技術者可以不同但等效的方式修改並實踐本發明。舉例而言，在上文中陳述的製程步驟可以不同次序執行。此外，除以下申請專利範圍中所描述之外，並不意欲限制本文中展示之構造或設計之細節。因此，顯然可改變或修改以上所揭示之特定實施例，且認為所有此等變化在本發明之範疇及精神內。因此，本文中尋求之保護陳述於以下申請專利範圍中。
10A．．．可堆疊式封裝
10B．．．可堆疊式封裝
12．．．積體電路晶粒
12A．．．第一晶粒
12B．．．另一晶粒
12C．．．說明性晶粒
12D．．．說明性晶粒
13．．．黏著或環氧樹脂材料
14．．．密封材料
14A．．．密封材料之頂面
14B．．．密封材料之側面
16．．．引線指狀物
16A．．．引線指狀物之一部分
17．．．底面
18．．．線接合件
19．．．晶粒12A之頂面
20．．．晶粒腳座
23．．．氣隙
24．．．導熱材料
26．．．犧牲支撐結構
30．．．引線框
50．．．印刷電路板
52．．．襯墊
54．．．接點
圖1及圖2係本文所揭示之可堆疊式積體電路封裝之說明性實施例的橫截面圖；
圖3係描繪說明性實例之橫截面圖，其中本文所揭示之複數個可堆疊式積體電路封裝被操作地耦接至印刷電路板；
圖4係本文所揭示之可堆疊式積體電路封裝之說明性實施例的平面圖；及
圖5A至圖5G描繪可用於形成本文所描述之可堆疊式積體電路封裝之說明性製程流程。
儘管本文所揭示之發明易受各種修改及替代形式之影響，但其具體實施例已在圖式中以實例展示且在本文中加以詳細描述。然而，應瞭解，本文中特定實施例之描述並非意欲將本發明限制於所揭示之特定形式，而相反，本發明將涵蓋屬於由所附申請專利範圍界定之本發明之精神及範圍之內的所有修改、均等物及替代。
10B．．．可堆疊式封裝
12．．．積體電路晶粒
13．．．黏著或環氧材料
14．．．密封材料
14A．．．密封材料之頂面
16．．．引線指狀物
16A．．．引線指狀物之一部分
17．．．底面
18．．．線接合件
20．．．晶粒腳座
23．．．氣隙

Claims (20)

  1. 一種經封裝之積體電路裝置，其包含：一引線框，其包含一晶粒腳座及複數個引線指狀物；複數個積體電路晶粒，其係以一堆疊排列安置於該腳座上，其中該等晶粒之全部皆朝上且在相鄰晶粒之間具有一黏著層；複數個導電結構，用於將該複數個晶粒之每一者耦接至該等引線指狀物；及一密封材料體，其安置於該複數個晶粒及該複數個導電結構周圍，該密封材料體具有一頂面，其中該複數個引線指狀物被摺疊，使得該等引線指狀物之一部分被安置於該密封材料體之該頂面之上；以及該腳座具有不含該密封材料之一低側面。
  2. 如請求項1之裝置，其中該晶粒腳座及該等引線指狀物界定一大體上平坦之底面。
  3. 如請求項2之裝置，其中該複數個導電結構包含複數個線接合件，該等線接合件接附至該晶粒之一邊緣旁。
  4. 如請求項2之裝置，其中該複數個晶粒中之一第一晶粒係藉由一導電材料而耦接至該晶粒腳座。
  5. 如請求項2之裝置，其中該複數個積體電路晶粒係藉由黏著或環氧樹脂材料而彼此耦接。
  6. 一種堆疊總成，其包含：一第一經封裝之積體電路裝置及一第二經封裝之積體電路裝置，該第二經封裝之積體電路裝置堆疊於該第一 經封裝之積體電路裝置之上，該第一及第二經封裝之積體電路裝置之每一者包含：一引線框，其包含一晶粒腳座及複數個引線指狀物；複數個積體電路晶粒，其係以一堆疊排列安置於該腳座之一頂面上，其中在相鄰晶粒之間具有一黏著層；複數個導電結構，用於將該複數個晶粒之每一者耦接至該等引線指狀物；及一密封材料體，其係在該複數個晶粒及該複數個導電結構周圍，在該腳座的該頂面及側邊上具有該密封材料，但並非在該腳座之底面上，該密封材料體具有一頂面，其中該複數個引線指狀物被摺疊，使得該等引線指狀物之一部分被安置於該密封材料體之該頂面之上，以及一導熱膏或導熱膠布接觸該第二經封裝之積體電路之該晶粒腳座的該底面以及在第一積體電路封裝中該複數個晶粒的最上層者之一頂面。
  7. 如請求項6之總成，其中該第一經封裝之積體電路裝置及該第二經封裝之積體電路裝置之該等引線指狀物電耦接至彼此。
  8. 如請求項6之總成，其中該第二經封裝之積體電路裝置上之該等引線指狀物之一底面導電地耦接至該第一經封裝之積體電路裝置上之該等引線指狀物之該等部分之一 頂面，該等部分被安置於該密封材料體之該頂面之上。
  9. 如請求項6之總成，進一步包含一印刷電路板，該印刷電路板電耦接至該第一經封裝之積體電路裝置之該等引線指狀物。
  10. 如請求項9之總成，其中該印刷電路板藉由該晶粒腳座之該底面之一接點電耦接至該第一經封裝之積體電路裝置之該晶粒腳座。
  11. 如請求項6之總成，其中該第一及第二經封裝積體電路裝置、該晶粒腳座、該密封材料體及該等引線指狀物中至少一者界定一大體上平坦之底面。
  12. 如請求項11之總成，其中在該第一及第二經封裝積體電路裝置中至少一者中，該複數個導電結構包含複數個線接合件。
  13. 如請求項11之總成，其中在該第一及第二經封裝積體電路裝置中至少一者中，該複數個晶粒中之一第一晶粒係藉由一導電材料而耦接至該晶粒腳座。
  14. 如請求項11之總成，在該第一及第二經封裝積體電路裝置中至少一者中，其中該複數個積體電路晶粒係藉由黏著或環氧樹脂材料而彼此耦接。
  15. 一種用於封裝積體電路裝置之方法，其包含：附接一第一晶粒至一引線框之一腳座，該引線框包含複數個引線指狀物；將至少一個額外晶粒安置於該第一晶粒之上，該第一晶粒及該至少一個額外晶粒被電耦接至該複數個引線指 狀物，其中全部晶粒皆朝上且在相鄰晶粒之間具有一黏著層；形成一密封材料體，該密封材料體圍繞該第一晶粒及該至少一個額外晶粒，但並非在該腳座之該低側面上；及摺疊該複數個引線指狀物，使得該等引線指狀物之一部分被安置於該密封材料體之一頂面之上。
  16. 如請求項15之方法，其中附接該第一晶粒至該腳座包含藉由一導電材料將該第一晶粒附接至該腳座。
  17. 如請求項15之方法，其中該第一晶粒及該至少一個額外晶粒係由複數個線接合件而電耦接至該等引線指狀物。
  18. 如請求項15之方法，其中該等引線指狀物僅沿著該晶粒腳座之相對邊而安置。
  19. 如請求項17之方法，其中在將該至少一個額外晶粒安置於該第一晶粒上之前，將該第一晶粒電耦接至該等引線指狀物。
  20. 如請求項15之方法，其中該晶粒腳座、該密封材料體及該等引線指狀物界定一大體上平坦之底面。
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