TWI397616B - 利用有機表面鈍化及微差電鍍延遲進行由底部往上電鍍 - Google Patents

利用有機表面鈍化及微差電鍍延遲進行由底部往上電鍍 Download PDF

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Publication number
TWI397616B
TWI397616B TW098139365A TW98139365A TWI397616B TW I397616 B TWI397616 B TW I397616B TW 098139365 A TW098139365 A TW 098139365A TW 98139365 A TW98139365 A TW 98139365A TW I397616 B TWI397616 B TW I397616B
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TW
Taiwan
Prior art keywords
substrate
passivation film
trench
via structure
seed layer
Prior art date
Application number
TW098139365A
Other languages
English (en)
Chinese (zh)
Other versions
TW201026911A (en
Inventor
王政岳
坤華
陶龍
張鴻
Original Assignee
應用材料股份有限公司
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Filing date
Publication date
Application filed by 應用材料股份有限公司 filed Critical 應用材料股份有限公司
Publication of TW201026911A publication Critical patent/TW201026911A/zh
Application granted granted Critical
Publication of TWI397616B publication Critical patent/TWI397616B/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/46—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C25D5/022—Electroplating of selected surface areas using masking means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/46—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
    • H10P14/47—Electrolytic deposition, i.e. electroplating; Electroless plating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H10W20/0765—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches the thin functional dielectric layers being temporary, e.g. sacrificial layers

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Chemically Coating (AREA)
TW098139365A 2008-11-24 2009-11-19 利用有機表面鈍化及微差電鍍延遲進行由底部往上電鍍 TWI397616B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11754008P 2008-11-24 2008-11-24

Publications (2)

Publication Number Publication Date
TW201026911A TW201026911A (en) 2010-07-16
TWI397616B true TWI397616B (zh) 2013-06-01

Family

ID=42196702

Family Applications (1)

Application Number Title Priority Date Filing Date
TW098139365A TWI397616B (zh) 2008-11-24 2009-11-19 利用有機表面鈍化及微差電鍍延遲進行由底部往上電鍍

Country Status (6)

Country Link
US (1) US8293647B2 (cg-RX-API-DMAC10.html)
JP (1) JP5409801B2 (cg-RX-API-DMAC10.html)
KR (1) KR101368308B1 (cg-RX-API-DMAC10.html)
CN (1) CN102224574B (cg-RX-API-DMAC10.html)
TW (1) TWI397616B (cg-RX-API-DMAC10.html)
WO (1) WO2010059857A2 (cg-RX-API-DMAC10.html)

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CN102798471B (zh) * 2011-10-19 2015-08-12 清华大学 一种红外探测器及其制备方法
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US10381266B2 (en) 2012-03-27 2019-08-13 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US11437269B2 (en) 2012-03-27 2022-09-06 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
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CN104112697B (zh) * 2013-04-18 2017-09-15 中芯国际集成电路制造(上海)有限公司 一种改善铜填充质量的方法
JP6187008B2 (ja) * 2013-08-07 2017-08-30 大日本印刷株式会社 金属充填構造体の製造方法及び金属充填構造体
US9899234B2 (en) 2014-06-30 2018-02-20 Lam Research Corporation Liner and barrier applications for subtractive metal integration
US9349637B2 (en) * 2014-08-21 2016-05-24 Lam Research Corporation Method for void-free cobalt gap fill
US9997405B2 (en) 2014-09-30 2018-06-12 Lam Research Corporation Feature fill with nucleation inhibition
US9859124B2 (en) * 2015-04-17 2018-01-02 Taiwan Semiconductor Manufacturing Company Ltd Method of manufacturing semiconductor device with recess
US10170320B2 (en) 2015-05-18 2019-01-01 Lam Research Corporation Feature fill with multi-stage nucleation inhibition
US20160351493A1 (en) * 2015-05-27 2016-12-01 Macronix International Co., Ltd. Semiconductor device and manufacturing method for the same
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US10438847B2 (en) 2016-05-13 2019-10-08 Lam Research Corporation Manganese barrier and adhesion layers for cobalt
US10573522B2 (en) 2016-08-16 2020-02-25 Lam Research Corporation Method for preventing line bending during metal fill process
US10211099B2 (en) 2016-12-19 2019-02-19 Lam Research Corporation Chamber conditioning for remote plasma process
US10242879B2 (en) 2017-04-20 2019-03-26 Lam Research Corporation Methods and apparatus for forming smooth and conformal cobalt film by atomic layer deposition
KR102828798B1 (ko) 2018-12-05 2025-07-02 램 리써치 코포레이션 보이드 프리 (void free) 저응력 (low stress) 충진
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WO2020255772A1 (ja) * 2019-06-18 2020-12-24 東京エレクトロン株式会社 基板処理方法および基板処理装置

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Also Published As

Publication number Publication date
WO2010059857A3 (en) 2010-08-19
JP5409801B2 (ja) 2014-02-05
US20100130007A1 (en) 2010-05-27
JP2012510162A (ja) 2012-04-26
KR20110102374A (ko) 2011-09-16
TW201026911A (en) 2010-07-16
KR101368308B1 (ko) 2014-02-26
CN102224574B (zh) 2014-06-11
WO2010059857A2 (en) 2010-05-27
US8293647B2 (en) 2012-10-23
CN102224574A (zh) 2011-10-19

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