TWI392038B - 立式晶片尺寸封裝及其製造方法 - Google Patents

立式晶片尺寸封裝及其製造方法 Download PDF

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Publication number
TWI392038B
TWI392038B TW098118886A TW98118886A TWI392038B TW I392038 B TWI392038 B TW I392038B TW 098118886 A TW098118886 A TW 098118886A TW 98118886 A TW98118886 A TW 98118886A TW I392038 B TWI392038 B TW I392038B
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Taiwan
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wafer
bump
vertical
contacts
wafers
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TW098118886A
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English (en)
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TW201001579A (en
Inventor
Tao Feng
Anup Bhalla
Yueh Se Ho
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Alpha & Omega Semiconductor
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Publication of TW201001579A publication Critical patent/TW201001579A/zh
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Publication of TWI392038B publication Critical patent/TWI392038B/zh

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Description

立式晶片尺寸封裝及其製造方法
本發明一般涉及半導體封裝，特別是一種立式晶片尺寸封裝。
電子設備的小型化引導了更小型的半導體裝置的設計和製造。半導體裝置一般被封裝用於電連接印刷電路板的佈線。晶片尺寸封裝提供了半導體裝置尺寸上的封裝，從而最小化封裝所消耗的電路板空間。
如MOSFETs(metallic oxide semiconductor field effecttransistor金屬氧化物半導體場效應電晶體)的這類垂直傳導功率半導體裝置具有在裝置的第一表面上形成的兩個電極或接頭以及在裝置的第二表面上形成的一第三個電極或接頭。為了把電極焊接到印刷電路板上，一些傳統的晶片尺寸封裝所用的方法是把所有的電極佈置在裝置的同一側。例如，美國第6,646,329號專利公開了一個封裝，包括導線架及其上結合的晶片。該晶片被連接到所述導線架上，其背面(漏極接點)與從導線架上延伸出的源極引腳和柵極引腳共面。所公開的這個結構非常複雜。
另一個優先技術的晶片尺寸封裝包括一個晶片，其漏極側安裝在一個金屬夾下，或者其源極和柵極電極被設置與該金屬夾的延伸區域的邊緣表面共平面，或者其如美國第6,624,522號專利所公開。所公開的封裝使得在其被鑲嵌到電路板上後， 很難視覺檢測焊點。
美國第6,653,740號專利所公開的倒裝式晶片MOSFET結構具有一個垂直傳導半導體晶片，通過一個擴散器或傳導電極，該晶片的漏極層連接該晶片頂部的漏極電極。所公開的上述結構存在電阻增加以及活躍區域減少的問題。
同樣已知，可以通過傳導阻滯和傳導層來使得裝置電極與印刷電路板相連接。像這樣的一個結構在美國第6,392,305號專利中被公開，其中電極的晶片連接傳導阻滯焊接，後者進一步通過其側表面與印刷電路板相連接。美國第6,841,416號專利公開了一個晶片尺寸封裝，其具有上下兩個傳導層與晶片終端相連接。在上下傳導層同一側的表面上形成的電極表面與印刷電路板相應鏈結焊點相連接。在這些案例中，對於低成本生產結構或製造過程都過於複雜。
這就需要一種晶片尺寸封裝技術，其可以提供在晶片雙面都可裝置接觸的電連接、能看見清楚的焊點、減小的印刷電路板安裝面積。並且該晶片尺寸封裝的製造方法允許適量的批量生產。該晶片尺寸封裝只需要簡單的生產步驟並具有較低的生產成本。
本發明公開的一種立式晶片尺寸封裝克服了先前技術的不足，為了實現本發明的目的，其具有一個能夠在立式構型下與印刷電路板適配連接的晶片尺寸封裝，例如晶片的上下表面的平面直立於印刷電路板所在平面。凸起的晶片通過其兩側的電 引腳連接到印刷電路板上。
本發明的一方面是公開一種立式晶片尺寸封裝，其具有兩側都設有引腳的晶片，所述每一引腳都包含電連接其上的焊接球，從而形成一個突起的晶片。
本發明的另一方面是公開一種立式晶片尺寸封裝，其具有兩側都設有引腳的晶片，晶片第一側面上的每一引腳包含電連接其上的焊接球從而形成一個凸點晶片，晶片第二側面由一個焊接層組成，其電連接第二側面和一個印刷電路板上形成的傳道杆。
本發明的另一方面，一個立式晶片尺寸封裝包括一個第一晶片和一個第二晶片，二者相連形成共漏極配置，第一和第二晶片都具有形成在非漏極側的柵極觸點、源極觸點，每一柵極觸點和每一源極觸點都包括一個與其電連接的焊接球，從而形成一個凸點共漏極晶片。
本發明的另一方面，一個立式晶片尺寸封裝包括串聯相連的第一、第二、第三晶片，上述晶片中的每一個都具有柵極觸點、源極觸點和漏極接觸點，每一柵極觸點、每一源極觸點和每一漏極接觸點都包括一個與其電連接的焊接球，從而形成一個凸點串聯晶片。
本發明的另一方面，一個立式晶片尺寸封裝包括一個觸點形成在其兩側的晶片，形成在晶片的第一側的每一觸點都包括一個與其電連接的焊接球，從而形成一個凸點晶片
本發明的另一方面，製造一個立式晶片尺寸封裝的過程包括以下步驟： 提供一個前側具有鋁襯墊而後側具有背側金屬的晶圓；在所述晶圓後側形成鈍化層；在晶圓後側打開視窗；在鋁襯墊和打開的視窗上化學鍍鎳/金鍍層(Ni/Au)，以形成下部凸點金屬鍍層；在下部凸點金屬鍍層上設置焊接球；切割晶圓形成一組凸點晶片。
在本發明的另一方面，製造一個共漏極立式晶片尺寸封裝的過程包括以下步驟：提供前側具有鋁襯墊而後側具有背側金屬的兩個晶圓；化學鍍每一晶圓的前側並保護每一晶圓的後側，從而形成下部凸點金屬鍍層；測定兩個晶圓的晶片佈局是否相互匹配；如相互匹配，則焊接晶圓後側；否則當第二晶圓比第一晶圓小時，切割第二晶圓；將從第二晶圓上切割的晶片附在第一晶圓的後側；在下部凸點金屬鍍層上設置焊接球；切割晶圓形成一組共漏極凸點晶片。
本發明的另一方面，製造一個表面安裝立式晶片尺寸封裝的過程包括以下步驟：提供一個假片基底，其具有一組晶片區域；蝕刻穿透位於每一晶片區域的角的孔洞；採用銅表面電鍍假片基底；凹槽化每一晶片區域的頂部表面，以形成一個凹槽和一組 觸點；凹槽化每一晶片區域的底部表面，以形成一組觸點；底部表面的該組觸點中的每一個電連接相對應的頂部表面的那組觸點中的一個；在每一個晶片區域的頂部表面上安裝一組凸點晶片；成型封裝該組凸點晶片；切割假片基底，形成表面安裝立式晶片封裝。
以上是本發明的大綱，更重要的一些技術特徵將在後面的具體實施例中採用細節加以描述，以有助於本發明的技術可以被更好的理解。本發明的其他附加技術特徵會被在後面的具體實施例中加以詳述，並且其構成本發明的附加權利要求。
在解釋本發明的實施例之前，必須清楚的是參考以下附圖及實施例來詳述的本發明的具體應用並不對本發明構成限制，其僅僅是用於描繪。
因此，本領域的技術人員基於本發明所公開之內容可以設計處其他方法和系統來實現本發明的若干目的，然而根據本發明的權利要求，這些裝置、結構並未脫離本發明的精神範圍。
本發明以下將會參考附圖並以實施例的方式進一步闡述本發明。然而，所採用的附圖及實施例並不用於限制本發明的範圍。附圖中省略了本發明所採用的為本領域技術人員所熟知的元件，僅繪出為闡述本發明所必須的元件。此外，本發明包括圖中示出和未示出的組件。
本發明公開了一種立式晶片尺寸封裝，其向晶片兩側上突起的裝置連接點提供電連接。所述封裝以固定的配置電連接刷電路板。
第1A圖描述了本發明第一實施例的立式晶片尺寸封裝100，其電連接凹槽印刷電路板150(printed circuit board，PCB)。第1E圖描述了安裝在凹槽PCB150上的立式晶片尺寸封裝的俯視圖，第1A圖描述了沿第1E圖的A-A線的橫截面視圖。所述立式晶片尺寸封裝100包含一個晶片105，該晶片105包括一個功率垂直傳導半導體裝置，如MOSFET。
所述晶片105具有一個前表面115(第1B圖)和一個後表面117(第1C圖)。在前表面115上設置有一個柵極120和一個源極130。在後表面117上設置有一個漏極140。
通過如第9圖所示的製造過程900，在晶片100上形成柵極觸點120，源極觸點130，漏極觸點140，所述製造過程900包括步驟910，在該步驟中，在晶圓的前側形成鋁焊墊(Al)並在晶圓上形成一個鈦/鋁合金的背側金屬。在步驟920中，在晶圓背側形成一個鈍化層，在步驟930中，在所述鈍化層上形成至少一個視窗以暴露背側金屬。
在第一實施例中，形成有一個單一的視窗。在步驟940中，在晶圓的兩側化學鍍鎳/金(Ni/Au)以進一步提供凸點下金屬層(under bump metallization，UBM)作為焊接球的金屬觸點。在本發明中，除非另有說明，否則所述柵極、源極和漏極觸點包括所述UBM。同樣，為了簡單明瞭，鈍化層圖中未示出。
晶片尺寸固定封裝100有凸起的觸點用於焊接到印刷電路 板150上。在步驟950中，將所述焊接球固定在金屬觸點上，在步驟960中，將凸點晶圓切割成一組凸點晶片110。所述切割可以通過一個特殊的鋸子完成。如第1E圖所示，凸點柵極觸點120和凸點源極觸點130設置與所述凸點晶片110的前表面115上並被柵極焊接凸點165和源極焊接凸點170覆蓋。一個凸點漏極觸點140設置在所述凸點晶片110的後表面117上並被一個漏極焊接凸點175覆蓋。位於所述金屬觸點上方的焊接球的輪廓在第1B圖和第1C圖中以虛線示出。
參考第1D圖，所示的是印刷電路板150的俯視圖。線跡160a、160b和160c在表面151上形成，並分別包括獨立的圓形端163a、163b和163c。線跡160a和160b分別提供與柵極觸點120和與源極觸點130的電連接，同樣線跡160c提供與漏極觸點140的電連接。當凸點晶片110被佈置在沿印刷電路板的一部分形成的凹槽或缺口155中時，所述圓形端163a、163b和163c尺寸適配的分別鋪襯在焊接球165、170和175下。
所述凹槽155尺寸及形狀適配地接收凸點晶片110的一個側部111。所述凹槽155為凸點晶片110提供線性排列，從而使得焊接球165、170和175如第1A圖和第1E圖所示地分別相應覆蓋鋪在所述圓形端163a、163b和163c。此外，凹槽155將凸點晶片110保持在一個立式位置上，從而使得在焊接回流時該凸點晶片110的側部111被設置在凹槽155中。有利的是，非導電印刷電路板150盡可能減少在晶片110的漏極觸點140與柵極觸點120、源極接觸點130之間的短路。此外，當採用鐳射來切割凸點晶片110時，凸點晶片的側表面上可以形成二 氧化矽來提供進一步的短路保護。
第2E圖描述了安裝在凹槽PCB250上的立式晶片尺寸封裝200的俯視圖，第2A圖描述了沿第2E圖的A-A線的橫截面視圖。所述立式晶片尺寸封裝200包含一個晶片205，該晶片205包括一個功率垂直傳導半導體裝置，如MOSFET。本實施例與第1A圖-第1E圖的第一實施例相似，只是其源極和漏極具有多個金屬觸點而不是一個金屬觸點。
所述晶片205有一個前表面215(第2B圖)和一個後表面217(第2C圖)，在前表面215上設置有一個柵極觸點220、源極觸點230a和230b。漏極觸點240a和240b設置在所述後表面217上。隨後要被設置在上述觸點上的焊接球的輪廓用虛線示出。
如第9圖所示，在製造過程900中，在晶片205上設置柵極觸點220、源極觸點230a和230b、漏極觸點240a和240b。在本實施例中，在步驟930中，為源極和漏極設置二個視窗。在相應設置有焊接球265，270a和270b的晶片205的前表面215上形成凸點柵極觸點220、凸點源極觸點230a和230b，在相應設置有焊接球275a和275b的晶片205的後表面217上形成凸點漏極觸點240a和240b，從而形成一個凸點晶片210(如第2E圖所示)。
第2D圖是印刷電路板250的俯視圖。在表面251上形成線跡260a、260b、260c、260d和260e，其分別相應包括圓形端263a、263b、263c、263d和263e。線跡260a提供與柵極觸點220的電連接。線跡260b和260c分別提供與源極觸點230a 和230b的電連接。線跡260d和260e分別提供與漏極觸點240a和240b的電連接。當凸點晶片210被佈置在沿印刷電路板的一部分形成的凹槽或缺口255中時，所述圓形端263a、263b和263c、263d和263e尺寸適配的分別鋪襯在上述焊接球下。
所述凹槽255尺寸及形狀適配地接收凸點晶片210的一個側部211。所述凹槽255為凸點晶片210提供線性排列，從而使得焊接球265、270a和270b、275a和275b如第2A圖和第2E圖所示地分別相應覆蓋鋪在所述圓形端263a、263b和263c、263d和263e上。此外，凹槽255將凸點晶片210保持在一個立式位置上，從而使得在焊接回流時該凸點晶片210的側部211被設置在凹槽255中。有利的是，非導電印刷電路板250盡可能減少在晶片210的漏極觸點240a、240b與柵極觸點220、源極接觸點230a、230b之間的短路。
第3A圖-第3E圖描述了安裝本發明第三實施例的立式晶片尺寸封裝300，其電連接一個印刷電路板350。所述立式晶片尺寸封裝300包含一個晶片305，該晶片305包括一個功率垂直傳導半導體裝置，如MOSFET。
所述立式晶片尺寸封裝300在各方面都與第一實施例中的立式晶片尺寸封裝100相同，只是本實施中的立式晶片尺寸封裝300電連接一個不具有凹槽的印刷電路板350。因此，相較於晶片105的觸點，晶片305的觸點設置在鄰近晶片305的邊緣處。如第3B圖和第3C圖所示，在晶片305的一個前表面315上、鄰近晶片305的一個邊緣307的位置上形成一個柵極觸點320和一個源極觸點330。同樣的，在後表面317上、鄰 近邊緣304的位置上形成一個漏極觸點340。
如第3D圖所示的印刷電路板350具有與線跡160a、160b、160c(如第1D圖所示)相同的線跡360a、360b、360c。沒有凹槽並且所述凸點晶片310通過焊接回流在圓形端363a、363b、363c處電連接所述線跡360a、360b、360c。
如第3A圖-第3E圖所示，封裝300電連接印刷電路板350。
焊接球365、370和375被相應逐個焊接到金屬層320、330和340。焊接球365、370和375的焊接回流分別將柵極觸點320連接至線跡360a、將源極觸點330連接至線跡360b、將漏極觸點340連接至線跡360c。
第4A圖-第4D圖描述了本發明第四實施例的立式晶片尺寸封裝400，其電連接一個印刷電路板450。所述立式晶片尺寸封裝400包含一個晶片405，該晶片405包括一個功率垂直傳導半導體裝置，如MOSFET。
所述晶片405有一個前表面415(第4B圖)和一個後表面417(第4C圖)。在前表面415上、鄰近晶片405邊緣407處設置有一個柵極觸點420、一個源極觸點430。在所述後表面217上設置有一個漏極觸點440，其進一步包括一個厚焊接層。
如第9圖所示，在製造過程900中，在晶片405上設置柵極觸點420、源極觸點430、漏極觸點440。在晶片405的後表面417上設置一個厚焊接層475。在所述後表面417上不需要鈍化層。
第4D圖是印刷電路板450的俯視圖。在表面451上形成線跡460a、460b，其分別相應包括圓形端463a、463b。線跡 460a提供與柵極觸點420的電連接。線跡460b提供與源極觸點430的電連接。線跡460c的傳導杆490提供與漏極觸點440的電連接。當凸點晶片410被佈置在印刷電路板450上時，所述圓形端463a、463b尺寸適配的分別鋪襯在焊接球465、470下，所述印刷電路板450的凸點晶片410的後表面417上的焊接層475鄰接所述傳導杆490。
第5A圖-第5D圖描述了本發明第五實施例的立式晶片尺寸封裝500，其電連接一個凹槽印刷電路板550。所述立式晶片尺寸封裝500包含兩個晶片510和520，二者都進一步包括功率垂直傳導半導體裝置，如MOSFET。晶片510的尺寸大於或等於晶片520的尺寸，並且所述晶片510和晶片520相互連接共漏極配置。
晶片510具有一個前表面511(第5B圖)和一個後表面(圖中未示出)一個柵極觸點530和一個源極觸點535設置在所述前表面511上。一個漏極觸點(圖中未示出)包括一個鈦/鎳/銀背側金屬(Ti/Ni/Ag)。晶片520具有一個前表面521(第5B圖)和一個後表面(圖中未示出)一個柵極觸點540和一個源極觸點545設置在所述前表面521上。一個漏極觸點(圖中未示出)包括一個鈦/鎳/銀背側金屬(Ti/Ni/Ag)。
在如第10圖所示的製造過程1000中，晶片510和520的漏極觸點可以相互電連接。在步驟1010中，採用了兩個晶圓。第一晶圓包括一組晶片510，第二晶圓包括一組晶片520，所述兩個晶圓的後側包括晶片510和520的後表面並包括鈦/鎳/銀背側金屬(Ti/Ni/Ag)。在步驟1020中，所述兩個晶圓的前側都化 學鍍有鎳/金鍍層(Ni/Au)作為保護。在步驟1030中，測量晶片510的尺寸是否與晶片520的尺寸相等。如果尺寸相等，則兩個晶圓的佈局相互匹配，並在隨後的步驟1040中，兩個晶圓的背側焊接在一起。在步驟1040中，放置兩個晶圓的位置，以使得晶片510和晶片520一一相互匹配。如果晶片510比晶片520打，則在步驟1050中，將第二晶圓切割成若干晶片520，並在步驟1060中，以共漏極的結構將所述晶片520附在第一晶圓的晶片510上。為了實現該目的，匹配過程宜採用紅外照相機或鐳射。在步驟1040和1060中，可以使用導電環氧膠551。可選地，可採用回流溫度高於焊接球565、570、575和580的焊接。
在步驟1070中，焊接球位於兩個晶圓的前側，以提供與晶片510和520的柵極觸點、源極觸點的電連接。如第5A圖和第5E圖所示，焊接球565、570、575和580分別電連接並位於金屬觸點530、535、540和545下。最後，在步驟1080中，切割晶圓以形成凸點雙晶片共漏極晶片590。
凸點雙晶片共漏極晶片590電連接印刷電路板550。參考第5D圖，印刷電路板550具有線跡560a、560b、560c和560d，其分別相應包括圓形端563a、563b、563c和563d。線跡560a和560b分別提供與第一晶片510的柵極觸點530和源極觸點535的電連接。線跡560c和560d提供與第二晶片520的柵極觸點540和源極觸點545的電連接。當凸點雙晶片共漏極晶片590被佈置在沿印刷電路板550的一部分形成的凹槽或缺口555上時，所述圓形端563a、563b、563c和563d尺寸適配的分別 鋪襯在焊接球565、570、575和580下。
所述凹槽555尺寸及形狀適配地接收凸點晶片590的一個側部511。所述凹槽555為凸晶片590提供線性排列，從而使得焊接球565、570、575和580如第5A圖和第5E圖所示地分別相應覆蓋鋪在所述圓形端563a、563b、563c和563d上。此外，凹槽555將凸點晶片590保持在一個立式位置上，從而使得在焊接回流時該凸點晶片590的側部511被設置在凹槽555中。有利的是，非導電印刷電路板550盡可能減少在晶片590的柵極觸點與源極觸點之間的短路。此外，此外，如果採用鐳射來切割凸點晶片590，則凸點晶片的側表面上可以形成二氧化來提供進一步的短路保護。
根據本發明第六實施例，多個立式晶片可以安裝在一個PCB上。如第6圖所示，一個立式晶片尺寸封裝600包含一系列連接的三個MOSFET，其電連接至一個印刷電路板650上。第一MOSFET610包括一個柵極觸點，其通過焊接球615電連接線跡651a。第一MOSFET610的源極觸點通過焊接球617電連接線跡651e。第一MOSFET610的漏極觸點通過焊接球619電連接線跡651f。
第二MOSFET620包括一個柵極觸點，其通過焊接球621電連接線跡651b。第二MOSFET620的源極觸點通過焊接球619電連接線跡651f和第一MOSFET610的漏極。第二MOSFET620的漏極觸點通過焊接球623電連接線跡651g。
第三MOSFET630包括一個柵極觸點，其通過焊接球625電連接線跡651c。第三MOSFET630的源極觸點通過焊接球623 電連接線跡651g和第二MOSFET620的漏極。第三MOSFET630的漏極觸點通過焊接球627電連接線跡651d。
通過如前所述的製備過程900，形成第一、第二、第三MOSDET610、620、630的柵極、源極和漏極。印刷電路板650最好包括一組凹槽，其尺寸及形狀適配的接受MOS-FET610、620、630的側部，從而使得MOSFET610、620、630以立式位置設置在所述印刷電路板650上，該立式位置允許焊接連接具有清楚的視角並減少印刷電路板被佔用面積。
如第7圖所示，本發明的第七實施例中，立式晶片尺寸封裝700包括一個晶片705，其電連接一個印刷電路板750。該晶片705包括一個功率垂直傳導半導體裝置，如MOS-FET。
晶片705僅僅在其一側邊710處具有凸點，從而形成凸點晶片710。印刷電路板750上的凹槽755接收凸點晶片710。如前所述，凸點晶片710的觸點730通過焊接球770連接印刷電路板的線跡760。線跡760的圓形端763尺寸和形狀適配的鋪襯在焊接球770下。
流程圖第8A圖-第8F圖描述了一個表面安裝封裝800的形成過程。參考第8A圖，採用具有一組晶片區域815(僅示出其中一個)的一個假片(dummy wafer)或基底。通過在一組晶片區域815的角上蝕刻出空洞820，形成曲線接觸路由823a、823b、823c、823d(如第8B圖所示)。接下來，如第8C圖所示，在假片的所有表面上鍍上一層銅層825。假片沒有被切割成單獨的晶片區域815，因此晶片區域815的直邊沒有暴露，故沒有鍍上銅層825。然而，蝕刻的接觸路由823a-823d提供了晶片 815的頂部和底部之間的電連接。
假片和基底的頂部表面和底部表面隨後被蝕刻或更簡便地被機械半切穿。底部表面830上的銅層凹槽化，提供觸點如第8D-2圖所示的835a、835b、835c和835d。頂部表面840(第8D-1圖)被分割以提供頂部接觸點847a、847b、847c和847d，上述接觸點電分別相應通過蝕刻的接觸路由823a、823b、823c、823d連接底部接觸點835a、835b、835c和835d。頂部表面840同樣凹槽化，以提供凹槽845。這樣就形成了路由晶片850。在第8E圖中，一個凸點晶片860被安裝在凹槽845中的路由晶片850上，如前述實施例一樣。凸點晶片860採用焊接回流通過其焊接球電連接觸點847a、847b、847c和847d。
組成安裝在凸點晶片860上的路由晶片850的假片或基底的頂部採用成型化合物870封裝，並被切割形成如第8F圖所示的表面安裝封裝800，其中所述成型化合物具有一個適配的成型凹槽並。所述表面安裝封裝800可以表面安裝在一個具有線跡890的印刷電路板880上。
在另一個實施例中，第11圖描述了與本發明的立式晶片尺寸封裝連用的一個引線架1100。一個凸點晶片1110安裝在引線架1150的立式位置上，其焊接球1170電連接該引線架。該引線架被包裹在一個塑膠模型1190中。這種配置允許小型封裝，並減小電線焊接及減小與感應係數和電阻有關的電線。
在之前的實施例中，可以採用任意非傳導基底來替代印刷電路板，只要該基底具有適合安裝本發明的立式晶片尺寸封裝的特徵。所述特徵包括，用於連接立式晶片尺寸封裝的焊接球 的線跡，以及用於接收晶片的凹槽。
本發明的立式晶片尺寸封裝提供了在晶片兩側與裝置觸點的電連接、一個清楚地焊接視野和減小的印刷電路安裝面積。
上述實施例的具體應用可以通過多種方式實現，然而其仍未脫離本發明的範圍。例如，與晶片尺寸封裝的底部填充金屬上具有塗層相似，可以在印刷電路板的表面做塗層從而提供額外的保護以防止短路。進一步而言，某一實施例的一些方面可以包含部分專利內容，而不使用同一實施例的其他內容。此外，不同實施例的一些方面可以合併使用。本發明的範圍應該以其權利要求書所要求的內容加以確定。
100、200、300、400、500、600、700‧‧‧立式晶片尺寸封裝
105、205、305、405‧‧‧晶片
110、210、310、410、710、860、1110‧‧‧凸點晶片
111、211、511‧‧‧側部
115、215、315、415、511、521‧‧‧前表面
117、217、317、417‧‧‧後表面
120、220、320、420、530、540‧‧‧柵極觸點
130、230a、230b、330、430、535、545‧‧‧源極觸點
140、240a、240b、340、440‧‧‧漏極觸點
150、250、350、450、550、650、750、880‧‧‧印刷電路板
151、251、451‧‧‧表面
155、255、555、755、845‧‧‧凹槽
160a、160b、160c、260a、260b、260c、260d、260e、360a、360b、360c、460a、460b、460c、560a、560b、560c、560d、760、890‧‧‧線跡
163a、163b、163c、263a、263b、263c、263d、263e、363a、363b、363c、463a、463b、563a、563b、563c、563d、763‧‧‧圓形端
165、170、175、265、270a、270b、275a、275b、365、370、375、465、470、565、570、575、580、615、617、619、621、623、625、627、770、1170‧‧‧焊接球
407‧‧‧邊緣
475‧‧‧焊接層
490‧‧‧傳導杆
510、520、705‧‧‧晶片
551‧‧‧導電環氧膠
590‧‧‧凸點雙晶片共漏極晶片
610、620、630‧‧‧金屬氧化物半導體場效應電晶體
651a、651b、651c、651d、651f、651g、651e‧‧‧電連接線跡
730‧‧‧觸點
800‧‧‧表面安裝封裝
815‧‧‧晶片區域
820‧‧‧空洞
823a、823b、823c、823d‧‧‧接觸路由
825‧‧‧銅層
830‧‧‧底部表面
840‧‧‧頂部表面
847a、847b、847c、847d、835a、835b、835c、835d‧‧‧接觸點
850‧‧‧路由晶片
870‧‧‧化合物
900、1000‧‧‧製造過程
1100、1150‧‧‧引線架
1190‧‧‧塑膠模型
通過以下的實施例和相應的附圖對本發明的目的以及技術特徵進一步描述：第1A圖是沿第1E圖的A-A線的立式晶片尺寸封裝的橫截面結構示意圖，其描述了本發明第一實施例中的與凹槽印刷電路板相連的封裝結構。
第1B圖是本發明第一實施例的晶片的前表面的俯視結構示意圖。
第1C圖是本發明第一實施例的晶片的後表面的俯視結構示意圖。
第1D圖是本發明第一實施例的凹槽印刷電路板的俯視結構示意圖。
第1E圖是本發明第一實施例的與凹槽印刷電路板相連的立式晶片尺寸封裝的俯視結構示意圖。
第2A圖是沿第2E圖的A-A線的立式晶片尺寸封裝的橫截面結構示意圖，其描述了本發明第二實施例中的與凹槽印刷電路板相連的封裝結構。
第2B圖是本發明第二實施例的晶片的前表面的俯視結構示意圖。
第2C圖是本發明第二實施例的晶片的後表面的俯視結構示意圖。
第2D圖是本發明第二實施例的凹槽印刷電路板的俯視結構示意圖。
第2E圖是本發明第二實施例的與凹槽印刷電路板相連的 立式晶片尺寸封裝的俯視結構示意圖。
第3A圖是沿第3E圖的A-A線的立式晶片尺寸封裝的橫截面結構示意圖，其描述了本發明第三實施例中的與非凹槽印刷電路板相連的封裝結構。
第3B圖是本發明第三實施例的晶片的前表面的俯視結構示意圖。
第3C圖是本發明第三實施例的晶片的後表面的俯視結構示意圖。
第3D圖是本發明第三實施例的非凹槽印刷電路板的俯視結構示意圖。
第3E圖是本發明第三實施例的與非凹槽印刷電路板相連的立式晶片尺寸封裝的俯視結構示意圖。
第4A圖是沿第4E圖的A-A線的立式晶片尺寸封裝的橫截面結構示意圖，其描述了本發明第四實施例中的與印刷電路板相連的封裝結構。
第4B圖是本發明第四實施例的晶片的前表面的俯視結構示意圖。
第4C圖是本發明第四實施例的晶片的後表面的俯視結構示意圖。
第4D圖是本發明第四實施例的印刷電路板的俯視結構示意圖。
第4E圖是本發明第四實施例的與印刷電路板相連的立式晶片尺寸封裝的俯視結構示意圖。
第5A圖是沿第5E圖的A-A線的雙晶片共漏極立式晶片 尺寸封裝的橫截面結構示意圖，其描述了本發明第五實施例中的與印刷電路板相連的封裝結構。
第5B圖是本發明第五實施例的第一晶片的前表面的俯視結構示意圖。
第5C圖是本發明第五實施例的第二晶片的前表面的俯視結構示意圖。
第5D圖是本發明第五實施例的印刷電路板的俯視結構示意圖。
第5E圖是本發明第五實施例的與印刷電路板相連的雙晶片共漏極立式晶片尺寸封裝的俯視結構示意圖。
第6圖是本發明第六實施例的與印刷電路板相連的立式晶片尺寸封裝的俯視結構示意圖。
第7圖是立式晶片尺寸封裝的橫截面結構示意圖，其描述了本發明第七實施例中的與印刷電路板相連的封裝結構。
第8A圖一第8F圖描述了製造本發明的表面安裝式封裝的方法。
第9圖是本發明的立式晶片尺寸封裝的製備過程的流程圖。
第10圖是本發明的雙晶片共漏極立式晶片尺寸封裝的製備過程的流程圖。
第11圖是本發明的引線架封裝的橫截面示意圖。
100‧‧‧立式晶片尺寸封裝
105‧‧‧晶片
110‧‧‧凸點晶片
111‧‧‧側部
115‧‧‧前表面
117‧‧‧後表面
130‧‧‧源極觸點
140‧‧‧漏極觸點
150‧‧‧印刷電路板
155‧‧‧凹槽
160b、160c‧‧‧線跡
163b、163c‧‧‧圓形端
170、175‧‧‧焊接球

Claims (19)

  1. 一種立式晶片尺寸封裝，其特徵在於，包括一個晶片，其具有在其前側和後側上形成的觸點，在所述晶片安裝到立式構型上之前，所述每一觸點包括一個與其電連接的焊接球，從而形成一個凸點晶片；所述晶片安裝在一個立式構型上，故所述晶片的前側和後側實質上與安裝表面垂直；所述凸點晶片安裝在形成在一印刷電路板上的凹槽中，從而電連接晶片觸點並形成在所述印刷電路板上的一線跡，其中所述線跡的一圓形端的尺寸適配的鋪襯在所述焊接球下以及所述焊接球分別相應覆蓋鋪在所述圓形端上；所述凸點晶片安裝在作為立式構型的所述印刷電路板上凹槽中；從而使得晶片觸點採用焊接回流通過焊接球電連接所述線跡。
  2. 如申請專利範圍第1項所述的一種立式晶片尺寸封裝，其特徵在於，所述凸點晶片安裝在一個非傳導基底上，以電連接晶片觸點和形成在基底上的傳導線跡，凸點晶片安裝在立式構型上。
  3. 如申請專利範圍第2項所述的一種立式晶片尺寸封裝，其特徵在於，所述晶片是可安裝的，從而使得晶片的焊接球電連接晶片觸點和基底線跡，並且所述晶片觸點和基底線跡實質上相互垂直。
  4. 如申請專利範圍第1項所述的一種立式晶片尺寸封裝，其特徵在於，所述觸點包括一個鎳/金凸點下部金屬鍍層。
  5. 如申請專利範圍第1項所述的一種立式晶片尺寸封裝，其特徵在於，所述晶片是一個垂直傳導裝置。
  6. 如申請專利範圍第5項所述的一種立式晶片尺寸封裝，其特徵在於，所述晶片是一個功率MOSFET(金屬氧化物半導體場效應電晶體)；所述晶片的第一側包括一個柵極觸點和至少一個源極觸點；所述晶片的第二側包括至少一個漏極觸點。
  7. 一種立式晶片尺寸封裝，其特徵在於，包括一個晶片，其具有在其前側上形成的觸點，在所述晶片安裝到立式構型上之前，所述每一觸點包括一個與其電連接的焊接球，從而形成凸點晶片；所述晶片安裝在一個立式構型上，從而使得所述晶片的前側和後側實質上與安裝表面垂直；所述凸點晶片安裝在形成在一印刷電路板上的凹槽中，從而電連接晶片觸點且形成在所述印刷電路板上的一線跡，其中所述線跡的一圓形端的尺寸適配的鋪襯在所述焊接球下以及所述焊接球分別相應覆蓋鋪在所述圓形端上；所述凸點晶片安裝在作為立式構型的的所述印刷電路板上凹槽中；所述晶片後側進一步包括一後側觸點和一焊接層；所述晶片安裝在後側焊接層上，從而使得所述後側觸點電連接形成在安裝表面上的傳導杆。
  8. 如申請專利範圍第7項所述的一種立式晶片尺寸封裝，其特徵在於，所述安裝所述晶片使得其前側觸點通過焊接回流電連接安裝表面上的線跡。
  9. 如申請專利範圍第7項所述的一種立式晶片尺寸封裝，其特徵在於，所述晶片是一個MOSFET。
  10. 如申請專利範圍第7項所述的一種立式晶片尺寸封裝，其特 徵在於，所述前側觸點包括一個鎳/金凸點下部金屬鍍層。
  11. 一種立式晶片尺寸封裝，其特徵在於，包括一個第一晶片和一個第二晶片；所述晶片都是垂直傳導晶片並且上述晶片的後側相互連接從而使得二者的前側相反；所述每一晶片都進一步包括位於其前側的觸點；所述每一前側觸點都包括一個電連接其上的焊接球，從而形成一個凸點共後側晶片；所述凸點共後側晶片安裝在一個立式構型上，從而使得晶片的前側實質上與安裝表面垂直。
  12. 如申請專利範圍第11項所述的一種立式晶片尺寸封裝，其特徵在於，所述第一、第二晶片是垂直MOSFET，其具有位於前側的柵極觸點和源極觸點、位於後側的漏極觸點；所述凸點共後側晶片是一個凸點共漏極晶片。
  13. 如申請專利範圍第11項所述的一種立式晶片尺寸封裝，其特徵在於，所述凸點共後側晶片安裝在一個非傳導基底上以電連接器前側和基底上形成的線跡；所述凸點共後側晶片是一個凸點共漏極晶片安裝在一個立式構型上。
  14. 如申請專利範圍第11項所述的一種立式晶片尺寸封裝，其特徵在於，所述第一晶片比第二晶片大。
  15. 一種立式晶片尺寸封裝，其特徵在於，包括一個晶片，其具有在其前側和後側上形成的觸點，所述每一觸點包括一個與其電連接的焊接球，從而形成一個凸點晶片；所述晶片安裝在一個立式構型上，故所述晶片的前側和後側實質上與安裝表面垂直；以及進一步包括一個路由晶片，其上所述凸點晶片安裝在一個立式構型上，從而形成一個表面安裝封裝；所 述路由晶片提供凸點晶片與表面安裝封裝的底部之間的電連接。
  16. 一種立式晶片尺寸封裝，其特徵在於，包括一個晶片，其具有在其前側和後側上形成的觸點，在晶片安裝到立式構型上之前，所述每一觸點包括一個與其電連接的焊接球，從而形成一個凸點晶片；所述晶片安裝在一個立式構型上，故所述晶片的前側和後側實質上與安裝表面垂直；以及進一步包括一個引線架，在其上所述凸點晶片安裝在一個立式構型上，所述凸點晶片的觸點通過焊接球電連接引線架的引腳。
  17. 一種製造立式晶片尺寸封裝的方法，其特徵在於，包括以下步驟：提供一個前側具有觸點而後側具有背側金屬的晶圓；在所述晶圓後側形成鈍化層；在晶圓後側打開視窗以暴露背側金屬；在金屬襯墊和晶圓的兩側化學鍍鎳/金鍍層(Ni/Au)，以形成凸點下部金屬鍍層；在凸點下部金屬鍍層上設置焊接球；切割晶圓形成一組凸點晶片。
  18. 一種製造共漏極立式晶片尺寸封裝的方法，其特徵在於，包括以下步驟：提供前側具有鋁襯墊而後側具有背側金屬的兩個晶圓；化學鍍每一晶圓的前側並保護每一晶圓的後側，從而形成凸點下部金屬鍍層；測定兩個晶圓的晶片大小和佈局是否相互匹配；如相互匹配，則焊接晶圓後側；否則當第二晶圓的晶片比第一晶圓的晶片小時，切割第二晶圓；將從第二晶圓上切割的晶片附在第一晶圓的後側；在凸點下部金屬鍍層上設置焊接球；切割晶圓形成一組共漏極凸點晶片。
  19. 一種製造表面安裝立式晶片尺寸封裝的方法，其特徵在於， 包括以下步驟：提供一個假片基底，其具有一組晶片區域；蝕刻穿透位於每一晶片區域的角的孔洞；採用銅表面電鍍假片基底；凹槽化每一晶片區域的頂部表面，以形成一個凹槽和一組觸點；凹槽化每一晶片區域的底部表面，以形成一組觸點；底部表面的該組觸點中的每一個電連接相對應的頂部表面的那組觸點中的一個；在每一個晶片區域的頂部表面上安裝一組凸點晶片；成型封裝該組凸點晶片；切割假片基底，形成表面安裝立式晶片封裝。
TW098118886A 2008-06-30 2009-06-06 立式晶片尺寸封裝及其製造方法 TWI392038B (zh)

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CN101621043B (zh) 2013-08-07
TW201001579A (en) 2010-01-01
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