TWI390644B - 形成整合被動元件模組的半導體裝置和方法 - Google Patents

形成整合被動元件模組的半導體裝置和方法 Download PDF

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Publication number
TWI390644B
TWI390644B TW097139476A TW97139476A TWI390644B TW I390644 B TWI390644 B TW I390644B TW 097139476 A TW097139476 A TW 097139476A TW 97139476 A TW97139476 A TW 97139476A TW I390644 B TWI390644 B TW I390644B
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Taiwan
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layer
insulating layer
polymer film
substrate
insulating
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TW097139476A
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English (en)
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TW200929407A (en
Inventor
Yaojian Lin
Haijing Cao
Qing Zhang
Kang Chen
Jianmin Fang
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Stats Chippac Ltd
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Description

形成整合被動元件模組的半導體裝置和方法
本發明大體關於半導體裝置，且更特別地，關於一種具有整合被動裝置、表面配置裝置、及印刷電路板(PCB)構件之系統級封裝(SiP)的製造方法。
半導體或電腦晶片實際上係發現於今日所製造的每種電器產品中。晶片不僅僅是用於非常複雜的工業及商用電子設備中，也用於例如電視、洗衣機和乾衣機、收音機及電話類的家用品與消耗品中。隨著產品變得更小巧且更多功能，有需要包含更多晶片至較小型產品中以執行各種功能。行動電話尺寸上的縮小係如何將越來越多能力整合至越來越小的電子產品內的某一範例。
隨著電子產品變得越來越小，整合一些晶片至一單系統封裝內是渴望的。藉由整合原先獨立分開的晶片至一單封裝內，可大幅降低製造成本。雖然不錯，使用薄膜製程技術於具有其它晶片和封裝之晶圓上形成晶片的整合出現許多挑戰。例如，今日的薄膜製造製程於形成系統級封裝時需要使用昂貴、特殊的基板材料。印刷電路板雖可充當基板來使用，它們相當脆弱並可能於薄膜製程期間藉所使用的高溫損毀。同時，在今日SiP元件中，任何連接的IC晶片大體上限制為一2D配置架構。因此，可直接耦接至一基板的IC晶片數量大幅受到該基板的幾何限制。最後，若使用傳統科技將構件或額外裝置配置至基板背面，可能需 要使用基板穿孔(TSV)以電性連接所附構件至該基板內部電性結構。TSV生產困難且昂貴，所以它們的使用大幅地增加完成元件的成本。
需要存在一種形成具有整合薄膜裝置、表面黏著科技裝置及印刷電路板裝置之系統級封裝的方法。此外，需要存在該系統的製造技術如所述地減少製程步驟而產生較短週期時間和較低成本。
在某一實施例中，本發明是一種半導體裝置的製造方法，包括步驟為提供一基板，於該基板上部表面置放一絕緣層，形成一於該基板上部表面上之整合被動電路，移除該基板，沉積一於該絕緣層上之絕緣聚合物薄膜層及形成一於該絕緣聚合物薄膜層上之互連結構。
在另一實施例中，本發明是一種半導體裝置的製造方法，包括步驟為提供一基板，於該基板上部表面上置放一絕緣層，在該基板頂部表面上形成一整合被動電路，移除該基板及配置一於該絕緣層上之印刷電路板。該印刷電路板包含一絕緣聚合物薄膜層及一沉積於該絕緣聚合物薄膜層上之互連結構。
在另一實施例中，本發明是一種半導體裝置的製造方法，包括步驟為提供一基板，於該基板上部表面上置放一絕緣層，及藉由將一傳導層沉積於該基板上與將一介電層沉積於該基板上而形成一於該基板上之整合被動電路。該方法進一步包含形成一於該整合被動電路上之鈍化層，於 該鈍化層中蝕刻第一開口以露出該整合被動電路之第一表面，移除該基板，於該絕緣層中蝕刻第一開口以露出該整合被動電路之第二表面，沉積一於該絕緣層上之絕緣聚合物薄膜層及形成一於該絕緣聚合物薄膜層上之金屬層。該金屬層接觸該整合被動電路之第二表面。
在另一實施例中，本發明係一種半導體裝置的製造方法，包括步驟為提供一基板，於該基板上部表面上沉積一絕緣層，形成一於該基板上部表面上之整合被動電路，以覆晶或線接合技術將IC晶粒或分散構件表面配置至該整合被動電路之第一表面上，以介電模封材料對晶圓模封，移除該基板，沉積一於該絕緣層上之絕緣聚合物薄膜層及形成一於該絕緣聚合物薄膜層上之互連結構。
參考該圖示將本發明描述於下列說明之一或更多實施例中，其中，類似編號代表相同或類似構件。在以最佳模式說明本發明而得到發明目的時，那些熟知此項技術之人士會了解到它想要將可能落入由下列揭示及圖式所支持之所附申請專利範圍及它們等效例之本發明精神及範圍內之替代例、修改例及等效例涵蓋在內。
具有整合被動裝置、表面配置裝置及以PCB為基礎之裝置之系統級封裝可製造以減輕成本並減輕結合複數個裝置至一單封裝內之相關困難度。甚至，該系統可使用較少製程步驟及較便宜材料製造，其對較短週期時間及較低整體成本有所貢獻。
一配置的半導體裝置示於圖1。裝置10牽涉到面向下朝著一晶片載體基板或PCB 16配置晶粒14主動區12。根據晶粒14的電性設計，主動區12可包含主動及被動裝置、傳導層及介電層。晶粒14及基板或PCB 16間之電性及機械性互連可透過包括大量個別傳導焊接凸塊或球22之焊接凸塊結構20而得。於置放在晶粒14主動區12上之凸塊墊或互連處24上形成該焊接凸塊。藉由主動區12內所形成之傳導軌跡將凸塊墊24連接至晶粒14之主動電路。以回焊製程將焊接凸塊22電性及機械性連接至載體基板或PCB 16上之接觸墊或互連處26。該半導體裝置提供自晶粒14上之主動裝置至載體基板或PCB 16上之傳導軌跡之一短電性傳導路徑，以減少訊號傳導、降低電容並擁有整體較佳的電路性能。
轉向圖2a，顯示製造具有整合薄膜裝置、表面配置裝置及以PCB為基礎之裝置之系統級封裝之第一步驟。半導體晶圓28具有置放一絕緣層32於其上之基板30。基板30大體包含一虛擬晶圓或例如犧牲性矽(Si)晶圓或任何其它合適玻璃晶圓之基板材料。因此，基板30使用較傳統基板便宜的材料而能於製造時犧牲之。該絕緣層32係一選擇性層。當存在時，可使基板30和晶圓28之其它層電性隔離。絕緣層32也可充當一蝕刻停止層。如此，在移除基板30時，絕緣層32可用來偵測基板30之終點以防止基板30及絕緣層32上所形成構件之損毀。絕緣層32可包含任何合適材料且也可形成於多層內。例如，它可包含二氧化矽 (SiO2 )、氮化矽(Si3 N4 )層、氮氧化矽(SiON)或對於矽蝕刻劑具有良好選擇性之任何其它材料層。沉積絕緣層32可牽涉到物理氣相沉積(PVD)或化學氣相沉積(CVD)。
一傳導層34a－34g沉積並圖案化於絕緣層32上。傳導層34形成包含電容器(34b)、電阻器(34e和34f)及電感器(34g)之各種整合被動裝置之終端。在替代性實施例中，例如電晶體、二極體或其它消耗性及能量中性裝置之額外系統構件或被動裝置可形成。傳導層34可由鋁(Al)、鋁合金、銅(Cu)、鎳(Ni)、金(Au)、銀(Ag)、自我對準矽化物、多晶矽或適合用於在基板上沉積之其它電性傳導材料所製。一物理氣相沉積、化學氣相沉積、電解電鍍或無極電鍍製程可使用以形成傳導層34。
電阻層36形成於傳導層34及絕緣層32上。電阻層36可為任何合適材料，包含鎳鉻合金(NiCr)、金屬矽化物、氮化鉭及具有高電阻之多晶矽。電阻層36之沉積可牽涉PVD或CVD。
一介電層38圖案化並形成於電阻層36上。介電層38形成包含電容器、電阻器及電感器之各種被動電路構件以及支撐接觸墊34a和34h的部分。介電層38可為氮化矽(SiN)、氧化鉭(Ta2 O5 )、氧化給(HfO2 )或一介電薄膜材料。在某一替代性實施例中，電阻層36形成於介電層38上。
接著，鈍化層40沉積於絕緣層32、傳導層34、電阻層36及介電層38上。鈍化層40可圖案化以產生各種開口，藉以露出一或更多晶圓28之較下層。在第2a圖中，保護層 40圖案化並蝕刻以露出部分傳導層34及介電層38。鈍化層40可包含任何合適絕緣材料，例如聚醯亞胺、苯環丁烯(BCB)、PBO(聚苯噁唑)、環氧樹脂為主之絕緣聚合物或其它絕緣材料。鈍化層40，如所有進一步鈍化層，提供晶圓28各層間之物理性支撐及電性絕緣。
傳導層42沉積於鈍化層40上。傳導層42，如傳導層34，可包含任何合適材料並藉任何合適方法形成之。如圖2a所示，經由於鈍化層40形成之圖案優點，傳導層42接觸部分傳導層34及介電層38。在替代性實施例中，鈍化層40可蝕刻以使傳導層42也接觸到電阻層36。傳導層42充當一黏著層使用，有助於傳導層44沉積至晶圓28上。在某一替代性實施例中，一擴散障礙材料可沉積於傳導層42及傳導層44之間，以增強該二層間之物理性及/或電性連接。
傳導層44圖案化並形成於傳導層42上。傳導層44，類似傳導層34，可包含任何合適材料並藉任何合適製程形成之。例如，在某一實施例中，傳導層42包含鈦(Ti)而傳導層44包含銅。
最後，鈍化層46形成於傳導層44及所有較下層上，如圖2a所示。鈍化層46，如鈍化層40，可包含任何合適材料並藉任何合適方法形成之。鈍化層46提供結構支撐並可圖案化以露出之一或多個晶圓28之較下層。例如，在圖2a中，鈍化層46蝕刻以露出部分傳導層42及傳導層44。
視應用而定，該裝置可使用金屬、介電質、絕緣體及 鈍化層之各種結合來製造之。例如，一些應用可能需要在晶圓28上形成額外金屬及介電層或某些移除。同時，一或更多接地面可於製造製程期間形成於晶圓28上。類似地，用於該裝置之額外互連功能可藉由增加圖案化金屬互連層而得。
在替代性實施例中，可使用一金屬－絕緣體－金屬(MIM)架構將電容器形成於該裝置內。本例中，二單金屬層可形成於具有一置放於該二金屬層間之介電層之基板30上。額外電阻層也可形成於該二金屬層之間以改變該電容器特性。在某一範例中，電漿沉積之氮化矽、三氧化二鉭或陽極氧化鋁膜沉積於該金屬層間而可大幅增加該電容器電容值。
在圖2a中，該整合被動裝置包含一由傳導層44及42、介電層38、電阻層36和傳導層34b所形成之電容器。該整合被動裝置進一步包含由傳導層34e、電阻層36和傳導層34f所形成之電阻器。該整合被動裝置進一步包含由傳導層44、42和34g所形成之電感器。於晶圓28上形成之電感器為單層式或堆疊式螺旋電感器構件。大體上，堆疊式螺旋電感器提供每單位面積較高之電感值，但單層式螺旋電感器提供一較佳Q值。一螺旋電感器可形成於具有一絕緣層置於其間之至少二金屬層中。第一，一螺旋設計圖案化於該第一金屬層，且使用貫穿該絕緣層所形成之通孔將一螺旋內部電子性耦接至該第二金屬層。在這類電感器中，該金屬層可由例如銅、銀或金之高傳導性金屬所形成。一或 更多該整合被動裝置可根據該裝置之電性功能互連成一被動電路。
參考圖2b，黏著層50沉積於鈍化層46上。接著使用黏著層50將一暫時晶圓載體52配置至鈍化層46。暫時晶圓載體52可為玻璃、矽、陶磁、金屬、聚合物複合物或其它剛性材料。
圖2c顯示基板30之移除及絕緣層32之圖案化。利用一額外濕蝕刻步驟將基板30以機械背面研磨移除。替代性地，可使用電漿蝕刻及/或一化學機械平坦化(CMP)製程。在本實施例中，最初多數基板30是使用一背面研磨製程來移除，其留下約10-25微米的殘餘基板30。該殘餘基板30使用濕蝕刻、乾蝕刻或CMP製程移除。在移除基板30後，絕緣層32露出。
絕緣層32蝕刻以產生露出部分傳導層34a和34h的通孔。在某一實施例中，使用一雷射鑽孔技術，搭配下列製程中所形成之選擇性通孔來開口絕緣層32。
參考圖2d，絕緣聚合物薄膜54施加至在絕緣層32上之晶圓28的背面。可使用例如壓合、印刷、噴塗或旋塗之任何合適製程來施加聚合物薄膜54。施加後，聚合物薄膜54蝕刻以露出部分傳導層34a和34h。可使用光微影技術或一雷射鑽孔系統來蝕刻聚合物薄膜54。形成時，聚合物薄膜54可能超過0.5微米(μm)厚。然而，在一些應用中，聚合物薄膜54比50微米更厚。在本實施例中，聚合物薄膜54包含一具有例如大於1kΩcm電阻之高電阻率材料。聚合 物薄膜54可包含聚醯亞胺、BCB、PBO、環氧樹脂或水滲透率(WPR)－介電材料。聚醯亞胺材料大體具有一約3.3左右的介電常數及一約2.4X1015 Ωcm左右的電阻率。環氧樹脂大體具有一約4.4左右的介電常數及一約1.0X1015 Ωcm左右的電阻率。WPR－介電材料大體具有一約3.6左右的介電常數及一約1.0X1015 Ωcm左右的電阻率。
金屬層56沉積於聚合物薄膜54上。在本實施例中，金屬層56為銅且典型厚度超過15微米。然而，在替代性實施例中，金屬層56的厚度範圍可自約3至25微米，典型地為12微米。金屬層56可由任何合適金屬所形成，例如，金、銀、鋁、鋁合金、銅、錫或鎳。視應用而定，較佳地，金屬層56可佈線，用以避免直接由晶圓28內所形成之整合被動裝置之一或更多的下方經過。例如，參考至圖2d，金屬層56沉積，用以避免直接由該電感器下方經過，因金屬層56及流經金屬層56的信號會干擾該電感器或其它被動裝置操作。金屬層56可充當一接地面。
現在轉向圖2e，可以與形成聚合物薄膜54和金屬層56所使用之類似方式將額外金屬及絕緣聚合物薄膜層添加至該半導體裝置。該絕緣聚合物薄膜62沉積於聚合物薄膜54及金屬層56上。一金屬層64沉積於金屬層56及聚合物薄膜62上。金屬層64形成電感器及具有其它執行值之帶狀線。在那些層上，沉積絕緣聚合物薄膜66。金屬層68沉積於聚合物薄膜66上。金屬層56、64和68與絕緣層54和66之結合構成一互連結構，其電性連接金屬層34、42和 44以提供該半導體封裝內之整合被動裝置及其它半導體晶粒一完整的電性互連。
金屬層68可形成獨立接地面、電感器及/或傳輸線。該絕緣聚合物薄膜層可包含例如聚醯亞胺或環氧樹脂之單一聚合材料或具有一添加填充材料或纖維材料之聚合物合成物。對於多數應用而言，該聚合物薄膜層在曝露於高頻電磁輻射時應具有高電阻率及一低損失正切。對多數應用而言，1kΩcm電阻率及0.01損失正切會令人滿意。在某一實施例中，可使用由日立(Hitachi)公司所製造之第MSL－BE－67G(H)號基板材料。其在2GHz時具有一0.01損失正切及一1x1015 Ωcm電阻率。該額外聚合物薄膜層蝕刻以考慮到在該額外金屬層間互連性。
最後，焊接光罩72形成於金屬層68及聚合物薄膜66上。焊接光罩72圖案化以露出部分金屬層68。
視該最終應用而定，任意結合的額外金屬層及額外聚合物薄膜層可添加至該半導體裝置中。例如，在一些應用中，一單金屬層及聚合物薄膜層會足以提供晶圓28內形成之裝置及額外外部構件間所需之電性互連。然而，在一些實施例中，數個額外金屬及聚合物薄膜層添加至該半導體裝置以提供一PCB互連結構。在一些實施例中，該額外金屬層可形成例如互連電路、接地面及帶狀線之特定系統構件。
添加互連電路有助於耦接至晶圓28之系統構件及形成於該晶圓內或其上之系統構件間之電子通訊。視該系統應 用而定，該互連可以任何合適架構來形成。
一接地面可提供形成於晶圓28上之被動裝置一電性地面連接之金屬層。接地面也提供耦接至晶圓28之分散構件一選擇性接地。大體上，接地面減少該被動裝置間及該半導體裝置之被動裝置和其它構件間之噪音及串音。
傳輸線或帶狀線包含一金屬材料並充當一收發電磁輻射之傳輸線。因此，帶狀線有助於信號匹配、信號傳輸，並進一步確保該系統射頻信號之整合性。
大體上，帶狀天線包括形成於二平行接地面間之一金屬條。一介電材料置放於該接地面間並環繞著該金屬條。該金屬條的幾何特性、該金屬條及該接地面間的距離及該介電材料的相對介電係數決定該傳輸線特性阻抗。替代性地，帶狀線可為一微帶天線形式。在這類架構中，帶狀線包括一以介電材料與單一接平面分開之金屬條。
在一替代性實施例中，聚合物薄膜54及金屬層56如上所述地形成。然而，不同於直接在聚合物薄膜54及金屬層56上沉積額外金屬層及聚合物薄膜層，額外聚合物薄膜層及金屬層先使用一獨立的PCB製造製程形成。一旦形成，將結合的額外金屬層及聚合物薄膜層與聚合物薄膜54及金屬層56對準並接著結合至聚合物薄膜54及金屬層56。可使用例如上述那些製程中任一合適製程將內含額外金屬及聚合物薄膜層之預製PCB結合至聚合物薄膜54及金屬層56。替代性地，它們可藉由沉積一在該PCB上之均勻金屬層來結合，其中，該均勻金屬層接觸並結合至金屬層 56。例如，參考至圖2e，金屬層68均勻並以此方式連接至金屬層56。結合後，雷射鑽孔該額外金屬及聚合物薄膜層以形成提供對金屬層56存取開通通孔。
在進一步替代性實施例中，一獨立PCB可直接連接至絕緣層32。本例中，根據上述方法，可於該PCB中開通通孔以露出絕緣層32及傳導層34。一均勻金屬層接著可沉積於該PCB上以連接傳導層34並進一步連接該PCB至晶圓28。
在本實施例中，架構該額外PCB以避免將該額外金屬層直接佈線於晶圓28上所形成之被動裝置下方，因而避免例如電感器之被動構件之高頻損失。
轉向圖2f，顯示該半導體裝置製造之最後步驟。第一，以一熱或紫外線固化製程來移除暫時晶圓載體52及黏著層50並使用溶劑浸泡及/或電漿清潔來清潔之。一旦乾淨，分散構件或半導體晶粒可被耦接至傳導層44。可使用任何合適製程來耦接該構件。例如，參考第2f圖，構件80可為一分散被動裝置，構件84可被一數位積體電路(IC)，構件90可為一射頻IC，且構件96可為一表面聲波濾波器。使用凸塊82、86、92和98將這些構件連接至傳導層44。利用本方法，被動裝置、主動裝置、分散被動裝置、其它IC晶片或分散封裝中之任何結合可連接至晶圓28。
凸塊82、86、92和98在構件80、84、90和96以及傳導層44間形成一電性和機械性互連。施用回焊製程至沉積在傳導層44露出部分及構件80、84、90和96接觸墊上 之焊接材料來形成凸塊82、86、92和98。在替代性實施例中，凸塊82、86、92和98由金或銅結構或例如錫/鉛(Sn/Pb)、銅/鋅(CuZn)或銅/銀(CuAg)焊料之任何其它合適材料形成，每一種焊料內含一選擇性助熔劑材料。可透過任何合適互連結構將凸塊82、86、92和98電性連接至晶圓28內所形成任一被動裝置中。在一替代性實施例中，額外構件80、84、90和96在該額外金屬層及額外聚合物薄膜層前耦接至晶圓28。
可使用例如SMT及線接合之替代性製程將構件80、84、90和96耦接至傳導層44。選擇性底部填充88和94可沉積在構件80、84、90和96下以提供機械性支撐並充當構件80、84、90和96以及晶圓28之熱電橋。底部填充88和94可包含環氧化物、聚合材料、薄膜或其它非傳導材料。
利用所附構件80、84、90和96，該半導體裝置接著可使用一覆晶或線接合製程來連接至其它構件或系統。參考第2f圖，使用一合適製程將線接合墊及導線76連接至金屬層68以結合熱、壓力及/或超音波能量而在線接合墊和導線76以及金屬層68之間形成一機械性和電性接合。視應用而定，可透過一金屬互連網路將線接合墊和導線76電性連接至晶圓28上形成之被動裝置。該些線接合及線接合墊可藉由任何合適方法或傳導材料形成。也示於圖2f者連接至金屬層68之凸塊74。凸塊74被耦接至金屬層68以協助將該半導體裝置連接至例如PCB或記憶體電路之額外構件。凸 塊74可使用一球滴或孔版印刷製程形成。凸塊74也可藉由一金屬互連網路而被連接至晶圓28上所形成之被動裝置。凸塊74間之互連及被動裝置可視應用需求而以任何合適方式圖案化。
轉向圖3，使用一線接合製程將數位IC 100連接至傳導層44。因此，線102連接數位IC 100一表面上所形成之接觸墊至傳導層44。在替代性實施例中，可使用一線結合製程將任何合適構件耦接至傳導層44。在本實施例中，模封化合物或膠封104也置放於構件80、100、90和96以及鈍化層46上。可在構件80、100、90和96耦接至傳導層44之後沉積膠封104。在本實施例中，略過提供黏著層50及暫時晶圓載體52步驟。
轉向圖4，將凹槽110及112自絕緣層32中移除。凹槽110及112可視應用而具有任何合適外形。形成凹槽110及112後，在絕緣層32上形成聚合物薄膜54期間，聚合物薄膜54滲入凹槽110及112。藉由滲入凹槽110及112中，聚合物薄膜54最好是黏合至絕緣層32以提供一具有較佳物理整合性之系統。在本製程期間，可以模封化合物或膠封104置放於鈍化層46及構件80、84、90和96上來取代黏著層50及暫時晶圓載體52之形成而將黏著層50及暫時晶圓載體52之形成省略。
在進一步替代性實施例中，凹槽110及112可形成於絕緣層32及鈍化層40中，藉以使聚合物薄膜54接合兩層以進一步增加該連接之物理整合性。使用一蓄意過度蝕刻 於蝕刻絕緣層32時將該凹槽形成至鈍化層40中。以絕緣層32充當該蝕刻光罩以底切至鈍化層40內。該底切可達到一增強支撐效果。
在圖5中，選擇性底部填充88和94以及膠封104未施用於該半導體裝置製造期間。替代性地，模封化合物114施加於鈍化層46及構件80、84、90和96上。模封化合物114可藉由印刷或壓縮模封來施加。例如，模封化合物可為來自松下(Matsushita)公司之第X8710F3A號化學品、來自住友(Sumitomo)公司之第X80280S號化學品或來自日東(Nitto)公司之第GE－100LFCG號化學品或具有正確CTE、收縮率、介電常數、損失正切、電阻率及機械或熱強度之任何模封化合物材料。該絕緣層32蝕刻以提供凹槽110與112以增強聚合物薄膜54及絕緣層32間之物理連接，藉此提供該半導體裝置較大物理整合性。
在圖6中，在基板30移除前使用一合適SMT或覆晶製程將構件80、84、90和96耦接至傳導層44。該額外底部填充材料未於傳導層44及構件80、84、90和96間形成以提供額外機械性支撐。略過鈍化層46。替代性地，模封化合物116形成於構件80、84、90和96、傳導層44、傳導層42及鈍化層40上。本實施例中，用以結合模封化合物116來連接構件80、84、90和96至傳導層44之配置製程提供適當機械性支撐給該些構件。再次地，蝕刻絕緣層32以提供凹槽110和112以增強聚合物薄膜54及絕緣層32間之物理性連接，藉此提供更大的系統物理整合性。最後， 在本實施例中，鈍化層46未被施加以於薄膜製程期間充當一在晶圓28上之最終鈍化層。
轉向圖7，使用一黏著層118將一永久性支撐基板120或晶圓載體連接至模封化合物116。永久性支撐基板120可包含玻璃、矽、陶磁、金屬、聚合物複合物或其它剛性材料。
轉向圖8，使用黏著層122將一散熱器124架置配置於模封化合物114及內嵌式構件80、84、90和96上。散熱器124提供改善的散熱。散熱器124大體上包含一例如鍛造銅之金屬材料。
示於各種實施例中之半導體裝置可使用習知技術中所熟知之工具及設備來製造，例如，線接合、圖案化、蝕刻及相似設備。該半導體裝置適合延伸至先進科技以在低製造成本下整合一些構件並產生較高的整體可重複品質。
雖然本發明一或更多實施例已被詳加說明，熟知此項技術之人士會了解在不偏離下列申請專利範圍中所述之本發明範圍，那些可產生之實施例的修改及改寫。
10‧‧‧半導體裝置
12‧‧‧主動區
14‧‧‧晶粒
16‧‧‧印刷電路板
20‧‧‧焊接凸塊結構
22‧‧‧焊接凸塊
24‧‧‧凸塊墊/互連處
26、34a、34h‧‧‧接觸墊
28‧‧‧半導體晶圓
30‧‧‧基板
32‧‧‧絕緣層
34、42、44‧‧‧傳導層
34b‧‧‧電容器
34e、34f‧‧‧電阻器
34g‧‧‧電感器
36‧‧‧電阻層
38‧‧‧介電層
40、46‧‧‧鈍化層
50、118、122‧‧‧黏著層
52‧‧‧暫時晶圓載體
54、62、66‧‧‧聚合物薄膜
56、64、68‧‧‧金屬層
72‧‧‧焊接光罩
74、82、86、92、98‧‧‧凸塊
圖1說明一示範性半導體裝置。
圖2a-2f說明一形成系統級封裝之製程。
圖3說明一黏附分散構件之系統級封裝。
圖4說明一具有形成於該晶圓絕緣層內之凹槽之系統級封裝。
圖5說明一具有沉積於該鈍化層及該構件上之模封化 合物之系統級封裝。
圖6說明一不具有形成於該晶圓上之最終鈍化層之系統級封裝。
圖7說明一黏附有晶圓載體之系統級封裝。
圖8說明一具有黏附於該模封化合物上之散熱器之系統級封裝。
10‧‧‧半導體裝置
12‧‧‧主動區
14‧‧‧晶粒
16‧‧‧印刷電路板
20‧‧‧焊接凸塊結構
22‧‧‧焊接凸塊
24‧‧‧凸塊墊/互連處
26‧‧‧接觸墊

Claims (22)

  1. 一種半導體裝置的製造方法，包括：提供一第一暫時基板，於該基板上部表面上置放一絕緣層；形成一於該絕緣層的第一表面上之整合被動電路，其藉由：(a)形成一在該絕緣層的第一表面上之第一傳導層，(b)形成一在該第一傳導層上之介電層，(c)形成一在該絕緣層上之第二傳導層；安置一於該整合被動電路上之第二暫時基板；移除該第一暫時基板；沉積一於相對於該絕緣層的第一表面的該絕緣層的第二表面上之絕緣聚合物薄膜層；形成一於該絕緣聚合物薄膜層上之互連結構；及移除該第二暫時基板。
  2. 根據申請專利範圍第1項之方法，包含接合一永久性支撐基板至該半導體裝置。
  3. 根據申請專利範圍第1項之方法，包含電性連接一半導體晶粒至該整合被動電路。
  4. 根據申請專利範圍第1項之方法，包含：在該絕緣層中蝕刻一凹槽；及將一部分絕緣聚合物薄膜層沉積至該凹槽中。
  5. 根據申請專利範圍第1項之方法，其中移除該暫時基 板包含：使用一研磨製程來移除第一數量之暫時基板；及使用濕蝕刻、乾蝕刻或化學機械平坦化製程來移除第二數量之暫時基板。
  6. 一種半導體裝置的製造方法，包括：提供一暫時基板，於該暫時基板上部表面上置放一絕緣層；形成一於該絕緣層的第一表面上之整合被動電路，其藉由形成纏繞的一傳導層以建立於該絕緣層的第一表面上的感應特性；移除該暫時基板；及在相對該絕緣層的第一表面的該絕緣層的第二表面上配置一印刷電路板，其中，該印刷電路板包含：一絕緣聚合物薄膜層；及一形成於該絕緣聚合物薄膜層上之互連結構。
  7. 根據申請專利範圍第6項之方法，包含沉積一在該整合被動電路上之晶圓載體。
  8. 根據申請專利範圍第6項之方法，包含接合一永久性支撐基板至該半導體裝置。
  9. 根據申請專利範圍第6項之方法，包含電性連接一半導體晶粒至該整合被動電路。
  10. 根據申請專利範圍第6項之方法，包含：在該絕緣層中蝕刻一凹槽；及將一絕緣聚合物薄膜沉積至該凹槽中。
  11. 根據申請專利範圍第6項之方法，其中移除該暫時基板步驟包含：使用一研磨製程來移除第一數量之暫時基板；及使用濕蝕刻、乾蝕刻或化學機械平坦化製程來移除第二數量之暫時基板。
  12. 一種半導體裝置的製造方法，包括：提供一暫時基板，於該暫時基板上部表面上置放一絕緣層；形成一於該絕緣層的第一表面上之整合被動電路，藉由：將一傳導層沉積於該絕緣層的第一表面上，及將一介電層沉積於該絕緣層上；形成一於該整合被動電路上之鈍化層；於該鈍化層中蝕刻第一開口以露出該整合被動電路之第一表面；移除該暫時基板；於該鈍化層中蝕刻第一開口以露出該整合被動電路之第二表面；沉積一於相對該絕緣層的第一表面的該絕緣層的第二表面上之絕緣聚合物薄膜層；及形成一於該絕緣聚合物薄膜層上之傳導層，其中該傳導層接觸到該整合被動電路之第二表面。
  13. 根據申請專利範圍第12項之方法，包含電性連接一半導體晶粒至該整合被動電路中露出之第一表面。
  14. 根據申請專利範圍第13項之方法，包含將模封材料沉積於整合被動電路露出之第一表面及半導體晶粒上。
  15. 根據申請專利範圍第12項之方法，其中移除該暫時基板包含：使用一研磨製程來移除第一數量之暫時基板；及使用濕蝕刻、乾蝕刻或化學機械平坦化製程來移除第二數量之暫時基板。
  16. 根據申請專利範圍第12項之方法，包含形成一於該傳導層上之焊接光罩。
  17. 根據申請專利範圍第16項之方法，包含在該焊接光罩下形成一均勻傳導層，該均勻傳導層滲入該絕緣聚合物薄膜中。
  18. 根據申請專利範圍第12項之方法，包含：在該絕緣層中蝕刻一凹槽；及將一部分絕緣聚合物薄膜層沉積至該凹槽中。
  19. 一種半導體裝置的製造方法，包括：提供一暫時基板，於該暫時基板上部表面上沉積一絕緣層；形成一於該絕緣層的第一表面上之整合被動電路；移除該暫時基板；沉積一於相對該絕緣層的第一表面的該絕緣層的第二表面上之絕緣聚合物薄膜層；沉積一於該絕緣聚合物薄膜層上之互連結構；及接合一於該整合被動電路上方的晶圓載體。
  20. 根據申請專利範圍第19項之方法，包含接合一永久性支撐基板至該半導體裝置。
  21. 根據申請專利範圍第19項之方法，包含電性連接一半導體晶粒至該整合被動電路。
  22. 根據申請專利範圍第19項之方法，其中移除該暫時基板包含：使用一研磨製程來移除第一數量之暫時基板；及使用濕蝕刻、乾蝕刻或化學機械平坦化製程來移除第二數量之暫時基板。
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