TWI387105B - 降低切換轉換器中電壓耦合效應之功率元件 - Google Patents

降低切換轉換器中電壓耦合效應之功率元件 Download PDF

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TWI387105B
TWI387105B TW097143307A TW97143307A TWI387105B TW I387105 B TWI387105 B TW I387105B TW 097143307 A TW097143307 A TW 097143307A TW 97143307 A TW97143307 A TW 97143307A TW I387105 B TWI387105 B TW I387105B
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semiconductor device
power semiconductor
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TW201019471A (en
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Wei Chieh Lin
Ho Tai Chen
li cheng Lin
Jen Hao Yeh
Hsin Yen Chiu
Hsin Yu Hsu
Shih Chieh Hung
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Anpec Electronics Corp
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Description

降低切換轉換器中電壓耦合效應之功率元件
本發明係指一種功率半導體元件，尤指一種可改善切換時所產生之電壓突波及增進製程穩定性之功率半導體元件。
溝槽式功率電晶體是一種常見的傳統半導體元件，主要用於電源管理的部分，實際的例子如切換式電源供應器、電腦中心或周邊電源管理IC、背光板電源供應器以及馬達控制等等。溝槽式功率電晶體可提供快速的切換速度，然而，切換時伴隨而來的電壓突波效應，卻成為另一個必須克服的問題，而若要解決切換時之突波效應，通常可以藉由提高輸入電容(Input Capacitance)與反饋電容(Reverse Transfer Capacitance)之比值並且使該比值達到最佳化來抑制切換時之電壓突波。
為了抑制切換時之電壓突波，業界無不努力改善溝槽式功率電晶體的結構以最佳化輸入電容與與反饋電容之比值。常見的結構，如美國專利US7253473、US7037788、US6809349、US6806548所揭露之樣式，透過縮短溝槽深度，於溝槽表面向源極區形成閘極方式以提高輸入電容與反饋電容之比值來達到降低切換時之電 壓突波。然而，前述專利中並未揭露如何解決這些結構實現時將遭遇如佈植不均勻或PN接面異常導通等問題。
因此，本發明之主要目的即在於提供一種功率半導體元件。
本發明揭露一種功率半導體元件，包含有一背向金屬層、一基底層、一半導體層及一正向金屬層，該基底層，形成於該背向金屬層上；該半導體層，形成於該基底層上，該半導體層包含有一第一溝槽式結構、一第二溝槽式結構、一p型基體層、複數個n型源極區電極及一介電層，該第一溝槽式結構，包含有一第一閘極氧化層形成於一第一溝槽周圍，該第一溝槽中佈值有多晶矽；該第二溝槽式結構，包含有一第二閘極氧化層形成於一第二溝槽周圍，該第二溝槽中佈值有多晶矽；該p型基體層，形成於該第一溝槽式結構與該第二溝槽式結構之間；該複數個n型源極區電極，形成於該p型基體層上該第一溝槽式結構與該第二溝槽式結構之間；以及該介電層，形成於該第一溝槽式結構、該第二溝槽式結構及該複數個n型源極區上；以及該正向金屬層，形成於該半導體層上，且覆蓋該複數個n型源極區電極於該p型基體層上所形成之空隙。
請參考第1圖，第1圖為本發明實施例一溝槽式功率電晶體10的剖視圖。溝槽式功率電晶體10用以實現一功率半導體元件，其包含一背向金屬層101、一基底層102、一半導體層104及一正向金屬層106。半導體層104包含有一第一溝槽式結構201、一第二溝槽式結構202、一p型基體層204、n型源極區電極n_1~n_k及一介電層206。第一溝槽式結構201包含有一閘級氧化層208形成於一第一溝槽210周圍，而第一溝槽210內則佈有多晶矽。第二溝槽式結構202包含有一閘級氧化層212形成於一第二溝槽214周圍，而第二溝槽214內則佈有多晶矽。p型基體層204形成於第一溝槽式結構201與第二溝槽式202結構之間。n型源極區電極n_1~n_k，形成於p型基體層204上第一溝槽式結構201與第二溝槽式結構202之間。介電層206形成於第一溝槽式結構201、第二溝槽式結構202及n型源極區電極n_1~n_k上。正向金屬層106形成於半導體層上104，且覆蓋n型源極區電極n_1~n_k於p型基體層204上所形成之空隙。其中，n型源極區電極n_1~n_k於p型基體層204上所形成之每一空隙下方包含有一P+接觸區域。
在半導體層104中，第一溝槽式結構201及第二溝槽式結構202形成溝槽式功率電晶體10的閘極，n型源極區電極n_1~n_k形成溝槽式功率電晶體10的源極，而背向金屬層101則形成溝槽式功率電晶體10的汲極。較佳地，第一溝槽式結構201包含一頂端延伸區P，自第一溝槽210頂部向第一溝槽210兩側延伸，頂端 延伸區P佈值有多晶矽。此外，n型源極區電極n_1~n_k於p型基體層204上所形成之空隙與頂端延伸區P錯開而不重疊。在本發明實施例中，在溝槽式功率電晶體10之製程，主要係在形成基底層102及半導體層104後，於半導體層104上製作第一溝槽式結構201及第二溝槽式結構202，接著利用傾斜式離子佈植形成p型基體層204，以及利用傾斜式離子佈植形成n型源極區電極n_1~n_k，最後經蝕刻程序形成接觸洞，完成正向金屬層106及背向金屬層101。較佳地，正向金屬層106之材質可為鋁。
本發明實施例可改善利用傾斜式離子佈植形成p型基體層204與n型源極區電極時，因光罩之偏移或錯誤校準所造成佈植結果不均勻的問題。請參考第2圖至第7圖，第2圖至第7圖分別為本發明實施例溝槽式功率電晶體10之各佈局階段的上視示意圖及對應之立體結構剖視圖。較佳地，第一溝槽式結構201包含複數個頂端延伸區P，其佈值有多晶矽，分別自第一溝槽210頂部向第一溝槽210兩側延伸。舉例來說，如第2(a)圖及第2(b)圖所示，第一溝槽式結構201包含頂端延伸區P_1~P_3，其係沿一第一方向200間隔地形成於第一溝槽210頂部，並自第一溝槽210頂部向第一溝槽210兩側延伸，且頂端延伸區P_1~P_3佈值有多晶矽。此外，頂端延伸區P_1~P_3的排列方式可有許多不同變化。例如，在第2(a)圖及第2(b)圖中，頂端延伸區P_1~P_3係對稱地形成於第一溝槽210頂部；在第3(a)圖及第3(b)圖中，頂端延伸區P_1~P_3係非對稱地形成於第一溝槽210頂部。另一方面，正向 金屬層106之材質較佳地可為鎢金屬，相較於前述材質為鋁之正向金屬層106，會有兩次的離子佈植分別是表面較重之二氟化硼的植入以形成歐姆接觸，以及較輕的硼離子佈植使得橫向擴散深度加深及吸收電流能力增加，且於n型源極區電極下方形成P+接觸區，以避免崩潰情形發生。因此，當正向金屬層106之材質使用鎢金屬時，n型源極區電極於p型基體層204上所形成之空隙的形狀或排列方式亦可有許多不同變化，例如，在第4(a)圖及第4(b)圖中，n型源極區電極於p型基體層204上所形成之空隙係長條狀排列；以及在第5(a)圖及第5(b)圖中，n型源極區電極於p型基體層204上所形成之空隙係呈一棋盤狀。上述各種變化實施例(第2(a)圖至第5(b)圖)可適當組合，以實現不同實施例。例如，若n型源極區電極於p型基體層204上所形成之空隙係呈棋盤狀，則如第6(a)圖及第6(b)圖所示，頂端延伸區P_1~P_3可沿第一方向200間隔且對稱地形成於第一溝槽210頂部；或者，如第7(a)圖及第7(b)圖所示，頂端延伸區P_1~P_3可沿第一方向200間隔且非對稱地形成於第一溝槽210頂部。因此，本發明透過改變溝槽式功率電晶體10之結構比例及佈局方式，而能有效改善米勒效應以達抑制切換時之突波效應，且可避免佈植結果不均勻而能輕易控制製程穩定性以及降低PN接面異常的導通情況。
值得注意的是，第2(a)、2(b)至7(a)、7(b)圖之溝槽式功率電晶體10之佈局係為本發明之實施例，本領域具通常知識者當可據以做不同之變化及修飾。舉例來說，在第2(a)、2(b)至7(a)、7(b)圖 中，頂端延伸區P僅包含有頂端延伸區P_1~P_3，實際上，相同架構亦可衍生為多個頂端延伸區；當然，在此情況下，如頂端延伸區P或n型源極區電極n_1~n_k於p型基體層204上所形成之空隙之形狀、位置之變化亦同前所述，本領域具通常知識者當可做適當之變化，在此不贅述。同樣地，第二溝槽式結構202之佈局方式亦同於第一溝槽式結構201。除此之外，本發明實施例中溝槽式結構之頂端延伸區P係以正方形或長方形為例說明，請注意，本發明實施例中所述之形狀僅用於舉例說明，並非本發明之限制條件。
綜上所述，透過本發明之佈局結構，溝槽式功率電晶體10之結構比例及佈局能有效改善米勒效應以達降低切換時之突波效應及降低PN接面異常的導通情況，且更重要的是，可避免佈植結果不均勻而能提升製程穩定性。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
10‧‧‧溝槽式功率電晶體
101‧‧‧背向金屬層
102‧‧‧基底層
104‧‧‧半導體層
106‧‧‧正向金屬層
200‧‧‧第一方向
201‧‧‧第一溝槽式結構
202‧‧‧第二溝槽式結構
204‧‧‧p型基體層204
n_1~n_k‧‧‧n型源極區電極
206‧‧‧介電層
208、212‧‧‧閘級氧化層
210、214‧‧‧第一溝槽
P、P_1~P_3‧‧‧頂端延伸區
第1圖為本發明實施例一溝槽式功率電晶體的剖視圖。
第2(a)圖為本發明實施例一溝槽式功率電晶體之佈局上視示意圖。
第2(b)圖為第2(a)圖中之溝槽式功率電晶體之立體結構剖視圖。
第3(a)圖為本發明實施例另一溝槽式功率電晶體之佈局上視示意圖。
第3(b)圖為第3(a)圖中之溝槽式功率電晶體之立體結構剖視圖。
第4(a)圖為本發明實施例另一溝槽式功率電晶體之佈局上視示意圖。
第4(b)圖為第4(a)圖中之溝槽式功率電晶體之立體結構剖視圖。
第5(a)圖為本發明實施例另一溝槽式功率電晶體之佈局上視示意圖。
第5(b)圖為第5(a)圖中之溝槽式功率電晶體之立體結構剖視圖。
第6(a)圖為本發明實施例另一溝槽式功率電晶體之佈局上視示意圖。
第6(b)圖為第6(a)圖中之溝槽式功率電晶體之立體結構剖視圖。
第7(a)圖為本發明實施例另一溝槽式功率電晶體之佈局上視示意圖。
第7(b)圖為第7(a)圖中之溝槽式功率電晶體之立體結構剖視圖。
200‧‧‧第一方向
201‧‧‧第一溝槽式結構
202‧‧‧第二溝槽式結構
n_1~n_k‧‧‧n型源極區電極
210‧‧‧第一溝槽
214‧‧‧第二溝槽
P_1~P_3‧‧‧頂端延伸區

Claims (12)

  1. 一種功率半導體元件，包含有：一背向金屬層；一基底層，形成於該背向金屬層上；一半導體層，形成於該基底層上，該半導體層包含有：一第一溝槽式結構，包含有一第一閘極氧化層形成於一第一溝槽周圍，以及一頂端延伸區，該頂端延伸區自該第一溝槽頂部向該第一溝槽兩側延伸，其中該第一溝槽與該頂端延伸區中佈值有多晶矽；一第二溝槽式結構，包含有一第二閘極氧化層形成於一第二溝槽周圍，該第二溝槽中佈值有多晶矽；一p型基體層，形成於該第一溝槽式結構與該第二溝槽式結構之間；複數個n型源極區電極，形成於該p型基體層上該第一溝槽式結構與該第二溝槽式結構之間；以及一介電層，形成於該第一溝槽式結構、該第二溝槽式結構及該複數個n型源極區上；以及一正向金屬層，形成於該半導體層上，且覆蓋該複數個n型源極區電極於該p型基體層上所形成之空隙。
  2. 如請求項1所述之功率半導體元件，其中該複數個n型源極區電極於該p型基體層上所形成之空隙與該頂端延伸區錯開 而不重疊。
  3. 如請求項1所述之功率半導體元件，其中該第一溝槽式結構另包含複數個頂端延伸區，分別自該第一溝槽頂部向該第一溝槽兩側延伸，該複數個頂端延伸區佈值有多晶矽。
  4. 如請求項3所述之功率半導體元件，其中該複數個頂端延伸區沿一第一方向間隔地形成於該第一溝槽頂部。
  5. 如請求項3所述之功率半導體元件，其中該複數個頂端延伸區係對稱地形成於該第一溝槽頂部。
  6. 如請求項3所述之功率半導體元件，其中該複數個頂端延伸區係非對稱地形成於該第一溝槽頂部。
  7. 如請求項3所述之功率半導體元件，其中該複數個頂端延伸區之形狀相同。
  8. 如請求項3所述之功率半導體元件，其中該複數個頂端延伸區之形狀相異。
  9. 如請求項3所述之功率半導體元件，其中該複數個n型源極區電極於該p型基體層上所形成之空隙與該複數個頂端延伸區錯開而不重疊。
  10. 如請求項1所述之功率半導體元件，其中該複數個n型源極區電極於該p型基體層上所形成之空隙係呈一棋盤狀。
  11. 如請求項1所述之功率半導體元件，其中該複數個n型源極區電極於該p型基體層上所形成之空隙係呈長條狀。
  12. 如請求項1所述之功率半導體元件，其中該複數個n型源極區電極於該p型基體層上所形成之每一空隙下方包含有一P+接觸區域。
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