TWI375327B - - Google Patents
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- Publication number
- TWI375327B TWI375327B TW094136596A TW94136596A TWI375327B TW I375327 B TWI375327 B TW I375327B TW 094136596 A TW094136596 A TW 094136596A TW 94136596 A TW94136596 A TW 94136596A TW I375327 B TWI375327 B TW I375327B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- semiconductor device
- stress
- region
- conductive
- Prior art date
Links
- 229910052751 metal Inorganic materials 0.000 claims description 44
- 239000002184 metal Substances 0.000 claims description 44
- 239000004065 semiconductor Substances 0.000 claims description 36
- 239000000758 substrate Substances 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 20
- 238000004519 manufacturing process Methods 0.000 claims description 17
- 229910052732 germanium Inorganic materials 0.000 claims description 15
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 15
- 230000008569 process Effects 0.000 claims description 15
- 230000008859 change Effects 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 11
- 230000004888 barrier function Effects 0.000 claims description 9
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 claims 2
- 229910052744 lithium Inorganic materials 0.000 claims 2
- 239000010410 layer Substances 0.000 description 54
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 18
- 229910052721 tungsten Inorganic materials 0.000 description 17
- 239000010937 tungsten Substances 0.000 description 17
- 230000015572 biosynthetic process Effects 0.000 description 14
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052707 ruthenium Inorganic materials 0.000 description 2
- VLJQDHDVZJXNQL-UHFFFAOYSA-N 4-methyl-n-(oxomethylidene)benzenesulfonamide Chemical compound CC1=CC=C(S(=O)(=O)N=C=O)C=C1 VLJQDHDVZJXNQL-UHFFFAOYSA-N 0.000 description 1
- IOVCWXUNBOPUCH-UHFFFAOYSA-M Nitrite anion Chemical compound [O-]N=O IOVCWXUNBOPUCH-UHFFFAOYSA-M 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910021340 platinum monosilicide Inorganic materials 0.000 description 1
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 1
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7845—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being a conductive material, e.g. silicided S/D or Gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Materials Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Description
根據本發明之一能梅主 心樣’ +導體装置,具備: 絕緣層’其形成於矽基板上; 第1導電層’其係形成於上述絕緣層上;及 第2導電層,其係形成於第1導電層上包含金屬者, 上述第2導電層’具有植人雜質形成而具有與其他區域 相異應力之應力變化區域。 根據本發明之一態樣,半導體裝置之製造方法, 係於矽基板上經由絕緣層形成包含金屬之導電層, 於上述導電層之—部分,植人雜質,形成具有植入雜質 形成而具有與其他區域相異應力之應力變化區域。 根據本發明之一態樣,半導體裝置之製造方法, 係於矽基板上形成絕緣層, 於上述絕緣層上形成第1導電層, 於上述第1導電層上形成包含金屬之第2導電層, 上述第2導電層,具有植入雜質形成而具有與其他區域 相異應力之應力變化區域。 【實施方式】 以下,參照圖面’說明本發明之一實施形態。 (第1實施形態) 圖1係表示關於本發明之第1實施形態之半導體裝置之剖 面構造之剖面圖。圖1之半導體裝置,具備於矽基板1上鄰 接形成之PMOS電晶體2及NMOS電晶體3。任一電晶體均 具有形成於矽基板1之閘絕緣膜4,及形成於該閘絕緣膜4 上之閘電極5a、5b。閘電極5a、5b係例如以鎢(W)形成。 105662.doc 1375327 有拉張應力(tensile stress)之鎢(W^12(圖2)。膜厚為例如 約 10 0 n m。 其次,以抗蝕劑1 3等,遮蓋維持拉張應力之區域(圖 3)。例如,將PMOS電晶體2之形成區域覆蓋抗蝕劑13,使 NMOS電晶體3之形成區域之鎢膜露出。然後,對鎢膜12 植入钟(As)或侧(B)等雜質離子。植入雜質之鶴膜丨2a,拉 張應力被釋放而變化成應力可以忽視之大小或具有壓縮應 力(compressive stress)之區域(圖 4) 其认’使用圖案化及RIE荨異向性蚀刻,加工鶴膜12、 12a形成閘電極5a、5b(圖1)。閘電極5a、5b之寬可按照需 要決疋由約10 nm之細微圖案至約1 〇 μι^之寬的圖案。 與由具有拉張應力之鎢膜12構成之PMOS電晶體2之間電 極5a相對配置之通道表面具有壓縮應力,與由具有壓縮應 力之鎢膜12a構成之NMOS電晶體3之閘電極5b相對配置之 通道表面具有拉張應力。 形成圖1之構造’則以習知方法’進行延伸擴散層之形 成、閘電極5a、5b之側壁之形成、源/汲擴散層之形成 等。其後’於基板全面形成層間膜之後,以接觸製程形成 佈線層,完成電晶體》 如此’於第1實施形態’由於使PMOS電晶體2之閘電極 5a’與NMOS電晶體3之閘電極5b具有互相相異之應力,故 PMOS電晶體2之通道表面,與NMOS電晶體3之通道表面 之應力亦互相相反。因此,兩電晶體均可藉由應力提升遷 移度’可增大電晶體之驅動電流。 105662.doc 1375327 (第2實施形態) 上述之第1實施形態’由於閘電極係僅以鎢膜形成之單 層構造,故電晶體之限值電壓等電壓特性,會依存鶴膜之 性質。詳言之,限值等電氣特性,依存於接觸閘絕緣膜4 之金屬之攻函數。於此,於第2實施形態,使閘電極為層 . 疊構造’個別設置決定電氣特性之金屬,及決定應力之金 _ 屬層。 鲁圊5係表示關於本發明.之第2實施形態之半導體裝置之剖 面構造之刳面圖。圖5之半導體裝置’閘電極氕、5d之構 造與圖1之半導體裝置之閘電極53、5b相異。圖5之閘電極 5c、5d為2層構造,具有於閘絕緣膜4上形成之第1金屬層 21 ’及形成於第1金屬層21上之第2金屬層22 a、22b。 第1金屬層2 1係接觸閘絕緣膜4,決定電晶體之電氣特 性。第1金屬層2 1以例如氮化鈦(TiN)形成,該膜之厚度為 約5 nm。第2金屬層22a、22b係決定通道表面之應力者, φ 與第1實施形態同樣地以鎢形成,其厚度為約1 〇〇 nm。 圖6〜圖9係表示’表示圖5之半導體裝置之製造工序之一 例之剖面圖。以下,使用該等圖,說明圖5之半導體裝置 製造工序之順序。首先,於矽基板!上形成絕緣膜4後,例 如形成ΤιΝ23約5 nm(圖6),於其上面例如沉積鎢(w)】2約 I 00 nm(圖 7)。 其後之工序幾乎與第丨實施形態相同。簡單地說明,將 PMOS電晶體2之形成區域以抗蝕劑13遮蓋,於]^]^〇5電晶 體3之形成區域植入砷(As)或硼(B)離子,將nm〇s電晶體3 I05662.doc 之形成區域之鎢膜12之拉張應力釋放’使之具有壓縮應力 (圖 8) 〇 其後,剝離抗蝕劑13(圖9),加工鎢膜12形成閘電極5c、 5d(圖 5)。 如上所述,使第1金屬21為TiN時,電晶體2、3之電氣特 性係以TiN之特性決定。具體而言,閘電極5c、5d之功函 數依存於TiN之功函數,無論第2金屬層22a、22b之材料為 何,不會影響電晶體2、3之限值等電氣特性。因此,可個 別地控制電晶體2、3之電氣特性及通道表面之應力。 於上述說明’於決定電晶體2、3之電氣特性之第1金屬 層21上面,配置決定通道表面應力之第2金屬層22a、 22b’惟第1金屬21與第2金屬22a、22b會互相反應之情 形,於第1金屬21與第2金屬22 a、22b之間介插反應防止膜 為佳。 於第2實施形態之情形’亦於得到圖5之剖面構造後,以 習知手法,進行延伸擴散層之形成、閘電極义、5d之側壁 之升> 成、源/沒擴散層之形成等。其後,於基板全面形成 層間膜之後’以接觸製程形成佈線層,完成電晶體。 再者,第1金屬層21,亦可於NMOS電晶體3與PMOS電 晶體2互相使用個別的金屬,採用所謂雙金屬電極。具體 而言,例如,PMOS電晶體2之第1金屬層使用PtSi,NM〇s 電晶體3之第1金屬層21使用TiC。又,閘電極5C、5d,亦 可以3層以上之層疊膜形成。或者,pM〇s電晶體2與 NMOS電晶體3之中之一方以層疊構造,而另依方為單層構 J05662.doc -10- 1375327 造亦可。 圖10係表示使PMOS電晶體2之閘電極九為單層構造, NMOS電晶體3之閘電極5d為2層構造之半導體裝置之一例 之剖面圖。於圖10,NMOS電晶體3之閘極5d,係與圖5之 問電極5d同樣地,具有於閘絕緣膜4上形成之第!金屬層 21,及形成於第1金屬層21上之第2金屬層22b。 如此於第2實施形態’由於係以決定電晶體2、3之電氣 特性之第1金屬層,與決定電晶體2、3之通道表面應力之 第2金屬層22a、22b形成閘電極5c、5d,故可互相獨立地 控制電晶體之電氣特性及通道表面應力,可形成電氣特性 佳且遷移率高的電晶體。 (第3實施形態) 第3實施形態係使用鑲嵌製程製造半導體裝置者。 圖11表示關於本發明之第3實施形態之半導體裝置之剖 面構造之剖面圖。圖11之半導體裝置,具備以鑲嵌製程製 造之PMOS電晶體2及NMOS電晶體3 » PMOS電晶體2之閘電極5a與NMOS電晶體3之閘電極5b 係分別於形成在基板上之閘溝之周圍,使用例如鎢形 成。PMOS電晶體2之閘電極5a具有拉張應力,而NMOS電 晶體3之閘電極5 b具有壓縮應力》 圖12〜圖16係表示,表示圖η之半導體裝置之製造工序 之一例之剖面圖。以下,使用該等圖,說明圖丨丨之半導體 裝置製造工序之順序。首先,與第1實施形態同樣地,於 矽基板1上形成元件區域及元件隔離區域(STI) 11後,於全 105662.doc 1375327 面t成作為緩衝膜之氧化石夕膜。 ^ ’料假性㈣,於基板全面形成多以及氮化石夕 、/、人,使用抗蝕劑進行異方性蝕刻’形成假性閘電 、 -人’以習知手法’形成延伸擴散層區域後,於閘電 b周圍形成側壁24。其次’植入形成源/汲擴散層 =雜質。然後,藉由進行雜質離子之活化,形成源/汲區 ::5:按照需要,於源/汲區域25形成金屬矽化膜。
二人於基板全面沉積例如氧化矽膜後,以CMP法或回 餘法H⑽之氧切膜使其平坦化,使假性間膜之上 面露出。 …其次,㈣氮化石夕膜及氧化石夕膜,以稀氟酸系溶液去除 緩衝氧化膜露出矽基板丨,藉此形成用以形成閘電極&、 5 b之閘溝2 6 (圖12 )。 ”人於包3閘溝2 6之内部之基板上面以抗餘劑掩膜等 形成閘極絕緣膜4(圖丨3)。例如,可將係基板〗氧化,亦可 於基板全面沉積高介電體膜。 其次’於閘絕緣膜4之上面’形成成為閘電極5a、讣之 金屬層(例如’具有拉張應力之鎢)12(圖丨4)。其次,將基 板上面以CMP等平坦化,去除閘溝26外之鎢及閘絕緣膜 4(圖 15)。 其次,與第1實施形態同樣地,將使之具有拉張應力之 區域(PMOS電晶體2之形成區域)以抗蝕劑η遮蓋,於 NMOS電晶體3之形成區域植入砷(as)或硼(B)等雜質離子 (圖16)。藉此’ NMOS電晶體3之形成區域,拉張應力被釋 105662.doc 12 1375327 放,應力成可忽視之大小或具有壓縮應力(圖11)。 於圖11〜圖16,說明了形成單層構造之閘電極5a、5b之 例,惟亦可與第2實施形態同樣地形成層疊構造之閘電極 5c、5d。又,閘電極5a、5b,亦可如圖π所示形成為T字 型之閘電極5a、5b。圖17之閘電極5a' 5b,係於圖14之工 . 序後,藉由圖案化及RIE加工鎢膜12而形成。 此後’與通常的電晶體同樣地,依序形成層間膜與接 觸。 如此,於第3實施形態’於藉由鑲嵌製程形成pm〇s電晶 體2及NMOS電晶體3時’亦可使兩電晶體之閘電極5a、5b 之應力互相相反,不依電晶體之種類,可提升遷移率。 (第4實施形態) 第4實施形態’係使閘電極5a、5b為層疊構造,對應力 有影響之金屬形成於閘電極5a、5b之上層者。 圖18係表示關於本發明之第4實施形態之半導體裝置之 φ 剖面構造之剖面圖。圖18之導體裝置,具備PMOS電晶體2 ‘ 與NM〇S電晶體3,兩電晶體均具有以3層構造構成之閘電 極5e、5f。閘電極5e、5f,具有:多晶矽層21,其係形成 於閘絕緣膜4上;阻障層27,其係形成於多晶矽層21上; 及鶴膜28a、28b’其係形成於阻障層27上。 相對於PMOS電晶體2之閘電極“之材料之鎢膜具有拉張 應力’ NMQS電晶體3之閘f㈣之材料之鶴膜具有壓縮應 力。 以下,簡單說明圖18之半導體裝置之製造工序。於矽基 105662.doc -13- 1375327 圖3係接續圖2之工序剖面圖。 圖4係接續圖3之工序剖面圖。 圖5係表示關於本發明之第2實施形態 面構造之剖面圖。 裝置之剖 圖6係表不於圖5之半導體裝置之製造工序之 圖。 斤之一例之剖面 圖7係接續圖6之工序剖面圖。 圖8係接續圖7之工序剖面圖。 圖9係接續圖8之工序剖面圖。 圖1 0係表示PMOS電晶體2之閘電極5c為單岸^ NMOS電晶體3之閘電極5(1為2層構造之半導體裝構&, 之剖面圖。 、之一例 圖11係表示關於本發明之第3實施形態之半導體裝置. 剖面構造之剖面圖。 、之 圖12係表示於圖1丨之半導體裝置之製造工序之一例之剖 面圖。 圖13係接續圖12之工序剖面圖。 圖I4係接續圖13之工序剖面圖。 圖1 5係接續圖14之工序剖面圖。 圖1 6係接續圖1 5之工序剖面圖。 圖1 7係表示形成T字型之閘電極之例之剖面圖。 圖18係表示關於本發明之第4實施形態之半導體裝置之 剖面構造之剖面圖。 圖1 9係表示圖18之變形例之剖面圖。 105662.doc * 16 - 1375327 【主要元件符號說明】 1 矽基板 2 PMOS電晶體 3 NMOS電晶體 4 閘絕緣膜 5a, 5b, 5c, 5d, 5e, 5f 閘電極 6a, 6b 通道區域 12 鎢膜 21 第1金屬層 22a, 22b 第2金屬層 23 TiN 27 阻障層 28a, 28b 鎢膜
105662.doc
Claims (1)
- 第094136596號專利申請案 中文申請專利範圍替換本(101年5月) 十、申請專利範圍: 1. 一種半導體裝置,具備: 絕緣層,其形成於矽基板上; 第1導電層,其係形成於上述絕緣層上;及 金屬層,其係形成於上述第1導電層上; 上述金屬層,具有植入雜質而形成之具有與其他區域 相異應力之應力變化區域,上述應力變化區域構成至少 一部分閘電極。 2. 如請求項1之半導體裝置,其中 上述第1導電層構成至少一部分閘電極, 上述第1導電層,決定上述閘電極之功函數, 上述應力變化區域,控制於上述閉電極下方之上述矽 基板内形成之通道區域的應力。 3. 如請求項2之半導體裝置,其中 上述應力變化區域及上述通道區域之任一方具有壓縮 應力’另一方具有拉張應力。 4. 如請求項1之半導體裝置,其中 上述金屬層,具有: 第1導電區域,其係形成第1導電型M〇s電晶體者;及 第2導電區域,其係形成第2導電型M〇s電晶體者, 上述應力變化區域,係上述第丨或第2導電區域。 5·如請求項1之半導體裝置,其中具備 阻障層,其係形成於上述第丨導電層及上述金屬層 間, 105662-1010504.doc 1375327 上述第1導電層係矽層。 6·如請求項1之半導體裝置,其中具有: 阻障層’其係形成於上述金屬層上;及 石夕化物層’其係形成於上述阻障層上。 7. 如請求項1之半導體裝置,其中 上述應力變化區域’具有壓縮應力或拉張應力之一 方》 8. —種半導體裝置之製造方法, 係於矽基板上形成絕緣層, 於上述絕緣層上形成第1導電層, 於上述第1導電層上形成金屬層, 上述金屬層,具有植入雜質形成而具有與其他區域相 異應力之應力變化區域,上述應力變化區域構成至少一 部份閘電極。 9. 如請求項8之半導體裝置之製造方法,其中 上述第1導電層構成至少一部份閘電極, 上述第1導電層’決定上述閘電極之功函數, 上述應力變化區域,控制於上述閘電極下方之上述矽 基板内形成之通道區域的應力。 10. 如請求項9之半導體裝置之製造方法,其中 上述應力變化區域及上述通道區域之任一方具有壓縮 應力’另一方具有拉張應力。 11. 如請求項8之半導體裝置之製造方法,其中 於上述金屬層,設有:第1導電區域,其係形成第1導 105662-1010504.doc 1375327電型MOS電晶體者;及第2導電區域 型MOS電晶體者, 其係形成第2導電 上述應力變化區域,係上述第1或第2導電區域 12. 如請求項8之半導體裝置之製造方法,其中 ,於上述第1導電層及上述金屬層間形成阻障層 上述第I導電層係矽層。 13. 如請求項8之半導體裝置之製造方法,其中於上述金屬層上形成阻障層, 於上述阻障層上形成石夕化物層。 14·如請求項8之半導體裝置之製造方法,其中 上述第1導電層及上述金屬層係使用鑲嵌製程形成。I05662-I010504.doc
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US20070108529A1 (en) * | 2005-11-14 | 2007-05-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained gate electrodes in semiconductor devices |
US8101485B2 (en) * | 2005-12-16 | 2012-01-24 | Intel Corporation | Replacement gates to enhance transistor strain |
WO2008038346A1 (fr) * | 2006-09-27 | 2008-04-03 | Fujitsu Limited | Dispositif semiconducteur et son procédé de fabrication |
WO2008096587A1 (ja) * | 2007-02-07 | 2008-08-14 | Nec Corporation | 半導体装置 |
JP5222583B2 (ja) * | 2007-04-06 | 2013-06-26 | パナソニック株式会社 | 半導体装置 |
US7960243B2 (en) * | 2007-05-31 | 2011-06-14 | Freescale Semiconductor, Inc. | Method of forming a semiconductor device featuring a gate stressor and semiconductor device |
EP2061076A1 (en) * | 2007-11-13 | 2009-05-20 | Interuniversitair Micro-Elektronica Centrum Vzw | Dual work function device with stressor layer and method for manufacturing the same |
JP2010073985A (ja) * | 2008-09-19 | 2010-04-02 | Toshiba Corp | 半導体装置 |
JP2011029303A (ja) * | 2009-07-23 | 2011-02-10 | Panasonic Corp | 半導体装置及びその製造方法 |
US20110147804A1 (en) * | 2009-12-23 | 2011-06-23 | Rishabh Mehandru | Drive current enhancement in tri-gate MOSFETS by introduction of compressive metal gate stress using ion implantation |
JP5569243B2 (ja) | 2010-08-09 | 2014-08-13 | ソニー株式会社 | 半導体装置及びその製造方法 |
US8461034B2 (en) * | 2010-10-20 | 2013-06-11 | International Business Machines Corporation | Localized implant into active region for enhanced stress |
CN103367155B (zh) * | 2012-03-31 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Nmos晶体管及mos晶体管的形成方法 |
FR2995135B1 (fr) * | 2012-09-05 | 2015-12-04 | Commissariat Energie Atomique | Procede de realisation de transistors fet |
US9355888B2 (en) | 2012-10-01 | 2016-05-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Implant isolated devices and method for forming the same |
US9673245B2 (en) | 2012-10-01 | 2017-06-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Implant isolated devices and method for forming the same |
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JPH09246394A (ja) * | 1996-03-01 | 1997-09-19 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP2910836B2 (ja) * | 1996-04-10 | 1999-06-23 | 日本電気株式会社 | 半導体装置の製造方法 |
KR100265350B1 (ko) * | 1998-06-30 | 2000-09-15 | 김영환 | 매립절연층을 갖는 실리콘 기판에서의 반도체소자 제조방법 |
US6221735B1 (en) * | 2000-02-15 | 2001-04-24 | Philips Semiconductors, Inc. | Method for eliminating stress induced dislocations in CMOS devices |
JP2002093921A (ja) * | 2000-09-11 | 2002-03-29 | Hitachi Ltd | 半導体装置の製造方法 |
JP4831885B2 (ja) * | 2001-04-27 | 2011-12-07 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
US6919251B2 (en) * | 2002-07-31 | 2005-07-19 | Texas Instruments Incorporated | Gate dielectric and method |
JP2004172389A (ja) * | 2002-11-20 | 2004-06-17 | Renesas Technology Corp | 半導体装置およびその製造方法 |
US6872613B1 (en) * | 2003-09-04 | 2005-03-29 | Advanced Micro Devices, Inc. | Method for integrating metals having different work functions to form CMOS gates having a high-k gate dielectric and related structure |
US7183182B2 (en) * | 2003-09-24 | 2007-02-27 | International Business Machines Corporation | Method and apparatus for fabricating CMOS field effect transistors |
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