TWI375268B - Selective etching of carbon-doped low-k dielectrics - Google Patents
Selective etching of carbon-doped low-k dielectrics Download PDFInfo
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- TWI375268B TWI375268B TW093122683A TW93122683A TWI375268B TW I375268 B TWI375268 B TW I375268B TW 093122683 A TW093122683 A TW 093122683A TW 93122683 A TW93122683 A TW 93122683A TW I375268 B TWI375268 B TW I375268B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/963—Removing process residues from vertical substrate surfaces
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
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- Plasma & Fusion (AREA)
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Description
1375268 九、發明說明: 【發明所屬之技術領域] 本發明是有關於—種半導體製程技術,且特別是 於一種在低介電常數材料層中蝕刻圖案之方法。 【先前技術】 高操作速度的半導體元件通常會受到金屬線 延遲效應T=RC的限制’其中R是金屬線的電阻值, 是金屬線周圍的介電絕緣材料的電容值。隨著積體電路之 特徵尺寸持續的縮小’金屬線將會變得更薄且更為密集, 因而導致金屬線的電阻值升高且會使電容值升高,因此 使得延遲時間更長。透過改變*同材料之方式,例如伟 用高導電㈣材料以作為金屬線且使用低 作為絕緣材料’元件尺寸的縮小就不 =以 因此在許多半導體先件製程的後段製程中,已經=以 電常數材料(例如是有機赠_)來取⑽以及氧 後數材料取伽氧切這樣的改變對於 it ^ 許多的基礎原則的改變。由娜 =呈。銅鑲,/雙重鑲嵌製程是先在絕緣材料中蝕刻出鑲介層 二以及溝渠’之後再將銅填人介層洞以及溝渠内且回研^ h以使導電材料㈣在介層取及溝渠I在此製程所 j到的挑戰之中,在低介電常數材料中_出介層洞以 及溝渠可歧料雜祕的,妓目為顺帛 14353pif 5 Ϊ375268 此,數,二使:f種低介電常數材料。因 碳、氫、,,數 同材::層1二二層比:刻速率對靖近的不 蝕刻製程中,光阻層會用刻選擇比。通常在 隨著特徵尺寸的縮小,光電常數材料的罩幕。 應因小尺寸所造成的彳 、旱又也會隨著縮小,才能因 阻層而言必須挑戰。而對於薄的光 於許多低介電常數才才“ 選擇比。然而,由 難以達_刻選擇比 ’因此將使得光阻層 刻製程,低介電常數材料_:=目=傳統的介電餘 以及製程參數的搭配而更加的精=擇比㈣由製程化學物 蝕刻低介電常k材料的另月。 以及爛特徵_(介層祠 於圖案密度 電常數材料的蝕刻逮率問:渠)的尺寸而引發的低介 (micr〇I〇ading),或是微負載。齡、虫刻速率微負載 同尺寸的圖針_刻迷^ 微負載指的是在不 的蝕刻速率與在小的圖 '、’,、係為在大的圖案中 的钱刻速率)之_差異的百八料率(除以在大的圖案中 載,、會隨著小尺寸圖案的二比:缩::丄主意的是’微負 兩寬比的增加而增加。 、’’ 乂及小尺寸圖案的 【發明内容】 本發明之目的是提供-種低介電常數材料之_製 14353pif 私J匕製私磁目可改善習知低 “吊$材料層勒刻製程微負載(micr〇j〇wi_n_g_).之間題。在- 發明-實施例中,低介電常數介電層係形成在基底上, 二=為轉/襯層’上層為光阻罩幕。基底係置於一電黎 二室中’錢爛室中係提供—氣體混合物之電浆,以 巧财電常齡電層。上賴難體混合物包括包括一 二,的亂碳氣體或氫氟碳氣體、—含氮氣體以及—或多種 二加^體。其中’多氟的氟碳氣體或氫氟碳氣體例如是 4、C2F8、CHF3、C2f6 #,含氮氣體例如是&、邮、 添加氣㈣如是—錢的魏錢體、—惰 體及/或一碳·氧氣體。 易懂為之上述和其他目的、特徵和優點能更明顯 明如下。特+祕貫施例,並配合所_式,作詳細說 【實施方式】 有刻製程用於蝕刻低介電常數材料層時1 速表,且其相對於上方的罩幕層以及底下的 "手/襯層具有㈣刻選擇比。詳細的說明如 低ί電常數材料層未被罩幕層覆蓋 且有二的氣體中’其例如是電聚,其包括 /、有此里以及反應性的物質。此電漿通常是在 =成,:t是在-磁力增益型反應性離子心 反應至,或疋雙頻電容電漿源蝕刻反應室,里 CENTURA®半導體晶圓製㈣統的—部分,其係可由 14353pif 1375268
Applied Material Inc·,Santa Clara,Calif 取得。 低介電常數材料層通常是形成在一基底上,且使用定 義有特徵圖案的罩幕來触刻而將其圖案化。圖1是依照本 發明一較佳實施例之一晶圓100之剖面圖,其具有特徵圖 案101,其例如是位於基底150上的一低介電常數材料層 120内的溝渠或是介層洞,且圖丨為進行一低介電常數材 料層之钱刻製程到一半的時候’特徵圖案1〇1的側壁1〇5 以及底部表面1 〇6已經因|虫刻製程而被暴露出來。圖案化 的罩幕層110係部分的覆蓋住介電層12〇且定義出特徵圖 案101之開口。在一些應用中,介電層120與基底之間會 透過阻卩早/襯層丨30分離開來。金屬線(未繪示)可能會位於 阻障/襯層之底下。在一些應用中,阻障/襯層130可作為 金屬線與介電層12〇之間的擴散阻障層’並且在蝕刻介電 層丨2〇之過程中作爲一蝕刻終止層。 在本發明之一實施例中,介電層120包括一低介電常 數材料,其介電常數是低於氧化矽(Si〇2)的介電常數,氧 化石夕的介電常數約為4G。另外,低介電常數材料層 ,厚為0.4〜1.5微米。在蚀刻之前的罩幕層11〇的厚 又瓜疋1930埃,而阻障襯層13〇的厚度通常是數百埃。 上述膜層並未以實際比例繪示於圖中。 圖2是繪示MERIE反應室2〇〇之剖面示意圖,其係 f用於執行本發明之製㈣—反應室實例。反應室200包 腔室210 ’其係由一側壁212、一基部214以及一頂部 60所構成。腔室包括位在中間的一製程區2〇1,其所涵蓋 14353pif
S 1375268 的體積約為5,000至50,〇〇〇 cm3。反應室200更包括一製 程氣體供應器220,其係用以提供氣體以使氣體經一氣體 歧管262進入腔室210内,以及一氣體分配盤(GDP)264, 其係位於腔室210的頂部260,因此形成製程氣體。用盡 的氣體或揮發性的蝕刻產物,係藉由泵240而排出製程腔 室210外。另外,節流閥245係控制腔室210内的壓力。 而側壁212、基部214、頂部260以及GDP 264 —般都是 用銘所製成’其係藉由電鍍鋁於腔室210之内表面。側壁 212、基部214、頂部260以及GDP 264通常是接地。 腔室210更包括基座230 ’其係用以支撐腔室200内 的基底300。基座230係藉由一支撐環232而與基部214 電性隔離,且基座230會藉由一阻抗匹配網路255而連接 至一射頻(RF)電源供應糸統250。基座230包括一靜電吸 附極、一真空吸附極或是其他晶圓固定機構(未繪示),且 可以與一基底溫度控制系統(未繪示)熱連結。基底溫度控 制系統例如是阻抗熱線圈及/或連結至一加熱或冷卻流體 系統的流體通路,其係於電漿製程期間有利於控制基底 150的溫度。 控制系統280係包括一 CPU 282、一記憶體284以及 支持電路286,支持電路286係用以使cpu 282耦接至反 應室200的各種組件,以控制本發明之蝕刻製程。 圖2所繪示之反應器係用於反應性離子蚀刻(rie)製 程’其中電毁的產生是藉由以刚〜3_ Watts的電源施 加RF電壓至基座230,且將側壁212以及頂部26〇接地來 14353pif 9 ^75268 達成。當開啟RF電源250,基座230係作為—陰極電極, 而接地的側壁232、頂部260與GDP 264係—同作為一陽 極電極。而藉由電容祕RF電源便可以於陰極盘陽極電 極之間產生電漿且維持電聚。而實質DC偏屋一般會存在 於電漿與陰極電極之間,以使具能量的離子轟擊基^。 一圖2僅繪示可以實作本發明之多種電漿反應^的其中 一實例。例如,反應室200可以包括其他的額外電源&是 取代RF電源250 ’且電源可以耦接至腔室21〇,透過不同 的耦接硬體,其例如是習知已知的硬體,且為不會影響本 發明之應用的硬體,以產生電漿且維持電漿。例如,^有 兩f分離的電源供應器、一源極電極以及一偏極電源的反 應室,亦可以用於本發明。源極電源可以是RF電源,其 係施加電源至一誘導線圈以誘導耦合能量至電漿,而偏^ 電源是另一個RF束源電源,其係施加電源至一支持基座 以相對於電漿而偏壓基底。另外,源極電源可以是非常高 頻率(VHF)(例如是5〇〜250 MHz)電源’其係施加電源至一 線圈電極,而偏極電源可以是一 RF電源,其係施加電源 至面對線圈電極的晶圓支撐基座,反之亦然。 圖3是繪示依照本發明之另一較佳實施例,其包括使 用兩分離開來的電源供應器的反應室3〇〇、RF偏極電源供 應器350以及VHF源極電源供應器370。反應室300包括 真空腔室301,其係由一圓柱壁305以及一導電線圈362 所構成。在本發明之一實施例中,真空腔室;301之壁305 疋以鋁所製成,且為接地。壁3〇5的内表面3〇6與外表面 14353pif 10 3電免義。另外’晶圓支撐基座或是底部 真空腔室301的底部,且支撑基底⑼。 開來,且5疋藉由絕緣環316而與腔室壁3〇5隔離 RF 會維持真空腔室301内的真空度。 #嗥;+ Φ源供應a 35G與VHF源極電源供應器370 持美庙m電極其中之―、底部電極315,其亦是晶圓支 ㈣電極36G。底部f極是透過阻抗匹配網路 連接至RF偏極電源供應器350。頂部電極360 線圈362接觸’當開啟時,會透過阻抗匹配網路 而,接至源極電源供應器370。在本發明之一實施例 中’頂部電極亦可以是氣體分配盤(GDP),且其具有間隙 或孔洞’以允許製喊體流進腔f 3G1内。為了此目的, 在導電板362與頂命電極遍之間係提供有一間隙施, ^作為祕至—氣體供應器340之-氣體分配歧管。支撐 裒366係支撐頂部電極36〇且使頂部電極360與真空腔 壁305絕緣。 … 在本發明之一實施例中,偏極以及源極電源供應器 350、370之頻率分別是13.5 MHz以及60 MHz。且使用過 濾之方式以減少兩個RF電源供應器之間的干擾。在本發 明之—貫施例中’上述過濾的方法是利用匹配網路375内 的一誘導器’其係於13.6 MHz而接地至頂部電極360,其 顯現出對於60 MHz訊號的高阻抗。同樣的,亦可以在匹 配電路355中使用一電容器以於60 MHz而接地至頂部電 14353pif 11 極360’其顯現出對於13.6 MHz訊號的高阻抗。因此,兩 個RF電源350、370可以分別控制,以使來自源極電源370 以及由偏極電極350搞合至真空腔室301的相對電源量可 以依照想要的值來分配。一般而言,VHF源極電源37〇係 控制電漿密度,這是因為高效率的置換電流以及鞘加熱機 構係與較高的RF頻率有關。來自偏極RF電源35〇的低頻 激發則是控制基底的偏壓或是轟擊晶圓15〇的離子的能 i。因此,反應室300可以允許分開的控制電漿密度以及 基底偏壓。 在本發明之一實施例中,反應室300的操作是藉由一 控制器380來控制,控制器380包括一 CPU 382、一記憶 體384以及用於CPU 382的支持電路386,且記憶體384 内係存有程式指令。控制器380是辆接至反應室3〇〇的多 個構件,以控制本番明之蝕刻製程。 無論使採用反應室200或是反應室300、腔室210或 是腔室301來執行本發明之蝕刻製程時,都會使用泵24〇 或325將壓力降低至約1 mT〇n^之後,基底〗5〇將從保 持在接近真空狀態的載入轉移腔室(未繪示)移至腔室21〇 或301中’並將其放置在基座230或315上。接著氣體成 分將以各種體積流速通入腔室201或301以形成製程氣 體。當腔室210内的壓力穩定在一預定程度時,開啟電源 250或370以於製程區201或302中形成製程氣體電漿。 當使用反應室300時,可以開啟偏極電源350並且調整至 一預定程度以於基座315與電漿之間形成一預定偏壓。提 14353pif 12 1375268 高電漿密度之方法,電漿密度係定義為每單位體積的離子 數目,可以藉由在腔室壁212之周圍放置磁控裝置270以 在腔室210或301内提供一緩慢旋轉磁場之方式而達成。 磁控裝置可以是藉由低頻(〇.1_〇 5 Hertz)相AC電流源驅動 的電磁控裝置(未繪示)。另外,磁控裝置可以是固定在支 撐結構(未繪示)上的永久磁控裝置,其係以例如每秒 0.1-0.5轉的轉速旋轉。 含氟碳或氫氟碳氣體的電漿通常會用來蝕刻氧化 矽。氟碳或氫氟碳氣體會在電漿中貢獻氟和匚匕物質,且 蠢 其會在介電層120中破壞Si-Ο鍵。 2CF2 + Si〇2 SiF4 + 2C〇 其中姓刻產物SiF4以及c〇皆會揮發,因此可以將其抽出 腔室210外^時’一些化物質㈣小^可能會彼此 再結合或是於介電層反應之前與其他物質產生再結合,而 在特徵圖案之表面形成聚合物保護沈積物。由於特徵圖帛 的侧壁1〇5相較於特徵圖案的底部1〇6遭到電聚的離子爲 , 擊較少’因此這些保護沈積物會加速累積在特徵圖案的側 壁1〇。5 ’而促進非等向㈣^事實上,傳統在钱刻介㈣ . 之過程中’其例如是氧化碎薄膜,CFX物質往往被認為是 達到非等向钮刻輪扉的重要因素。因此用來飯刻氧化石夕薄 膜的許多飯刻化學物質都會使用氟碳氣體,其碳對氟的比 例相對較〶’其例如是C2f6、C4F6料,以提供足夠的保 14353pif 13 1375268 護沈積物來保護側壁。 一般所使用的氟碳氣體,其碳對氟的比例相對較高, 但卻往往導致低的姓刻速率以及高的微載效應 (microloading)。本發明之發明人發現,當蝕刻摻雜碳或低 介電常數材料層時,低介電常數材料層内的碳允許使用多 氟的碳氟氣體或氫碳氟氣體,其例如是具有相對低碳對氟 比例的碳氟氣體或氩碳氟氣體。多氟的碳氟氣體或氫碳氟
氣體的實例包括CF4、C2Fs、CHF3等等,較佳的是CF4。 由於在使用多氟的碳氟氣體或氫碳氟氣體蝕刻過程中,從 低介電常數材料層釋放出來的碳能夠保護侧壁,其特別是 具有相對高碳含量(超過8%碳)的低介電常數材料層。因 此二,低介電常數材料層的蝕刻製程中使用多氟的碳氟氣 ,或氫碳氟氣體時,對於低介電常數材料層有較高的蝕刻 、、率:T阻罩幕’有較佳的選擇比且有較少量的微負載。 ^^低’1電⑦數材料層320具有越複雜的成分通常需要
化學物成分。對於含有烧基,其例如是 氮二,氧化石夕薄膜的低介電常數材料層而言,含 的衝擊可以幫Μ·™3鍵的破壞,而且不會進一步 示’在以;光阻層的蝕刻選擇比。如圖4Α以及圖4Β所 程氣體㈣程氣體或是在以❿/哪3為主的製 蝕刻速率。* %,可以使明顯的提高低介電常數材料層之 會包括八=因,,在本發明之一實施例中的製程氣體通常 i中# 之氣體。適合的含氮氣體包括n2、nh3、nf3, '吊用的是N2。圖4A以及圖4B都顯示出,當N2 : 14353pif 14 CF4或是N2 : OVCHF3的體積流速比例 過0.4或0.3 fl寺,低介雪受叙一 、 ”在超 降。因此N二=:c=的,率都開始下 範園會根攄特殊的應用而有所不4同。3的4比例的最佳 除了多氟的碳氟氣體或氫碳氟氣體以 卜:=通常還包括了-種或多種的添加氣體= 加入可以在關魏中提供氫或是含氫自由基,而當與^ 或含氮自由基結合時’將會加快&偶鍵的破壞,進而提 向钮刻速率以及對於光阻的银刻選擇比。適合的含氫氣體 包括多氫的氫氟碳氣體,其例如是CH2f2、哪3等等。若 在製程氣體中有使用含氮氣體以及含氫氣體時,飯刻反應 包括: 〜
Si-CH3 + H- + Si-CH,以及 Si-CH + F* + N* SiFx + CaH^Nr 其中a、/S以及γ為整數,且蝕刻產物CaI^NT —般為揮 發性。而其他來自電漿與低介電常數材料層之間的作用而 可以形成的副產物包括CO、CN、NHX、NFX、HF、c H2 等等。 X X 3 2 以多氫的碳氟氣體作為含氫氣體的加入可以使得製 程裕度加寬,因此能改善蝕刻速率微負載效應以及橫越基 底的蚀刻均勻度。如圖5A所示,當於以CF4為主的電聚 I4353pif 15 中加入CH2F2氣體時’姓刻速率微負载效應會快速的降
低,=的製程裕度變得更寬廣。改善的製程裕度可以H 由因夕虱鼠灰氣體的加入而導致好的姓刻均勻度而獲得證 實1如圖5Β所示,其係繪示當使用CF4/N2/CH2F2製程= 越300mm的基底上的一低介電常數材料層的蝕 句度。當然’在圖5A中,卿2氣體的加人,飯 二右明/急速的增加’且其對於光阻罩幕_刻選擇比 也有月,.肩的改善。但是,者: 、, ^. 4ηΓ〇ηλ'!Τ/4 圍會,特殊的應用而有所不同。 特徵圖案的_。^可=氣體可助控制被⑽的 賴體大部分會撞擊二:二== 106,而增進該矣而ν ^ 了1又口系川1的底部表面 壁1〇5僅有微小的景,反f =而且其對於特徵圖案的側 ,濺4而使特徵圖案表面的蝕刻產物被濺墼下 氣,其中較佳的是氩氣括⑽、乳氣、乃'氣、山气氣以及氡 石反-氧氣體的加入可 比,阻障/襯層通常包善對於阻障趣層的韻刻選擇 是CO。 夕妷化物材料。適合的碳-氧氣體 括用流速與許多的因素有關,其包 _中所使用的特定氣體?=體== 14353pif 1375268 積流速比例可以依據不同的材料組合以及達到想要的特定 蝕刻選擇比、蝕刻速率或是特徵圖案幾何來定出,本發明 並未限定其範圍。在本發明之一實施例中,當製程氣體包 括CF4以作為碳氟氣體、N2以作為含氮氣體以及CH2F2以 作為多氫的氫氟碳氣體時,N2 : CF4的流速比例約為1 : 4 至2 . 1,且CHA : CF4的流速比例約為丨:3至1 :卜 通常是1 : 3至1 : 2。相對高體積流速的惰性氣體可以得 ,,佳的輪廓。在本發明之一實施例中,當製程氣體包括 氬氣以作為惰性氣體時,氬氣對碳氟氣體的流速比例是介 於 20 : 1 至 50 : 1。 實例 以下之實例係樯述使用本發明之方法以蝕刻基底 上的低介電常數材料層120。基底15〇之實例例如是具有 200 mm(8英对)或是30〇mm (12英,直徑的石夕晶圓。^圖 1所示,晶圓150上係覆蓋有厚度為數百埃的阻障/襯層 130、厚度為0.4〜1.5微米的低介電常數材料層12〇以及 約腦埃的罩幕層110,罩幕層11〇係圖案化以用於蚀刻 定義的特徵圖案101。 在以下的實例中,罩幕層是光阻,其例如 是”RIST〇N”,其係由 duP⑽ de Nem〇urs Chemicai
Company所製造。低介電常數材料層包括摻雜碳的介電材 料,其例如是摻雜CH3之有機矽酸玻璃(〇SG)、有機聚合 14353pif 17 1375268 物(例如是苯環丁烯、聚對二甲苯'聚四氟乙烯、聚醚、聚 醯亞胺)或是摻雜有碳為主的雜質(例如是CH3)的類似物。 OSG有時候指的是摻雜的二氧化矽,其例如是mack Diamond™ I 以及 Black Diamond™ Π,Black DiamondTM π 是 Black Diamond™ I 的改良’其相較於 Black Diam〇ndTM i 具較高的碳含量。Black Diamond™ I 以及 Black Diam〇nd™ II 皆可由 Applied Material Inc” Santa Clara, Calif 取得。其 他的OSG之實例是Corai™,其係來自N〇vdlus 〇f — 了⑽,
Calif ’ 以及 Sumika Film™,其係來自 Sumit〇m〇 Chemical φ
America,Inc.,Sanra Clara,Calif。在 Black Diamond™ I 的 實例中,OSG是採用化學氣相沈積製程以氧化曱基矽烷而 形成,其係揭露於Yau等人之專利us 6 〇54 379以及us 6,072,227。在此材料或相關材料中的甲基自由基的數目在 一單石夕烧中可以是I至4個。 阻障/襯層是BLOk™(阻障低介電常數材料)膜層,其 係為以化學氣相沈積法(CVD)或是電漿增益型CVD所幵j 成之矽碳化物膜層,其揭露在US 6,287,990 βΐ,2001年9 月η日公告以及us 6,3〇3,52皿,2〇01年1〇月1δ日公 · 告。BLOk™ 膜包括 BLOkTMI 以及 BLOkTMIl,BLOkTMII · 是 BL〇k™M 1 的改良,兩者皆可由 Applied Material Inc., ‘
Santa Clara,Calif取得。在阻障/襯層之底下還可以形成有 其他材料層,但其必須不會會影響本發明之實作。 一薄的抗反射層(600埃XARC)或是底部抗反射層 (barc)(未蟓示)’以及一硬罩幕層可以形成在罩幕層3ι〇 14353pif 18 1375268 以及OSG層320之間。當小特徵圖案尺寸發展至〇 25微 米以下時’ ARC(B ARC層)通常在微影製程中用來控制線/ 寬度’傳、统ARC(BARC的钱刻製程的執行會在侧低 介電常數材料層之前清除特徵圖案之開口處的 ARC(BARC層)。而硬罩幕層之材質通常是介電材料,其 例如是二氧化碎,且其於鑲嵌或雙重鑲嵌結構的製程中可 作為後續⑽製程的終止層。傳統硬罩幕層之酬製程 會在酬低介電常數㈣層之前進行以雜位於特徵圖案 開口處的硬罩幕層。 圖6是依據本發明之兩實施例於圖2之反應室屬或 是圖3之反應室300内钱刻低介電常數材料们2〇的製程 流程600。流程_包括—選擇的步驟_,此步驟係開啟 磁控裝置270 ’以在製程腔室21〇或3〇1内晶圓基底15〇 之上方產生磁場。itUi程6GG更包括步驟6G4,其係設定 :曰圓之1度(或陰極的溫度且藉由控制例如是氦氣背部 氣體流來保持溫度在一特定的值。 晶圓的溫度必須保持在足夠高的溫度以使大部分的 姓刻產物可以揮發,且必須足夠低,以使保護沈積物以及 ㈣產物沈積物可轉留在新_的舰圖案⑼的側壁 15=。腔室壁212或3〇5也需維持在一控制的溫度,其 例如疋攝氏15度’其剌用傳統冷卻或加熱機構以維持腔 室壁的溫度。 程序_更包括步驟606,其係透過氣體分配盤264 或360供應製程氣體至製程腔室21〇或3〇1内。程序6⑻ 14353pif 19 1375268 更包括步驟608 ’其係透過調整至少一製程參數’其例如 是一種或多種氣體成分的流速,或是調整節流閥225或325 的位置,來調整腔室210或301内的壓力
當使用反應室300時,程序600更包括步驟610,其 係利用VHF源極電源370點燃製程腔室301内的製程氣體 以形成電漿’其係透過VHF源極電源37.Q對頂部電極306 施予電源。之後或是在點燃電漿的同時,在程序600的步 驟612中’開啟Rj偏極電源35〇以電性偏壓晶圓支撐基 座。當使用反應室200時,步驟610至步驟012係為開啟 RF電源250 ’以點燃製程腔室21〇内的製程氣體,並且偏 壓晶圓支撐基座。 程序600更包括步驟614,其係使用電漿152蝕刻^ 電層120,以形成多個特徵圖案,其包括介電層12〇中白 特徵圖案ΗΠ。在本發明之一實施例中,步驟614是餘亥 Diam〇ndTM ’其對於BL〇kTM的選擇比約為川: 其對於光阻罩幕的選擇比是5: 1或更高。步學
測技術二2時:之Ϊ或終止之後,使用傳統光學終點1 個特^ 其係透過監控來自電漿的放射物,是否多 達到蝕二Ϊ的底部表面(例如特徵圖案101之表面106)泡 中,透止層I30之頂部。之後,在程序600的步驟61< 350而二才二VHF源極電源370以及/或偏極電源250务 製程氣體°而㈣控裝置27G也可以關閉,且停丘 或3〇1。 〜之後,卸除晶圓且將其移出製程腔室21( l4353pif 20 以上所述之程序600的步驟 進行 例如 一些或所有步驟可以同時進行戋以尚·(照顺序 明之一實施例中,程序600是透==同順序進行。在本發 是圖3之控制器380來執杆,^圖2之控制器2S0或 或384内的裎式指令來執行。j依據儲存在記憶體284 丄卜 木執仃另外,程序600的一些或所 有步驟可以於-硬體中執行,其例如是—特殊應用積體電 路(ASIC)或其㈣式之硬體,或是硬體與軟體的結合。 η表I以及表II綜合了所有的範圍,其例如是最小值以 及最大值’且許多製程參數的實例值是用在圖3之蝕刻反 應室300中’以蝕刻3〇〇mm之晶圓上的低介電常數材料
表I _Urn 製程氣體流 速(seem) •參數 -~--- cf4 最小值 2 最大值 200 實例 20 4 400 40 4 400 40 Ar 500 2000 源極電源(W) ------------ 偏極電源(W) 100 1500 300 2500 200 2000 腔室壓力(mTorr) 60 150 100 晶圓基座溫度(°c) 0 30 20 層 320。 14353pif 21
表II 製程參數 最小值 最大值 實例 製程氣體流 速(seem) cf4 50 80 65 n2 50 200 170 Ar 100 1500 500 CO 0 300 2000 源極電源(W) 0 1000 300 偏極電源(W) 1000 3000 2800 腔室壓力(mTorr) 10 150 30 晶圓基座溫度(°C) -20 40 -10 1375268 表III以及表IV列示出製程參數,其例如是RF電源、 壓力、製程氣體組成物以及流速等等,其係用於蝕刻反應 室200内的300mm的晶圓上的介電層320的一些實例。
表III
製程氣體流速(seem) 壓力 RF 陰極 cf4 n2 Ar ch2f2 (mT) (w) 溫度 實例1 40 20 2000 20 100 2000 15°C 實例2 60 60 2000 30 100 2000 15°C 實例3 60 60 2000 30 100 2000 30°C 14353pif 22 表IV 實例4 cf4 n2 Ar CH3F 」0 20 2000 15 壓力 (mT) RF (W) 2000
陰極 溫度 15°C 卡此i疋使用破蝕刻的測試晶圓的掃瞄式電子顯微鏡 置測蝕刻速率、對於光阻的蝕刻選擇比以及蝕刻 載。表V列示出在表ΠΙ以及1V内的製程參數的 二二里:吉果。如表中所示’本發明之實例對於低介電 刻速率高於_埃/分鐘,且對於光阻的 遊擇比會向於6: 1。
PR選擇比 在開口間隙中 微負載(%) 在小特徵圖案 Ψ
4~1兔量測—~ >8:1 未量測 由於貫際的製程參數,其例如是 體流速等等,合侬攄曰圓电# /坚刀虱 “庇^ 仏圓寸、腔室體積以及用於反應室 内的應體的不同而不同,因此本發明並未關於在此所述 14353pif 23 之製程參數範圍内。 雖然本發明已以較佳實施例揭露如上,然其並非用以 限定本發明,任何熟習此技藝者,在不脫離本發明之精神 t範圍内,當可作些許之更動與潤飾,因此本發明之=護 範圍當視後附之申請專利範圍所界定者為準。x ,、° 【圖式簡單說明】 圖1係繪示在一介電層中之溝渠或介層洞在一 程中間的垂直剖面示意圖。 圖2是依據本發明一實施例之用於低介電常數材料的 钱刻製程的電漿反應室的垂直剖面示意圖。 圖3是依據本發明另一實施例之用於低介電常數材料 的蝕刻製程的電漿反應室的垂直剖面示意圖。 、圖4A之圖表顯示出在低介電常數材料的蝕刻製程中 添加不_加物於A碳為主的電S中所產生的變化。、 圖4B之圖表顯示出在低介電常數材料的颠刻製程中 添加不同添加物於氟碳/氫氟碳混合物為主的電漿甲所產 生的變化。 圖5A之圖表顯示出在改變CH2F2/CF4的流速比例時 的低介電常數㈣祕刻速率、對於光_射彳選擇比以 及微負載的趨勢,其係依據本發明一實施例。 圖5B之圖表顯示出在橫越3〇〇 mm基底上的低介電 常數材料,細1均勻度’其係依據本發明—實施例。 圖6是依據本發明一實施例之用於顏刻低介電常數材 料層的製程程序的流程圖。 14353pif 24 1375268 【主要元件符號說明】 100 :晶圓 101 :特徵圖案 150 :基底 120 :低介電常數材料層 105 :側壁 106 :底部表面 110 :罩幕層 130 :阻障/襯層 200、300 :反應室 210、301 :腔室 212 :側壁 214 :基部 260:頂部 ’ 201 :製程區 220 :製程氣體供應器 262 :氣體歧管 264 :氣體分配盤(GDP) 240 :泵 245 :節流閥 230 :基座 232 :支撐環 214 :基部 255、375 :阻抗匹配網路 14353pif 25 1375268 250 :射頻電源供應系統 280、380 :控制系統 282、382 : CPU 284、384 :記憶體 286、386 :支持電路 350 : RF偏極電源供應器 370 : VHF源極電源供應器 305 :圓柱壁 362 :導電線圈 315 :晶圓支撐基座 316 :絕緣環 360 :頂部電極 368 :間隙 366 :支撐環’ 270 :磁控裝置 14353pif 26
Claims (1)
1375268 第93122683 ^中^利範圍無劃線修正本 叫月十、申請專範圍:
修正曰期:100年9月30日 1. 一種選擇性蝕刻低介電常數材料之電漿蝕刻製 程’其中该低介常數材料之介電常數小於4,該製程包括: 將該低介電常數材料層置於一電漿餘刻腔室中,並於 該電漿蝕刻腔室通入一蝕刻氣體混合物,該蝕刻氣體混合 物包括一多氟的氟碳氣體或氫氟碳氣體、一含氮氣體以及 一多氫的氫氟碳氣體;以及 在該電漿蝕刻腔室中維持該蝕刻氣體混合物之一電 漿,以蝕刻該低介電常數材料層,其中該蝕刻氣體混合物 之電锻·钱刻δ玄低介電常數材料層之钱刻速率係大於4〇〇〇 埃/分鐘。 2. 如申請專利範圍第1項所述之選擇性蝕刻低介電 常數材料之電漿蝕刻製程,其中該多氟的氟碳氣體為 CF4 ’該含氮氣體為Ν2,該多氫的氫氟碳氣體係選自 CH2F2、CH3F及其混合物。 3. 如申請專利範圍第1項所述之選擇性蝕刻低介電 f數材料之電漿蝕刻製程,其中該多氟的氟碳氣體或氫氟 碳氣體係選自cf4、C2F8、CHF3及其混合物。 4·如申請專利範圍第1項所述之選擇性蝕刻低介電 常數材料之電漿蝕刻製程,其中該含氮氣體係選自Ν2、 NH3、NF3及其混合物。 5.如申請專利範圍第1項所述之選擇性蝕刻低介電 常數材料之電漿蝕刻製裎,其中該多氫的氫氟碳氣體係選 自CH2F2、CH3F及其混合物。 14353pif 27 1375268 修正日期:1〇〇年9月30曰 爲第93122683號中文專利範圍無劃線修正本 範㈣1項崎⑼雜⑽低介電 吊數材料之1,倾刻製程,其中在該電祕刻腔室中所通 =::„合物中之該多氟的氟碳氣體嶋碳氣 體的、机速為-第-體積流速、該含氮氣體之流速為一第二 體積流速、該多氫的氫氟碳氣體之流速為—第三體積流速 且該第二體積流速和該第—體積流速之比為1:4至2:i。 7. 如申請專利範圍第i項所述之選擇性餘刻低介電 吊數材料之電漿_製程,其中在該錢㈣腔室中所通 體混合物中該多敦的氟碳氣體或氫敗碳氣體 的^速為-第-_流速、該錢氣體之錢為一第二體 =速、該錢的氫氟碳氣體之流速為—第三體積流速且 該弟二體積流速和該第一體積流速之比為1 : 3至n 。 8. 如中請翻範圍第丨項所述之選擇雜刻低介電 j材料之電⑽刻製程,其中該低介常數材料係形成於 基底上,該基底係置於該電漿蝕刻腔室之基座上,且在 ^祕難室中維持紐職舰合物之«的步驟包 在電容耦合射頻電源至該電漿蝕刻腔室 與該電浆之職生-實f的直流偏壓。从該基座 9. 如申請專利範圍第i項所述之選擇性餘刻低介 j材料之電祕刻製程,其中該低介常數材料係形成於 土底上,該基底係置於該電漿蝕刻腔室之基座上,且維 持該钱刻氣體混合物之電漿的步驟包括: 對該基座上施加一偏極電源;以及 對面對該基座之一頂部電極施加一源極電源,其中該 l^S3pi{ 28 爲第931226簡中文專利範圍無劃線修 正本 修正日期:100年9月30日 _電源之辭大於該偏極麵之頻率。 常數材料之電第丄:所述之選擇性蝕刻低介電 ==:的步驟更包括在該伽腔室 -常數二圍第1項所述之選擇_低介電 一庐〆製程,其中該蝕刻氣體混合物更包括 一h性巩體,該惰性氣體係選自 氡氣及其組合。 、自M L⑽、4氣、 12.如中請專利範圍第u項所述之選擇性 電常=料之電隸刻製程,其巾在該電漿㈣腔室所^ 敎體混合物中之該多氟的氟碳氣體或氫 nr第—體積流速,且該惰性氣體之流速為一^ 二體積“’且該第二體積流速和該第一體 20 : 1 至 50 : 1。 匕马 β 種選擇性_低介電常數材料之電漿餘 程,,、中該低介常數材料之介電常數小於4,該製程勺 將該低介電常數材料層置於一電裝餘刻腔室中I於 該電聚闕腔錢人-烟氣體混合物,該㈣氣體尾人 物包括-多氟的氟碳氣體或氫氟碳氣體、—含氮氣體:: 一多氫的氫氟碳氣體;以及 ' 在該電漿蝕刻腔室中維持該蝕刻氣體混合物之一 聚,以飯刻該低介電常數材料層,其中在該電_刻腔〜 中所通入之該蝕刻氣體混合物中之該多氟的氟碳氣體或^ I4353pif 29 修正日期:100年9月30日 舞第93122683號中文專利範____ = 為:第:體?流速、該含氮氣體之流速為 二7 :'、、該多氫的氫氟破氣體之流速為-第三體 積=、、,且該第二體積流速和該第—體職速之比為卜4 多 2 : 1。 二4二申請專利範圍第13項所述之選_刻低介 電:數材狀«勤,其中該多_氟碳氣體或氣 氣石厌軋體係選自CF4、C2F8、CHF3及其混合物。 15.如申4專利範圍第13項所述之選擇性侧低介 電常數材料之電_刻製程,其中該多氫的氫氟碳氣體係 遽自CH2F2、ch3f及其混合物。 16· —種選擇性蝕刻低介電常數材料之電漿蝕刻製 鹈,其中該低介常數材料之介電常數小於4,該製程包括了 將該低介電常數材料層置於一電漿蝕刻腔室中,並於 該電漿蝕刻腔室通入一蝕刻氣體混合物,該蝕刻氣體混合 物包括一多氟的氟碳氣體或氫氟碳氣體、一含氮氣體以及 一多氫的氫氟碳氣體;以及 在該電漿蝕刻腔室中維持該蝕刻氣體混合物之一電 漿,以蝕刻該低介電常數材料層,其中在該電漿蝕刻腔室 中所通入之該姓刻氣體混合物中之該多氟的氟碳氣體或氫 氟碳氣體的流速為一第一體積流速、該含氮氣體之流速為 一第二體積流速、該多氫的氫氟碳氣體之流速為一第三體 積流速,且該第三體積流速和該第一體積流速之比為〗:3 至 1 : 1。 17_如申請專利範圍第16項所述之選擇性蝕刻低介 14353pif 30 馬第93122683號中文專利範圍無劃線修正本 修正日期:100年9月30曰 ,數材料之電漿_製程,其中該多氟的氟碳氣體或氫 藏碳氣體係選自CF4、c2F8、CHF3及其混合物。 數杈申睛專利範圍帛16項所述之選擇性餘刻低介電常 CHF之電装餘刻製程’其中該多氫的氫氟碳氣體係選自 ' CH#及其混合物。
l4353pif 31
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- 2004-07-29 TW TW093122683A patent/TWI375268B/zh not_active IP Right Cessation
- 2004-07-30 KR KR1020040060613A patent/KR100849707B1/ko not_active IP Right Cessation
- 2004-07-30 EP EP04018095A patent/EP1503405A3/en not_active Withdrawn
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TW200509250A (en) | 2005-03-01 |
KR100849707B1 (ko) | 2008-08-01 |
US7256134B2 (en) | 2007-08-14 |
US20050026430A1 (en) | 2005-02-03 |
KR20050016080A (ko) | 2005-02-21 |
CN100353505C (zh) | 2007-12-05 |
CN1624881A (zh) | 2005-06-08 |
EP1503405A3 (en) | 2005-05-04 |
EP1503405A2 (en) | 2005-02-02 |
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