TWI355733B - Low stress sidewall spacer in integrated circuit t - Google Patents

Low stress sidewall spacer in integrated circuit t Download PDF

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Publication number
TWI355733B
TWI355733B TW094100442A TW94100442A TWI355733B TW I355733 B TWI355733 B TW I355733B TW 094100442 A TW094100442 A TW 094100442A TW 94100442 A TW94100442 A TW 94100442A TW I355733 B TWI355733 B TW I355733B
Authority
TW
Taiwan
Prior art keywords
forming
gate
dielectric
source
layer
Prior art date
Application number
TW094100442A
Other languages
English (en)
Chinese (zh)
Other versions
TW200527649A (en
Inventor
Minh Van Ngo
Simon Siu-Sing Chan
Paul R Besser
Paul L King
Errol Todd Ryan
Robert J Chiu
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of TW200527649A publication Critical patent/TW200527649A/zh
Application granted granted Critical
Publication of TWI355733B publication Critical patent/TWI355733B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/24Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW094100442A 2004-01-12 2005-01-07 Low stress sidewall spacer in integrated circuit t TWI355733B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/756,023 US7005357B2 (en) 2004-01-12 2004-01-12 Low stress sidewall spacer in integrated circuit technology

Publications (2)

Publication Number Publication Date
TW200527649A TW200527649A (en) 2005-08-16
TWI355733B true TWI355733B (en) 2012-01-01

Family

ID=34739734

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094100442A TWI355733B (en) 2004-01-12 2005-01-07 Low stress sidewall spacer in integrated circuit t

Country Status (8)

Country Link
US (1) US7005357B2 (enExample)
JP (1) JP5265872B2 (enExample)
KR (1) KR20060123481A (enExample)
CN (1) CN1902743A (enExample)
DE (1) DE112004002638B4 (enExample)
GB (1) GB2425405B (enExample)
TW (1) TWI355733B (enExample)
WO (1) WO2005071729A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7132352B1 (en) * 2004-08-06 2006-11-07 Advanced Micro Devices, Inc. Method of eliminating source/drain junction spiking, and device produced thereby
KR20080047482A (ko) * 2005-09-23 2008-05-28 엔엑스피 비 브이 반도체 디바이스용 구조체 제조 방법
US7465635B2 (en) * 2006-09-21 2008-12-16 Texas Instruments Incorporated Method for manufacturing a gate sidewall spacer using an energy beam treatment
US7741181B2 (en) * 2007-11-06 2010-06-22 International Business Machines Corporation Methods of forming mixed gate CMOS with single poly deposition

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0766406A (ja) * 1993-08-25 1995-03-10 Oki Electric Ind Co Ltd サリサイド型mosfet及びその製造方法
JPH07254574A (ja) * 1994-03-16 1995-10-03 Sony Corp 電極形成方法
JP2809113B2 (ja) * 1994-09-29 1998-10-08 日本電気株式会社 半導体装置の製造方法
JPH08186085A (ja) * 1994-12-28 1996-07-16 Nec Corp 半導体装置の製造方法
US5814545A (en) * 1995-10-02 1998-09-29 Motorola, Inc. Semiconductor device having a phosphorus doped PECVD film and a method of manufacture
JP3572561B2 (ja) * 1996-10-11 2004-10-06 富士通株式会社 半導体装置の製造方法
US5858846A (en) * 1997-08-04 1999-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Salicide integration method
JP2000133802A (ja) * 1998-10-28 2000-05-12 Nec Corp 半導体装置とその製造方法
KR100313510B1 (ko) * 1999-04-02 2001-11-07 김영환 반도체 소자의 제조방법
US6368988B1 (en) * 1999-07-16 2002-04-09 Micron Technology, Inc. Combined gate cap or digit line and spacer deposition using HDP
US6040223A (en) * 1999-08-13 2000-03-21 Taiwan Semiconductor Manufacturing Company Method for making improved polysilicon FET gate electrodes having composite sidewall spacers using a trapezoidal-shaped insulating layer for more reliable integrated circuits
KR100407684B1 (ko) * 2000-06-28 2003-12-01 주식회사 하이닉스반도체 반도체 소자의 제조 방법
US6483154B1 (en) * 2000-10-05 2002-11-19 Advanced Micro Devices, Inc. Nitrogen oxide plasma treatment for reduced nickel silicide bridging
US6495460B1 (en) * 2001-07-11 2002-12-17 Advanced Micro Devices, Inc. Dual layer silicide formation using a titanium barrier to reduce surface roughness at silicide/junction interface
US6664172B2 (en) * 2002-01-22 2003-12-16 United Microelectronics Corp. Method of forming a MOS transistor with improved threshold voltage stability
US7005376B2 (en) * 2003-07-07 2006-02-28 Advanced Micro Devices, Inc. Ultra-uniform silicides in integrated circuit technology

Also Published As

Publication number Publication date
JP2007518274A (ja) 2007-07-05
DE112004002638B4 (de) 2009-11-26
CN1902743A (zh) 2007-01-24
US7005357B2 (en) 2006-02-28
GB2425405B (en) 2008-08-20
JP5265872B2 (ja) 2013-08-14
WO2005071729A1 (en) 2005-08-04
US20050153496A1 (en) 2005-07-14
TW200527649A (en) 2005-08-16
KR20060123481A (ko) 2006-12-01
DE112004002638T5 (de) 2007-02-01
GB2425405A (en) 2006-10-25
GB0615073D0 (en) 2006-09-06

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees