GB2425405B - Low stress sidewall spacer in integrated circuit technology - Google Patents

Low stress sidewall spacer in integrated circuit technology

Info

Publication number
GB2425405B
GB2425405B GB0615073A GB0615073A GB2425405B GB 2425405 B GB2425405 B GB 2425405B GB 0615073 A GB0615073 A GB 0615073A GB 0615073 A GB0615073 A GB 0615073A GB 2425405 B GB2425405 B GB 2425405B
Authority
GB
United Kingdom
Prior art keywords
integrated circuit
sidewall spacer
low stress
circuit technology
stress sidewall
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB0615073A
Other languages
English (en)
Other versions
GB0615073D0 (en
GB2425405A (en
Inventor
Minh Van Ngo
Simon Siu-Sing Chan
Paul R Besser
Paul L King
Errol Todd Ryan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of GB0615073D0 publication Critical patent/GB0615073D0/en
Publication of GB2425405A publication Critical patent/GB2425405A/en
Application granted granted Critical
Publication of GB2425405B publication Critical patent/GB2425405B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/24—Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
GB0615073A 2004-01-12 2004-12-21 Low stress sidewall spacer in integrated circuit technology Expired - Fee Related GB2425405B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/756,023 US7005357B2 (en) 2004-01-12 2004-01-12 Low stress sidewall spacer in integrated circuit technology
PCT/US2004/043109 WO2005071729A1 (en) 2004-01-12 2004-12-21 Low stress sidewall spacer in integrated circuit technology

Publications (3)

Publication Number Publication Date
GB0615073D0 GB0615073D0 (en) 2006-09-06
GB2425405A GB2425405A (en) 2006-10-25
GB2425405B true GB2425405B (en) 2008-08-20

Family

ID=34739734

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0615073A Expired - Fee Related GB2425405B (en) 2004-01-12 2004-12-21 Low stress sidewall spacer in integrated circuit technology

Country Status (8)

Country Link
US (1) US7005357B2 (enExample)
JP (1) JP5265872B2 (enExample)
KR (1) KR20060123481A (enExample)
CN (1) CN1902743A (enExample)
DE (1) DE112004002638B4 (enExample)
GB (1) GB2425405B (enExample)
TW (1) TWI355733B (enExample)
WO (1) WO2005071729A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7132352B1 (en) * 2004-08-06 2006-11-07 Advanced Micro Devices, Inc. Method of eliminating source/drain junction spiking, and device produced thereby
EP1949416A2 (en) * 2005-09-23 2008-07-30 Nxp B.V. A method of fabricating a structure for a semiconductor device
US7465635B2 (en) * 2006-09-21 2008-12-16 Texas Instruments Incorporated Method for manufacturing a gate sidewall spacer using an energy beam treatment
US7741181B2 (en) * 2007-11-06 2010-06-22 International Business Machines Corporation Methods of forming mixed gate CMOS with single poly deposition

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5814545A (en) * 1995-10-02 1998-09-29 Motorola, Inc. Semiconductor device having a phosphorus doped PECVD film and a method of manufacture
US20020022367A1 (en) * 1999-04-02 2002-02-21 Ji Soo Park Method for fabricating semiconductor device
US6495460B1 (en) * 2001-07-11 2002-12-17 Advanced Micro Devices, Inc. Dual layer silicide formation using a titanium barrier to reduce surface roughness at silicide/junction interface
US20030139025A1 (en) * 2002-01-22 2003-07-24 Tong-Hsin Lee Method of forming a MOS transistor with improved threshold voltage stability

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0766406A (ja) * 1993-08-25 1995-03-10 Oki Electric Ind Co Ltd サリサイド型ｍｏｓｆｅｔ及びその製造方法
JPH07254574A (ja) * 1994-03-16 1995-10-03 Sony Corp 電極形成方法
JP2809113B2 (ja) * 1994-09-29 1998-10-08 日本電気株式会社 半導体装置の製造方法
JPH08186085A (ja) * 1994-12-28 1996-07-16 Nec Corp 半導体装置の製造方法
JP3572561B2 (ja) * 1996-10-11 2004-10-06 富士通株式会社 半導体装置の製造方法
US5858846A (en) * 1997-08-04 1999-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Salicide integration method
JP2000133802A (ja) * 1998-10-28 2000-05-12 Nec Corp 半導体装置とその製造方法
US6368988B1 (en) * 1999-07-16 2002-04-09 Micron Technology, Inc. Combined gate cap or digit line and spacer deposition using HDP
US6040223A (en) * 1999-08-13 2000-03-21 Taiwan Semiconductor Manufacturing Company Method for making improved polysilicon FET gate electrodes having composite sidewall spacers using a trapezoidal-shaped insulating layer for more reliable integrated circuits
KR100407684B1 (ko) * 2000-06-28 2003-12-01 주식회사 하이닉스반도체 반도체 소자의 제조 방법
US6483154B1 (en) * 2000-10-05 2002-11-19 Advanced Micro Devices, Inc. Nitrogen oxide plasma treatment for reduced nickel silicide bridging
US7005376B2 (en) * 2003-07-07 2006-02-28 Advanced Micro Devices, Inc. Ultra-uniform silicides in integrated circuit technology

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5814545A (en) * 1995-10-02 1998-09-29 Motorola, Inc. Semiconductor device having a phosphorus doped PECVD film and a method of manufacture
US20020022367A1 (en) * 1999-04-02 2002-02-21 Ji Soo Park Method for fabricating semiconductor device
US6495460B1 (en) * 2001-07-11 2002-12-17 Advanced Micro Devices, Inc. Dual layer silicide formation using a titanium barrier to reduce surface roughness at silicide/junction interface
US20030139025A1 (en) * 2002-01-22 2003-07-24 Tong-Hsin Lee Method of forming a MOS transistor with improved threshold voltage stability

Also Published As

Publication number Publication date
TW200527649A (en) 2005-08-16
CN1902743A (zh) 2007-01-24
KR20060123481A (ko) 2006-12-01
US20050153496A1 (en) 2005-07-14
GB0615073D0 (en) 2006-09-06
WO2005071729A1 (en) 2005-08-04
TWI355733B (en) 2012-01-01
DE112004002638T5 (de) 2007-02-01
JP5265872B2 (ja) 2013-08-14
US7005357B2 (en) 2006-02-28
GB2425405A (en) 2006-10-25
DE112004002638B4 (de) 2009-11-26
JP2007518274A (ja) 2007-07-05

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20221221